xcore® and RISC-V: a major milestone

Today represents a significant milestone for XMOS, with the announcement that our fourth generation xcore platform will be fully compatible with RISC-V.

Bringing xcore into the RISC-V ecosystem is the culmination of 12 months of work. The adoption of RISC-V represents the latest step on our strategy of using open-source tools – such as TensorFlow and FreeRTOS – to support designers working with XMOS hardware.

It has been a major project for our team, but an important one as we continue to push to make the benefits of the xcore platform as accessible as possible.

Developing the software-defined future

The xcore platform is at the cutting edge of the move to software-defined SoCs, which offer unparalleled efficiency, cost-effectiveness and versatility compared to traditional hardware approaches.

For a fast-moving and fundamentally fragmented market with the intelligent internet of things (IoT), this dynamic flexibility is crucial. With this collaboration we are supporting RISC-V programmers to rapidly realise highly differentiated and economical intelligent IoT solutions by giving them the ability to define entire systems in software.

Crucially, however, the xcore platform now has immediate familiarity and compatibility that comes with being part of the RISC-V community. Using standard RISC-V designs, tools and processes electronics engineers and designers will now be able to use the xcore platform without having to re-engineer their designs or learn new tools or software.

Combined with xcore’s modular design, which allows multiple chips to be combined together to act as one more powerful piece of hardware, these systems can scale as needed. Engineers have a familiar environment within which to control and develop systems that can then grow with the customer.

Of course, the combination of xcore and RISC-V, means that the benefits of XMOS’ technology are also available to a much larger pool of people. This is a big part of why we are so excited about today’s news – by bringing xcore into the RISC-V ecosystem, there is huge potential to accelerate the development of the intelligent IoT.

The start of a journey

XMOS is continuing to deepen the integration of RISC-V with the xcore platform –further developments are already in the pipeline for 2023 and beyond. We are also committed to contributing further to the RISC-V community and toolchain, opening the doors to a host of new customers joining the RISC-V ecosystem.

We will be discussing some of these plans – as well as providing the technical details of the integration to date – at this week’s RISC-V Summit in San Jose. Our CEO, Mark Lippett will be presenting on Tuesday, December 13 at 3:05pm, exploring the way in which software-defined SoCs are redefining the embedded development landscape by using RISC-V programmable threads. CTO, Henk Muller, will then go on to provide further technical detail in his session on Wednesday, December 14 at 4:00pm, where he will examine the xcore multi-threaded RISC-V architecture.

XMOS will also be hosting a stand in the exhibition hall during the RISC-V Summit so do pop by and talk to the team to find out more.

We look forward to seeing you there!

If you would like to find out more about our recent announcement, why not download our whitepaper exploring how RISC-V can be used to define SoCs in software.

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