xcore enables whole DSP systems to be built with the lowest system bill of materials, including significant DSP workloads in both fixed- and floating-point formats. The platform flexibility also enables solutions that integrate other key components, for example IO protocols, control algorithms and even AI. Uniquely with xcore, these entire DSP systems can be built using software alone.
With its unique multi-threaded, multi-core micro-architecture, xcore.ai delivers world-leading predictable programmability, essential for DSP applications requiring hard real-time performance. Each processing resource can be used independently, or in collaboration to solve more demanding problems. xcore’s unique architecture ensures that different parts of the system do not interfere with each other, delivering the robustness, low-latency and guaranteed execution time required by DSP systems, especially those supporting multiple sample rates.
xcore.ai is a unique programmable processor array – each xcore.ai features 16 hardware threads (HART) split between 2 multi-threaded processor ‘tiles’. Each tile is equipped with 512kB of SRAM and an integer vector unit capable of efficient block floating point, enabling every HART to execute a common set of control, DSP, AI and IO instructions. A powerful inter-processor communication infrastructure provides high speed communication between any number of xcore.ai chips. All this, within a single, homogeneous, and powerful development environment.
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The multiple threads available with xcore.ai simplify the integration of DSP functions with hard real time characteristics into a single chip embedded solution.
In addition to the library of fundamental DSP building blocks, XMOS provide a comprehensive set of high-level functions such as: PDM interfaces, acoustic echo cancellation, noise suppression, asynchronous sample rate conversion, automatic gain control and many others. These are packaged as reference applications that can be readily modified and extended to match unique system functionality and interface requirements all within a single, cost-effective device.
- 800 MFLOPS sustained
- 1,600 MFLOPS peak
- 98,561 FFTs/s
11,300 float FFT/s
1,024-Pt Complex FFT (Radix 2)/s
- 957M FIR filter taps/s
- 251M IIR filter (per biquad)/s
Scalability – dedicated XMOS links can be used to connect multi-chip systems and seamlessly extend performance.
XMOS provides a range of xcore.ai development boards with a range of interfaces including: