Physical AI Needs Two Kinds of Compute

The fast brain and the slow brain

Biology solved real-time intelligence long before robotics did, and it did not solve it with one big brain. It used systems running on radically different timescales — and, crucially, on radically different mechanisms.

The second system is slower, more deliberate and expensive. It reasons, plans and revises its model of the world — Daniel Kahneman’s System 2 to the reflex layer’s System 1. It is where understanding lives, and it is far too slow and too costly to keep a body upright.

The decisive engineering fact combines energy and mechanism. The entire human brain runs on roughly 20 watts, and the reflex layer is the cheapest part of it — not because it is a compressed version of the deliberative system, but because it does something categorically simpler: fixed, verifiable, fast responses. Evolution made the fast system fast by giving it less – less to do and less to learn – not more compute.

That distinction – hardwired reflex versus learned deliberation – is the one the current robotics consensus has only half-absorbed, and it has direct consequences for what we should build.

The industry has converged on the split — but only halfway

The fast/slow division is now the default mental model for embodied AI, and the credible teams are explicit that the inspiration is dual-process cognition.

Figure’s Helix uses an explicit System 1/System 2 framing: a vision-language model reasoning about scene and instruction at 7–9 Hz, and a smaller visuomotor policy turning intent into motor commands 20 times faster at 200 Hz.  The January 2026 update, Helix 02, added a faster floor still — “System 0,” a compact network emitting joint-level commands at 1 kHz. NVIDIA reached the same place from a different direction: its GR00T N1 foundation model is a dual-system design “inspired by human cognitive processing (Kahneman, 2011),” pairing a vision-language planner at around 10 Hz with a real-time action module.

None of this is new in spirit. Rodney Brooks made the argument in 1986 with his subsumption architecture, built explicitly against the slow, brittle symbolic AI of the era. Brooks layered control so that the lowest layers behaved like reflexes – cheap, protective, and always live – with higher layers subsuming them only when a goal demanded it; the lower layers kept running regardless.

What the reflex layer actually requires

Strip “determinism” down to the properties that matter. At the reflex boundary, a physical-AI system needs three things that current GPU-class inference struggles to guarantee: bounded worst-case latency under all inputs; verifiable behaviour across the full input space; and fault isolation, so that one failing task cannot impede another.

The reason GPU-class hardware struggles here is concrete rather than rhetorical: non-deterministic memory controllers, OS interrupt latency and thermal throttling all inject jitter into the worst case. You can engineer soft real-time behaviour on such hardware with careful scheduling – that is a fair challenge to the thesis – but a provable worst-case bound under every cache state, contention pattern and thermal condition is genuinely hard on a throughput-optimised part. The reflex layer’s job is to never miss its deadline, and “usually fast” is not good enough for it.

This points to a different class of computation for the reflex layer: deterministic, strongly partitioned, parallel and low-power.

Who actually competes here

This is where the popular framing – deterministic reflex silicon versus the GPU giants – is simply wrong.  The incumbents at the reflex layer are not NVIDIA, they are the microcontroller vendors — NXP, Renesas, TI. FPGAs (Lattice, AMD, Altera) offer comparable determinism and partitioning with more reconfigurability. And the development that most undercuts a naïve “two separate chips” reading is integration: NVIDIA’s Thor already bundles lockstep safety-island cores on the same die as its GPU compute. Industrial robotics, for its part, has run hard real-time control on EtherCAT, FPGA motion controllers and dedicated DSPs for decades; FANUC and Kuka did not wait for a new architecture.

Two clarifications follow.  First, the thesis is about two classes of computation, not necessarily two packages. Thor’s safety island does not refute the split – it *validates* it, then ships it as one SoC. The architectural separation is the real claim; packaging is a design choice driven by cost, power and integration. Standalone deterministic silicon wins where a Thor-class SoC is overkill: low-cost, low-power, heterogeneous edge devices at sub-$5 ASP.  These devices enable retrofits, and reflex compute pushed out into limbs, joints and end-effectors rather than centralised.

Second, the genuine differentiation sits on an axis both incumbents are weak on. Certified MCUs are deterministic but not highly parallel; GPUs are parallel but not deterministic. The opening is for compute that is both — deterministic timing with parallel throughput at low power. That is the niche an architecture such as XMOS’s XCORE occupies: one credible exemplar of the GenSoC class, alongside FPGAs.

The substrate sets the ceiling

It is fashionable to observe that value in semiconductors accrues upward — that Arm is architecturally dominant yet captures only a fraction of what is built on top of it, and that silicon vendors routinely cede margin to Tier-1 integrators and to whoever owns the software. True as far as it goes. But it confuses where margin happens to pool with the properties that the system actually depends on, and at the reflex layer those are not the same thing.

Isolation and timing determinism are not software features that a clever runtime supplies on top of indifferent hardware; they are properties of the hardware itself. Bounded worst-case latency, freedom from interference between tasks, a deadline that holds under every machine state, contention pattern and thermal condition — the silicon either provides these or it does not.  A middleware layer can expose determinism, but it cannot manufacture it where the hardware beneath has already surrendered it to jitter.  Whatever runtime sits above the metal, its best case performance is bounded – exactly and permanently – by the metal.

That is the asymmetry the architecture turns on. A deterministic substrate can always run best-effort work: spend any timing margin on throughput wherever a task does not need the guarantee. The reverse never holds — no scheduler, no real-time executor, no protocol above a throughput-optimised part can reconstruct real-time behaviour the part was never built to honour.

Put simply, you can give away hard real-time behaviour, but you can never get it back. That is why the silicon is not the commoditised floor of this stack; it is the part that sets the ceiling for everything built above it. Biology made the same call half a billion years ago — it did not run the reflex arc as software on the cortex, it built separate, bounded circuitry for it. The open question in physical AI is not who writes the layer above the split. It is who builds the substrate that can hold the deadline — because nothing above it can add that guarantee back once the hardware has given it away.