The xCORE 64-bit accumulator and memory bus
In a previous blog I discussed the new DSP capabilities of the xCORE-200 architecture at a very high level. I'd now like to look at some of those DSP capabilities in more detail.
XMOS xCORE-200 devices are built around a 32-bit fixed point architecture, which includes a 64-bit accumulator for enhanced dynamic range. This architecture was chosen because it gives flexibility to implement many different forms of fixed-point and integer arithmetic efficiently.
In addition to the raw 32/64 bit performance of the xCORE-200, the device family can scale in terms of processor cores and MIPS. At the lower end the 8-core 500 MIPS device (250 MMACS sustained) is ideal for High Resolution stereo audio I/O and processing applications, while the high-end 32-core 2000 MIPS device (1000 MMACS sustained) can support up to 64 channels of time division multiplexed (TDM) audio.
When implementing DSP algorithms it is necessary to have highly optimized access to large amounts of memory. The xCORE-200 includes 256 KBytes to 1 Mbyte on-chip zero wait SRAM that can be accessed by the processors cores through a 64-bit non-blocking tightly coupled memory interface. This allows all processor cores to access the on-chip memory without concern that the processor pipeline will stall while waiting for another core to complete its memory accesses.
The combination of 64-bit accumulator and 64-bit internal memory bus allows rapid load and store of data, coefficients and results. All loads and stores are 64-bit aligned and supported in the compiler. In fact, all global data arrays are 64-bit aligned to allow the compiler to use 64-bit loads and stores where ever possible.
xCORE-200 also incorporates a dual issue instruction set, which allows many of the mathematical operations such as shift and add to be issued in parallel with other instructions such as memory accesses, loop counting and modulo address pointer management. The instruction set also supports instructions for saturation, CRC, and zip/unzip instructions for bit, word and long word manipulation.
The xCORE-200 DSP library released by XMOS, supports all of the above techniques to give hand optimized performance.
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