SILICON

xCORE multicore microcontrollers are available from three device families. All the families are based on the same deterministic architecture and instruction set, making migration between device families easy. You can choose between a wide variety of core, memory and package variations, with pin-compatibility wherever possible giving you the option to flexibly add new features or cost-down existing designs.

• xCORE General-Purpose: our XS1-L and XS1-G devices offer deterministic performance and interface flexibility for digital systems
• xCORE-USB devices integrate a USB PHY for the highest levels of integration.
• xCORE-Analog devices are optimized for industrial applications and include Analog functions including multichannel 12bit ADCs.

Unlike traditional microcontrollers, xCORE devices can handle peripheral functions in software - so you can configure your xCORE device with the exact combination of peripherals and interfaces you require.

Common architecture

Every device is made up of one or more Tiles. There are several types of Tile, but the commonest is the basic processor Tile, which is the key to the deterministic processing, low latency and multicore capabilities of xCORE.

The xCORE processor Tile is itself composed of a number of components:

• xCORE logical processor cores: each tile contains 4, 5, 6 or 8 logical processor cores. The cores can execute computational code, 64-bit precision DSP, control tasks (such as logic decisions and executing a state machine) or software to handle I/O.
• xTIME Scheduler: the scheduler performs the functions of a real-time operating system in hardware. It schedules tasks through the cores, and provides clock and timing functions, with resolution down to 10ns.
• Hardware-Response ports: the key to ultra-low latency I/O. The ports contain high-speed logic, which is controlled directly by the logical cores. The Ports include: clocking logic; comparison logic; time stamping; serialization and de-serialization.
• xCONNECT: a fast crossbar switch that links the Tile resources together. xCONNECT can also be made available "off-tile", allowing tiles - and devices - to be efficiently interconnected.
• SRAM: a unified memory architecture for both program and data, that is shared by all of the cores on the tile.
• JTAG programming and debug interface:
• OTP ROM: specifically designed to help secure your IP