XS1 Port I/O Timing Application Note
Version 1.0
Publication Date: 2010/02/03
Copyright © 2010 XMOS Ltd. All Rights Reserved.

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XS1 Port I/O Timing Application Note (1.0)
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1
Introduction
XS1 devices provide the ability to delay the application clock with respect to incoming
data, to provide a valid data window for sampling data on XS1 ports.
This application note explains how to calculate the valid data windows for an XS1-G4
device and the considerations that need to be taken into account when adjusting the
application clock.
2
Input Timing
The valid data input window for an application is calculated as the sum of the input
setup time and the input hold time with regard to the application clock.
APP_CLK
APP_DATA
T
T
setup
hold
APP_CLK and APP_DATA are sampled each core clock cycle, with the values proceeding
down parallel pipelines. The overall delay applied to each may differ such that
APP_CLK may be moved forwards and backwards with respect to APP_DATA.
The sampling process introduces some positional uncertainty of the sampled version
of APP_CLK (APP_CLK'), so APP_CLK' should be positioned such that is not too near
the leading edge, or the trailing edge, of the data valid window.
APP_CLK' needs to be positioned at least Tsafe away from the leading edge of the
valid window:
XCORE_CLK
Tsafe
APP_CLK
Tcycle
Tpvd
Tocv
APP_DATA_IN
valid
Tsafe is comprised of the following components:
· Tcycle: The first XCore clock cycle which may just miss the APP_CLK or APP_DATA
signal changing.
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· Tpdv: The variability of pad propagation delays primarily due to the difference
in rise and fall delays through the pad, and differences in input slew rate.
· Tocv: The variability of the relative delay of clock and data between the pad and
the first on-chip sampling registers.
Similarly APP_CLK needs to be positioned at least Tsafe away from the trailing edge of
the valid window due to the uncertainty (equal to Tsafe) in its position.
If both constraints are met for a given valid window size and setup/hold time
combination, there is no need for any relative delays to be applied to APP_CLK and
APP_DATA.
If the constraints are not met, however, the clock needs to be moved by Tsafe.
From this the overall valid widow size required for a guaranteed correct operation
can be derived. The worst case scenario occurs where Thold = Tsafe - 0.1. In this
case the clock must be moved one XCore cycle towards the leading edge of the valid
window, yet still remain at least Tsafe away from the leading edge of the window.
Consequently the total width of the valid window required to accomodate all these
constraints is:
Tsafe + Thold + Tcycle
where:
Tcycle = XCore clock cycle plus jitter (for 400MHz operation this is 2.5ns plus 70ps
jitter = 2.57 ns).
Tsafe = Tcycle + Tpdv (900ps) +Tocv (250ps) = 2.57 + 1.15 = 3.72
APP_CLK
T
T
T
safe
hold
cycle
APP_DATA_IN
valid
Therefore the minimum valid window that will guarantee correct operation for any
given initial positioning of APP_CLK in the valid window is (as Thold tends to Tcycle):
Tsafe + 2 x Tcycle = 3.72 + 2.57 + 2.57 = 8.86 ns
Note that smaller valid windows may be possible depending on the required Thold
and Tsetup.
Note also that either the rising or falling edge of the incoming APP_CLK can be used
to generate the rising edge of APP_CLK' internally.
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XS1 Port I/O Timing Application Note (1.0)
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3
Output Timing
Output data is launched by a sampled and arbitrarily delayed version of the incoming
APP_CLK signal (APP_CLK'), which means any required hold time can be met (subject
to a granularity of one XCore clock cycle). There is an uncertainty of Tcycle as to the
exact position of APP_CLK' due to the sampling uncertainty of the incoming APP_CLK
signal.
This is summarised together with other delay factors in the table below:
Factor
Best Case
Worst Case
APP_CLK
Sampling uncertainty 0
1xTcycle
Latency between APP_CLK' and data launch
2xTcycle
2xTcycle
Flight time to pin
Tflight_best
Tflight_worst
The flight time to pin is summarized in the table below:
pFload
1
5
10
20
Tflight_best
1.588 1.707 1.857 3.147 ns
Tflight_worst 5.346 5.766 6.295 7.422 ns
3.1
Best case output scenario (APP_CLK delay of 0)
The fastest possible output case is when APP_CLK' is not delayed and the output
flight time is at a minimum (2 x Tcycle + Tflight_best).
APP_CLK
APP_CLK'
T
T
T
cycle
cycle
flight_best
APP_DATA_OUT
valid
invalid
If 2 x Tcycle + Tflight_best exceeds the required Top_hold period, no clock delay adjust-
ments are required.
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3.2
Worst case output scenario (APP_CLK delay of 0)
The worst case scenario is when APP_CLK' is not delayed with respect to APP_CLK:
APP_CLK
APP_CLK'
T
T
T
T
cycle
cycle
cycle
flight_worst
Tflight_best
APP_DATA_OUT
valid
invalid
valid
In this case the longest time output data may take to become valid after APP_CLK
rises is:
3 x Tcycle + Tflight_worst
3.3
Calculating output setup time
The setup time offered by the output data can be calculated as:
Tapp_clk - (((N+1) x Tcycle) + Tflight_worst)
Tapp_clk
APP_CLK'
(N+1) x Tcycle
Tflight_worst
Top_setup
where N is the number of Tcycle delays added to APP_CLK' to meet the required hold
time (see Input Timing - Section 2).
Note that Tflight_best and Tflight_worst incorporate all on chip and pad related variability
(Tpdv and Tocv) and represent genuine best and worst cases.
The cumulative delay of 3 x Tcycle + Tflight_worst may leave insufficient time to meet
application setup timing requirements. If this case APP_CLK' may be positioned so
that it occurs some time before APP_CLK, such that the addition of Tflight_best + 2 x
Tcycle to APP_CLK' still meets output hold time requirements with respect to APP_CLK,
and setup time is also met.
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The above can be accomplished by sampling the falling edge of APP_CLK and then
delaying that such that APP_CLK' ends up positioned just before the following
APP_CLK edge. This scheme is safe as long as APP_CLK is free running and will not
be stopped or drop cycles.
4
Turnaround Timing
Many applications (such as USB 2.0) specify turnaround timing constraints, which are
defined as a constraint on the time an event is seen at the input pins of the device,
to a given response being output from the device. The value is usually specified as a
fixed time, or as a number of application clock cycles. This section explains how to
calculate the response of the XS1 device in such situations.
The path an input signal takes from input to output is as follows:
1 Input pad delay
1ns*
2 Input resynchronization flip flops
2 x Tcycle
3 Sampling uncertainty
1 x Tcycle
4 Input port delay
1 x Tcycle
5 Internal processing in the XCore
N x Tcycle
6 Output port delay
TBD x Tcycle
7 Output flight time
See Section 3 (Tflight_worst)
The total turnaround time is the sum of the delays items 1-7 in the table above.
The value of item 5 is dependent on the software running on the XCore. The XTA
toolset can help to determine this number as a worst case.
5
Further Information
If you have any doubt as to whether the XS1 ports can be configured for the particular
timing requirements of your application please contact XMOS support.
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Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively,
the "Information") and is providing it to you "AS IS" with no warranty of any kind,
express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the Information, or any particular implementation thereof, is
or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
Copyright ©2009 XMOS Ltd. All Rights Reserved. XMOS and the XMOS logo are
registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names
mentioned in this document are the trademarks or registered trademarks of their
respective owners. Where those designations appear in this document, and XMOS
was aware of a trademark claim, the designations have been printed with initial
capital letters or in all capitals.
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Document Outline

• Introduction