USB Audio 2.0 Reference Design, XS1-L1 Edition
Hardware Manual
Version 1.0
Publication Date: 2009/10/05
Copyright © 2009 XMOS Ltd. All Rights Reserved.

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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1
Introduction
The USB Audio 2.0 Reference Design, XS1-L1 Edition (hereafter "the board") is a
hardware reference design for a USB audio interface using the XMOS XS1-L1 event-
driven processor. It contains a single XS1-L1 device enabling implementation of a
complete USB 2.0 high-speed device compliant with release 2.0 of the audio USB
device class.
A block diagram of the design is shown below:
13MHz
XSYS
1Mbit
Optical
Resync
S/PDIF
Oscil ator
Debug
FLASH
Digital Audio
Transmitter
JTAG
SPI
MCLK
Analog Out
1Vrms at
Ful Scale
3.5mm
USB
Passive
Stereo
High Speed
LPF
USB
480Mb/s
USB
ULPI
I2S
TRS Jack
Series B
Transciever
XMOS
24 bit 192kHz
Stereo Audio
CODEC
Receptacle
USB3318
XS1-L1-128
3.5mm
CS4270
Passive
Stereo
LPF
+5V VBus
TRS Jack
Analog In
2Vrms for
1.8V LDO
Ful Scale
3.3V LDO
+3V3D
User
Push-Button
Audio Master
LEDs
Switches
Clock Oscillator
1.0V DC-DC
L1 Core
Produces
Supply
24.576MHz
or
CODEC
11.2896MHz
4.3V LDO
Analogue
Supply
The XS1-L1 event-driven processor communicates with the USB host via a ULPI USB
transceiver at the 480Mb/s high-speed rate. The XS1-L1 controls the streaming of
audio data over the USB connection and direct I2S interface to the audio CODEC. Multi-
ple additional functions (e.g. Mixers/DSP etc.) can be implemented by modifications
to the standard software.
Some key features of the board are listed below:
· USB bus-powered. No external power supply required
· Streams bit perfect audio data up to 24-bit @ 192kHz
· Supports standard sample rates - 44.1kHz, 48kHz, 88.2kHz, 96kHz, 192kHz
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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· USB endpoints use the asynchronous synchronisation mode to allow an external
low jitter audio master clock to be used
· Optical digital audio output (S/PDIF)
· Stereo line level audio input and output
· XMOS XSYS debug header for easy programming/debug from the host using the
XMOS XTAG2 debug adapter
· Two push-button switches and two LEDs for programmable use
The diagram below shows the layout of the main components on the board:
I
G
H
N
I
D
H
A
B
B
E
J
L
M
F
E
K
C
A
XS1-L1 Device
H
Push-Button Switch
B
USB Connector/Transceiver
I
Green User LED
C
Audio CODEC
J
USB Power LED
D
Optical digital output
K
Audio Clocking
E
3.5mm Stereo Jack
L
1V0 Core Supply
F
SPI FLASH
M
4V3 Analogue Supply
G
XSYS Debug Interface
N
13MHz Oscillator
The rest of this document provides a detailed description of each of the main circuit
components.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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2
XS1-L1 Device [A]
The board is based on a single XS1-L1 device in a 128 pin TQFP package.
The XS1-L1 consists of a single XCore, which comprises an event-driven multi-
threaded processor with tightly integrated general purpose I/O pins and 64 KBytes
of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
The processor has time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports is provided in
Programming XC on XMOS Devices.
2.1
Clocking
A discrete 13MHz oscillator is used to feed the XS1-L1 reference clock input and
also the USB3318 USB transceiver. The L1 has the MODE1 and MODE0 pins wired
to ground which sets the internal XS1-L1 PLL multiplication factor to 30.75. This
results in a core clock frequency of 399.75MHz and an I/O reference clock frequency
of 99.9375MHz.
2.2
Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide a
reset to the L1. This ensures the device will be reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset over
the XSYS debug interface.
2.3
Boot
The boot mode of the device is set by the MODE3 and MODE2 pins which are
connected together on the board. With MODE3 and MODE2 both high (default), the
device will boot from the 1Mb SPI FLASH on the board. With MODE3 and MODE2 both
low, the device will not boot from SPI FLASH allowing boot instead via JTAG over the
XSYS debug link.
Without anything connected to the XSYS interface, the board will boot from SPI FLASH.
With the XTAG2 connected to the XSYS interface, the host can control the boot mode
of the device by way of the TRST_N line.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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3
USB Connector and Transceiver [B]
The board uses a standard USB series B receptacle as its USB connector. The
high-speed USB signals are connected to an SMSC® USB3318 USB transceiver which
provides a ULPI connection to the XS1-L1.
On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L1 is
ready to begin accepting USB traffic. The USB transceiver reset pin is connected to
bit zero of port 32A so this can be controlled by software.
The transceiver uses the 13MHz clock provided by a discrete oscillator on the board
which doubles as the reference clock for the XS1-L1.
The I/O pins for the USB transceiver are mapped to ports on the XS1-L processor as
described in the port map shown later in this document.
4
Audio CODEC [C]
The board uses a 24 bit, 192kHz stereo audio CODEC (Cirrus Logic® CS4270).
The CODEC is configured to operate in stand-alone mode meaning that no serial
configuration interface is required. The digital audio interface is set to I2S mode with
all clocks being inputs (slave mode).
The CODEC has three internal modes depending on the sampling rate used. These
change the oversampling ratio used internally in the CODEC. The three modes are
shown below:
CODEC mode
CODEC sample rate range
Single speed
4-54kHz
Double speed
50-108kHz
Quad speed
100-216kHz
In stand-alone mode, the CODEC automatically determines which mode to operate in
based on the input clock rates.
The internal master clock dividers are set using the MDIV pins. MDIV1 is tied low
and MDIV2 is controlled by the L1 on bit 2 of port 32A.
With MDIV2 low, the master clock must be 256Fs in single speed mode, 128Fs in
double speed mode and 64Fs in quad speed mode. This allows an 11.2896MHz
master clock to be used for sample rates of 44.1, 88.2 and 176.4kHz.
With MDIV2 high, the master clock must be 512Fs in single speed mode, 256Fs
in double speed mode and 128Fs in quad speed mode. This allows a 24.576MHz
master clock to be used for sample rates of 48, 96 and 192kHz.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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These master clock frequencies were chosen due to the easy availability of crystals
at these frequencies.
The reset pin on the CODEC is mapped to bit 1 of port 32A on the processor.
4.1
Audio IO
Two 3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio input
and output. The layout of the audio jacks is displayed below:
OUT
IN
A simple passive ac-coupling and low pass filter circuit is used on input and output.
The circuit is configured so that the audio output will produce approximately 1VRMS
(0dBV) for a digital full scale signal. Due to the output coupling capacitors, the
output impedance falls with frequency and is approximately 1k
@ 35Hz falling to

576
@ 1kHz.

The input circuit contains an attenuator such that a 2VRMS (+6dBV) signal will produce
a full scale digital output. The input impedance is approximately 8k .

www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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5
Optical digital output [D]
An optical digital audio transmitter is used to provide a digital audio output in
IEC60958 consumer mode (S/PDIF) format. The S/PDIF signal is generated from a
1-bit port on the processor as defined in the port map. The data stream from the L1
is reclocked using the external master clock to synchronise the data into the audio
clock domain. This is achieved using a simple external D-type flip-flop.
6
SPI Flash Memory [F]
The board contains a 1Mbit FLASH memory device which is connected via a standard
Serial Peripheral Interface (SPI).
The FLASH is connected to four 1-bit ports as shown in the port map. These are the
standard ports the processor will try to boot from in boot from SPI mode.
Three of these ports are shared with I2S digital audio signals therefore the FLASH
cannot be accessed at the same time as digital audio is playing. When accessing the
SPI FLASH, the CODEC is held in reset and it ignores the three inputs shared with SPI
signals. When digital audio is playing, the FLASH is deselected by holding its chip
select (slave select) line inactive. In this mode, the FLASH will ignore other input
signals and set its output high impedance therefore it does not affect the shared
signals. The slave select signal is only active when booting the device therefore and
is held inactive while audio is playing.
The XMOS development tools include the XFLASH utility for programming compiled
programs into the flash memory. Software may also access the FLASH memory at
run-time by interfacing with the above ports. Note that, as mentioned, this can not
happen simultaneously with audio IO.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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7
XSYS Interface [G]
A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory and selection of boot mode. A 20-way
IDC header is used as the physical connector and the pinout of this is shown below:
Signal
Pin
Description
TRST_N
3
JTAG Test Reset. Active low.
TMS
7
JTAG Test Mode Select.
TCK
9
JTAG Test Clock.
TD1
5
JTAG Test Data. From debug adapter to XS1-L1.
TD2
13
JTAG Test Data. From XS1-L1 to debug adapter.
SRST_N
15
System Reset. Active low. Resets XS1-L1 device.
DEBUG
11
XS1-L1 DEBUG Interrupt line.
GND
4, 8, 12, 16, 20
Ground.
NC
1, 2, 6, 10, 14, 17, 18, 19
These pins are not connected.
On power on, the XS1-L1 boots from the on-board flash memory. With the XTAG2
connected, the XS1-L1 can be reset and then booted from a program on the host PC.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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8
Push-Button Switches [H]
The board provides two push-button switches whose states can be sampled at any
time by software. The layout of these switches is shown below:
A
B
The switches are connected to two 1-bit ports, the mapping of which can be seen in
the port map.
The port will go logic low when the button is pressed.
9
User LEDs [I]
The board provides two user LEDs that can be driven by software. The layout of
these LEDs is shown below:
B
A
The LEDs are connected to two bits of port 32A as shown in the port map. Setting
the relevant bit high will turn the LED on.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 10/18
10
Power
The board is a high-power bus-powered USB device. This means all the power used
by the board is derived from the nominally +5V VBus supply from the USB connector
and that the device will use more than 100mA from the VBus line when configured.
The board will use approximately 150mA when fully configured and operating.
Simple Low drop out (LDO) linear regulators are used to generate the global 3.3V
supply and the 1.8V supply required by the USB3318 USB transceiver.
A low noise LDO regulator is used to generate the analogue supply for the Audio
CODEC. The CODEC offers higher audio performance at higher supply voltages so the
voltage for this supply is set at 4.3V. This allows some headroom between the 4.5V
minimum VBus voltage and the approx 100mV dropout of the LDO + RC pre-filter.
A low cost buck switching regulator is used to generate the 1.0V core supply for
the XS1-L1. A ferrite bead is used on the +5V VBus input to prevent switching noise
propagating down the USB cable.
When the board is correctly connected to a USB source the USB Power LED is illumi-
nated.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 11/18
11
Audio Clocking [K]
The audio USB endpoints are configured in asynchronous mode. This means that the
board acts as the audio clock master and the host as the slave. This has the benefit
that a simple crystal oscillator can be used to generate the audio master clock which
typically results in lower jitter and consequently higher quality audio.
Two crystal oscillators are used on the board to support the two standard sample rate
base frequencies (44.1 and 48kHz). The crystal oscillators are built using discrete
components for low cost and easy availability however standard canned oscillators
could also be used. The oscillator design is a simple Pierce oscillator using an
unbuffered inverter as the amplifying component. The MCLK_SEL signal selects which
of the two oscillators is enabled, only one is enabled at any one time to avoid any
interference from the unused clock.
The behaviour of this select signal is shown below:
MCLK_SEL
Audio master clock frequency
0
11.2896MHz
1
24.576MHz
The audio master clock is connected to a 1-bit port of the XS1-L1 so that all of the I2S
outputs are synchronised with it. This also allows the S/PDIF output to be generated
from a buffered 1-bit port clocked by the audio master clock input.
The MCLK_SEL signal is mapped to bit 2 of port 32A on the processor as shown in
the port map.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 12/18
12
Test Points
The board provides 18 through-hole test points as defined in the table below:
Test Point
Port
Signal
1
P1I0
CODEC_ADC_DATA
2
P1D0
SPI_MOSI / CODEC_DAC_DATA
3
P1A0
SPI_MISO / CODEC_SCLK
4
P1C0
SPI_CLK / CODEC_LRCK
5
NA
CODEC_MCLK
6
P32A2
MCLK_SEL
7
P32A1
CODEC_RST_N
8
NA
GND
9
P1L0
SPDIF_TX
10
NA
SPDIF_OUT
11
P32A6
XD55
12
P32A7
XD56
13
P32A8
XD57
14
P32A9
XD58
15
P32A10
XD61
16
NA
3V3
17
NA
5V
18
NA
4V3A
13
Printed Circuit Board
The PCB is a two layer design in a credit card form factor with dimensions of 86 x
54mm. The mounting holes are 3.2mm in diameter.
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 13/18
14
Port Map
The table below provides a full description of the port to signal mappings used on
the board.
Pin
Port
Processor
1b
4b
8b
32b
XD0
P1A0
SPI_MISO / CODEC_SCLK
XD1
P1B0
SPI_SS
XD10
P1C0
SPI_CLK / CODEC_LRCK
XD11
P1D0
SPI_MOSI / CODEC_DAC_DATA
XD12
P1E0
ULPI_STP
XD13
P1F0
ULPI_NXT
XD14
P4C0 P8B0
XD15
P4C1 P8B1
XD16
P4D0 P8B2
XD17
P4D1 P8B3
ULPI_DATA[0:7]
XD18
P4D2 P8B4
XD19
P4D3 P8B5
XD20
P4C2 P8B6
XD21
P4C3 P8B7
XD22
P1G0
ULPI_DIR
XD23
P1H0
ULPI_CLK
XD24
P1I0
CODEC_ADC_DATA
XD25
P1J0
SWITCH_A
XD34
P1K0
SWITCH_B
XD35
P1L0
SPDIF_TX
XD36
P1M0
MCLK_IN
XD49
P32A0
USB_PHY_RST_N
XD50
P32A1
CODEC_RST_N
XD51
P32A2
MCLK_SEL
XD52
P32A3
LED_A
XD53
P32A4
LED_B
XD55
P32A6
TESTPOINT
XD56
P32A7
TESTPOINT
XD57
P32A8
TESTPOINT
XD58
P32A9
TESTPOINT
XD61
P32A10
TESTPOINT
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 14/18
15
Schematics
REV
A
1
OF
TP16
TP17
TP18
1
MTH1
PTH_M3
MTH2
PTH_M3
MTH3
PTH_M3
MTH4
PTH_M3
+5V
FM1
FM2
FM3
+3V3
+4V3A
SHEET
NC
NC
NC
NC
NC
NC
SHEET NAME
PROJECT NAME
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
2A
2B
2A
2B
TOP_LEVEL
Copyright (c) 2009 XMOS Ltd.
SWA
SWB
XC-6 USB AUDIO
KSC421J
KSC421J
SEPT 14 2009
1A
1B
1A
1B
1K
NC
NC
10K
R1
R4
+3V3
LEDB
ADC_DATA
DAC_DATA
SCLK
LRCK
CODEC_MCLK
MCLK_SEL
CODEC_RST_N
GREEN
SIZE
A3
DATE
10K
1K
R3
+3V3
R2
LEDA
GREEN
LEDB
LEDA
SWITCHA
SWITCHB
SDOUT
SDIN
SCLK
LRCK
MCLK
MDIV2
RST_N
CODEC
ADC_DATA
DAC_DATA
SCLK
LRCK
CODEC_MCLK
MCLK_SEL
CODEC_RST_N
TP11
TP12
TP13
TP14
TP15
C2
100N
+3V3
C1
100N
NC
+3V3
SWITCHA
SWITCHB
SPDIF_TX
XCORE_MCLK
MCLK_SEL
LEDA
LEDB
X0D55
X0D56
X0D57
X0D58
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
X0D0
X0D10
X0D11
X0D24
X0D25
X0D34
X0D35
X0D36
X0D50
X0D51
X0D52
X0D53
X0D54
X0D55
X0D56
X0D57
X0D58
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
J2
VCC
IN
GND
TOTX147PL
2
3
1
PORT
1 BIT
PORTS
32 BIT
+3V3
CLK
TP10
L1_128_USB
SPDIF_OUT
33R
R5
+3V3
CLK_13M
SPDIF_MCLK
CODEC_MCLK
XCORE_MCLK
5
4
2
Q
VCC
GND
MCLK
Q
CLK_13M
C
MCLK_BUF1
MCLK_BUF2
D
U1
C_N
D
CP
NC7SZ175
6
3
1
+3V3
MCLK_SEL
CLOCK_GEN
SPDIF_TX
SPDIF_MCLK
TP9
MCLK_SEL
www.xmos.com

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 15/18
REV
A
1
OF
1
4R7
C8
10U
C3
1U
R18
+1V0
+1V0
SHEET
C6
330P
+3V3
6K8
10K
NC
C26
2U2
C9
100N
C10
100N
R7
R13
+3V3
45
46
48
47
17
39
40
41
43
54
57
60
65
66
71
78
80
88
91
92
99
116
129
SHEET NAME
PROJECT NAME
L1
2U2
C20
100N
C12
100N
Copyright (c) 2009 XMOS Ltd.
L1_128_USB
GND_17
GND_39
GND_40
GND_41
GND_43
GND_54
GND_57
GND_60
GND_65
GND_66
GND_71
GND_78
GND_80
GND_88
GND_91
GND_92
GND_99
OTP_VPP
GND_116
GND_PAD
PLL_AVDD
PLL_AGND
NC
OTP_VDDIO
XC-6 USB AUDIO
SEPT 14 2009
5
4
5
4
C16
100N
C19
100N
NC
LX
FB
VOUT
POWER
GND
GND
2
2
C15
100N
C11
100N
SIZE
A2
DATE
U6
NCP699SN33
VIN
EN
U7
NCP1521B
VIN
EN
1
3
1
3
C18
100N
C14
100N
U3
XS1_L1_128TQFP
VDDIO_1
VDDIO_15
VDDIO_26
VDDIO_32
VDDIO_44
VDDIO_50
VDDIO_64
VDDIO_73
VDDIO_79
VDDIO_93
VDDIO_103
VDDIO_111
VDDIO_120
VDD_12
VDD_29
VDD_49
VDD_59
VDD_68
VDD_74
VDD_77
VDD_83
VDD_101
VDD_108
VDD_123
PCU_VDDIO
PCU_VDD
PCU_GATE
PCU_WAKE
PCU_CLK
1
15
26
32
44
50
64
73
79
93
12
29
49
59
68
74
77
83
22
19
23
20
24
C17
100N
C13
100N
103
111
120
101
108
123
+5V
+5V
+3V3
+1V0
C4
C22
4U7
100N
NC
NC
+3V3
+1V0
+3V3
CLK
+1V0
CONFIG
U3
XS1_L1_128TQFP
RESERVED
MODE0
MODE1
MODE2
MODE3
DEBUG
RST_N
CLK
TDO
TDI
TMS
TCK
TRST_N
18
51
52
53
55
42
21
25
63
62
58
61
56
C21
100N
+3V3
NC
47K
X0D0
X0D10
X0D11
X0D24
X0D25
X0D34
X0D35
X0D36
X0D50
X0D51
X0D52
X0D53
X0D54
X0D55
X0D56
X0D57
X0D58
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
R9
+3V3
DEBUG
SRST_N
CLK
TD2
TD1
TMS
TCK
TRST_N
X0D0
+3V3
PHY_RST_N
CLK
8
2
4
SO
VCC
GND
X0D0
X0D1
X0D10
X0D11
ULPI_STP
ULPI_NXT
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
ULPI_DIR
ULPI_CLK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MODE[1:0] = 00 ==> PLL_MULT = 30.75 ==> 13MHZ REFCLK
MODE[3:2] = 11 ==> BOOT FROM SPI
MODE[3:2] = 00 ==> BOOT FROM JTAG (DON'T BOOT)
ALL MODE PINS HAVE INTERNAL PULLUPS
37
36
34
30
28
27
16
14
10
7
5
2
128
126
118
115
113
110
107
106
96
90
94
89
87
86
85
84
109
105
104
102
72
70
69
67
82
81
76
75
100
98
97
95
4
6
8
9
11
13
31
33
35
38
3
127
125
124
122
121
119
117
114
112
U3
X0D0
X0D1
X0D2
X0D3
X0D4
X0D5
X0D6
X0D7
X0D8
X0D9
U4
AT25FS010
SI
SCK
WP_N
HOLD_N
CS_N
1MBIT
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
X0D49
X0D50
X0D51
X0D52
X0D53
X0D54
X0D55
X0D56
X0D57
X0D58
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
X0D67
X0D68
X0D69
X0D70
5
6
3
7
1
SPI FLASH
+3V3
XS1_L1_128TQFP
10K
IO
+3V3
R12
NC
NC
NC
NC
NC
X0D11
X0D10
X0D1
2
4
6
8
10
12
14
16
18
20
J4
1
3
5
7
9
XSYS2
11
13
15
17
19
HEADER_RA
NC
NC
NC
TRST_N
TD1
TMS
TCK
DEBUG
TD2
SRST_N
8K06
SRST_N
R6
47K
R8
+3V3
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
ULPI_STP
ULPI_NXT
ULPI_DIR
ULPI_CLK
NC
C27
2U2
1
4
+1V8
NC
16
15
14
13
11
10
9
8
20
18
19
12
24
25
STP
NXT
DIR
GND
RST_OUT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
RBIAS
C24
100N
CLKOUT
NC
5
4
C23
100N
NC
VOUT
+3V3
GND
U8
NCP303LSN09
INPUT
CD
GND
2
2
5
3
U2
USB3318
VBAT
VDD33
VDDIO
VDD18
VBUS
DM
DP
ID
CPEN
REFCLK
RESETB
3
4
2
5
6
1
7
17
21
23
22
10K
U5
NCP699SN18
VIN
EN
+1V0
1
3
NC
NC
R14
+3V3
C7
1N
1K
R10
USB PHY
+5V
+1V8
C25
100N
CLK
PHY_RST_N
USB_DM
USB_DP
+5V
FB1
USB_VBUS
330R
1K
1700mA
+5V
R11
D3
GREEN
C5
10N
1
2
3
4
5
6
DM
DP
S1
S2
GND
VBUS
DNP
J3
USB_B
R17
www.xmos.com

---

USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 16/18
1
REV
A
OF
1
SHEET
CLK_13M
SHEET NAME
PROJECT NAME
CLOCK_GEN
470R
Copyright (c) 2009 XMOS Ltd.
CLK_13M
C36
33P
R29
XC-6 USB AUDIO
SEPT 14 2009
4
U9
NC7SZU04
5
3
X1
R21
2M2
13M
+3V3
ABLS2
2
C37
33P
SIZE
A3
DATE
11M2896
470R
C33
33P
R28
6
U10
NC7WZU04
5
2
R19
2M2
X3
1
11M2896
HC49US
C32
33P
C28
1U
MCLK_BUF1
MCLK_BUF2
C29
100N
FB2
10K
Q2
BSS138
3
2
33R
33R
D
S
C30
100N
R24
330R
1700mA
R27
R26
+3V3
G
1
C31
100N
+3V3
+3V3
5
6
4
2
Y1
Y2
VCC
GND
24M576
1K
C35
33P
R22
4
U10
NC7WZU04
U12
A1
A2
NC7WZ17
1
3
R20
2M2
X2
3
24M576
HC49US
MCLK
C34
33P
10K
Q3
BSS138
3
2
D
S
R25
G
1
+3V3
5
4
2
Q
VCC
GND
10K
Q1
BSS138
0
1
3
2
D
S
MECH1
MECH2
R23
+3V3
U11
S
I0
I1
NC7SZ157
6
3
1
G
1
CRYSTAL_INSULATOR
CRYSTAL_INSULATOR
11M2896
24M576
MCLK_SEL
www.xmos.com

---

USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 17/18
REV
A
1
OF
1
SHEET
SHEET NAME
CODEC
PROJECT NAME
Copyright (c) 2009 XMOS Ltd.
XC-6 USB AUDIO
J5
SJ-3523-SMT
2
3
1
SEPT 14 2009
SIZE
A3
DATE
C50
2N2
C49
2N2
R42
470R
R41
470R
C48
47U
10K
10K
R35
R36
10U
10U
C52
100N
C41
C42
+4V3A
C40
10U
C51
100N
+3V3
CODEC DEFAULTS TO STAND ALONE MODE
SDOUT PULLED LOW BY 47K - SLAVE MODE
M0 = 0 : DE-EMPHASIS OFF
M1 = 0 : NOT USED IN STAND ALONE SLAVE MODE
MDIV PINS SELECT CLOCK RATIOS. SEE PAGE 23 OF DATASHEET.
I2S/LJ_N PULLED HIGH : I2S INTERFACE FORMAT.
NC
NC
C54
100N
22
23
21
24
5
8
19
18
17
20
6
VD
VA
VQ
VLC
AGND
DGND
AOUTA
AOUTB
FILTP
CS4270
MUTEA_N
MUTEB_N
C43
10U
+4V3A
C55
100N
U13
AINA
AINB
SDOUT
SDIN
SCLK
LRCK
MCLK
MDIV1
MDIV2
I2S/LJ_N
M0
M1
RST_N
7
1
4
2
3
9
+3V3
15
16
12
13
11
10
14
SDIN
SCLK
LRCK
MCLK
MDIV2
RST_N
C45
220P
C46
220P
C56
2U2
+4V3A
C39
C44
47K
R34
C47
100P
10U
10U
3K3
3K3
6K8
2K7
R33
R32
R31
R38
R40
4K7
R39
4K7
SDOUT
C53
100N
6
5
4
10K
FB
NR
OUT
+3V3
R37
2
3
1
J6
U14
TPS73001
IN
EN
GND
SJ-3523-SMT
1
3
2
VREF = 1.225V
VOUT = 1.225 * (1 + 6K8/2K7) = 4.31V
C38
4U7
4V3A LDO REGULATOR
1R
R30
+5V
www.xmos.com

---

USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 18/18
16
Related Documents
The following documents provide more information on designing with the USB Audio
2.0 Reference Design, XS1-L1 Edition:
· Programming XC on XMOS Devices: explains how to program XMOS event-driven
processor devices using the XC language.
· XCore XS1 Architecture Tutorial: provides an overview of the XS1 instruction
set architecture.
· XS1 XSystem-L: provides an introduction on how to boot the XS1-L devices.
· XMOS Tools User Guide: explains how to use the XMOS Tools to program XMOS
event-driven processor devices.
The most up-to-date information on the board, including schematics and product
datasheets, is available from:
· http://www.xmos.com/usbaudio2/
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively,
the "Information") and is providing it to you "AS IS" with no warranty of any kind,
express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the Information, or any particular implementation thereof, is
or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
www.xmos.com

---

Document Outline

• Introduction
• XS1-L1 Device [A]
• USB Connector and Transceiver [B]
• Audio CODEC [C]
• Optical digital output [D]
• SPI Flash Memory [F]
• XSYS Interface [G]
• Push-Button Switches [H]
• User LEDs [I]
• Power
• Audio Clocking [K]
• Test Points
• Printed