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USB Audio 2.0 MC Hardware Manual
USB Audio 2.0 Reference Design, XS1-L2 Edition
Hardware Manual
Version 1.6
Part Number: XR-USB-AUDIO-2.0-MC
Board Version: 1V2
Publication Date: 2010/06/29
Copyright © 2010 XMOS Ltd. All Rights Reserved.
Contents
1
Release History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
3
XS1-L2 Device [A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
4
USB Connector and Transceiver [19 & I] . . . . . . . . . . . . . . . . . .
9
5
Audio CODEC [C]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
6
Digital Audio Output [13 & 14] . . . . . . . . . . . . . . . . . . . . . . .
10
7
Digital Audio Input [15 & 16]
. . . . . . . . . . . . . . . . . . . . . . . .
11
8
MIDI I/O [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
9
Audio Clocking [3 & K] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
10
SPI Flash Memory [L]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
11
XSYS Interface [18]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
12
User LEDs [I] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
13
Expansion Header [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
14
Power [1, G, H, J, M & Q] . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
15
Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
16
Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
17
Port Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
18
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
19
Board Revision Changes . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
20
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
www.xmos.com
1
Release History
Date
Version
Description
28/01/10
1.0
Initial version
05/02/10
1.1
Revisions following interval review
24/02/10
1.2
Revisions for power supply sequencing
02/03/10
1.3
Revisions for board release 1V1
27/04/10
1.4
Revisions for R102
28/05/10
1.5
Revisions for MIDI, PLL & XTAG2
29/06/10
1.6
Revisions for board release 1V2
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2
Introduction
The USB Audio 2.0 Reference Design, XS1-L2 Edition (hereafter "the board") is a
hardware reference design for a multi-channel USB audio interface using the XMOS
XS1-L2 dual-core event-driven processor. It contains a single XS1-L2 device enabling
implementation of a complete USB 2.0 high-speed device compliant with release 2.0
of the USB Audio Class specification.
A block diagram of the design is shown below:
¼"
Pre-Amp
Mono
TRS Jack
Word Clock
User
XSYS
4Mbit
GPIO
PLL
MCLK
BNC Input
LEDs
Debug
FLASH Header
3.5mm
Pre-Amp
Mono
GPIO
JTAG
SPI
GPIO
TRS Jack
SYNC OUT & I2C
I2C
3.5mm
Passive
13MHz
Stereo
MCLK
LPF
Oscil ator
TRS Jack
USB
High Speed
USB
480Mb/s
USB
ULPI
Series B
Transciever
XMOS
3.5mm
I2S
Passive
Stereo
LPF
24 bit
TRS Jack
t
Receptacle
USB3318
XS1-L2-124QFN
192kHz
u
3.5mm
O
I2C
Audio
Passive
&
CODEC
Stereo
I
n
LPF
g
MIDI
TRS Jack
l
o
a
n
CS4244
A
Passive
3.5mm
1.8V LDO
MIDI
LPF &
Stereo
In/Out
HP Amp
TRS Jack
MCLK
3.5mm
+3V3D
Resync
Passive
3.3V DC-DC
Stereo
LPF
TRS Jack
+5V IN
3.5mm
L1 Core
Passive
1.0V DC-DC
Supply
Stereo
LPF
TRS Jack
Optical
Coaxial
Optical
Coaxial
CODEC
Digital
Digital
Digital
Digital
3.5mm
RC LP Filter
Analogue
Passive
Audio Rx
Audio Rx
Audio Tx
Audio Tx
Stereo
Supply
LPF
TRS Jack
The XS1-L2 event-driven processor communicates with the USB host via a ULPI USB
transceiver at the 480Mb/s high-speed rate. The XS1-L2 controls the streaming of
audio data over the USB connection and direct I2S interface to the audio CODEC, digital
streams and MIDI communications. Multiple additional functions (e.g. Mixers/DSP
etc.) can be implemented by modifications to the standard software.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2.1
Feature Overview
Key features of the board are as follows:
· Support for standard sample rates - 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
176.4kHz, 192kHz
· Six channels of analogue line level input
· Eight channels of analogue line level output
· Optical and coaxial digital audio input (S/PDIF or ADAT)
· Optical and coaxial digital audio output (S/PDIF or ADAT)
· MIDI input and output
· Word (house) clock input to allow synchronization to an external clock
· Integrated instrument and microphone pre-amplifier
· Integrated headphone amplifier on analogue outputs 1/2
· Powered via USB bus or external 5V source
· XMOS XSYS debug header for easy programming/debug from the host using the
XMOS XTAG2 debug adapter
· Eight LEDs for programmable use
· Expansion header with I2C and twelve general purpose IOs for programmable use
· Multiple test-points to allow connection of custom ADC/DAC hardware etc
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2.2
Board Components
The diagram below shows the layout of the main components of the board:
D
C
B
E
F
P
G
H
A
I
O
Q
J
L
M
K
N
A
XS1-L2 Device
J
1V0 Core Supply
B
Audio CODEC
K
13MHz Oscillator
C
Headphone Pre-Amp
L
4Mb SPI FLASH
D
Instrument & Mic Pre-Amp
M
Power Supply Protection & Fuse
E
Audio CODEC Clock Buffers
N
Case LED Power Connector
F
PLL & Clock Distribution
O
8 x User Programmable LEDs
G
4V1 Analogue Supply
P
PLL Auxiliary Output LED
H
3V3 Digital Supply
Q
USB & Power On LEDs
I
USB Transceiver
The rest of this document provides a detailed description of each of the main board
components.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2.3
Connectors
The diagram below shows the layout of the connectors on the board:
5
6
7
8
9
10
11
12
4
13
3
14
15
2
16
20
19
1
18
17
1
5V DC Power In
11
Analogue 5/6 OUT (Stereo 3.5mm
Jack)
2
MIDI Input & Output (Via Gameport)
12
Analogue 7/8 OUT (Stereo 3.5mm
Jack)
3
75
BNC Word Clock Input
13
Optical Digital Output
4
Instrument IN (Mono 1/4" Jack)
14
Coaxial Digital Output
5
Microphone IN (Mono 3.5mm Jack)
15
Optical Digital Input
6
Analogue 1/2 IN (Stereo 3.5mm Jack)
16
Coaxial Digital Input
7
Analogue 3/4 IN (Stereo 3.5mm Jack)
17
Expansion Header
8
Analogue 5/6 IN (Stereo 3.5mm Jack)
18
XSYS Debug Interface
9
Analogue 1/2 OUT (Stereo 3.5mm
19
USB B Connector
Jack)
10
Analogue 3/4 OUT (Stereo 3.5mm
20
Push Button Power Switch
Jack)
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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3
XS1-L2 Device [A]
The board is based on a single XS1-L2 device in a 124 pin QFN package.
The XS1-L2 consists of a two XCore processors. Each XCore comprises an event-
driven multi-threaded processor with tightly integrated general purpose I/O pins, 64
KBytes of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
XCore processors have time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports are provided in
Programming XC on XMOS Devices available from www.xmos.com.
3.1
Clocking [K]
A discrete 13MHz pierce oscillator is used to feed the XS1-L2 reference clock input
and also the USB3318 USB transceiver. The L2 has MODE1 and MODE0 pins wired to
ground which sets the internal XS1-L2 PLL multiplication factor to 30.75. This results
in a default core clock frequency of 399.75MHz and an I/O reference clock frequency
of 99.9375MHz.
3.2
Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide
a reset to the L2. This ensures the device is reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset over
the XSYS debug interface.
3.3
Boot
The boot mode of the XS1-L2 is set by the MODE3 and MODE2 pins which are
connected together on the board.
With MODE3 and MODE2 both high (default), the device will boot from the 4Mb SPI
FLASH on the board. With MODE3 and MODE2 both low, the device will not boot
from SPI FLASH, thus instead allowing boot via JTAG using the XSYS debug link.
To allow automatic boot mode selection based on debug hardware presence the
MODE2 and MODE3 pins are connected to the TRST_N of the debug connector.
Without debug hardware connected to the XSYS interface, the board will boot from
SPI FLASH. With the XTAG2 connected to the XSYS interface, the host can control the
boot mode of the device by way of the TRST_N line. This functionality is provided
purely for developer convenience. A typical production board might use a jumper or
switch for manual boot mode selection if JTAG boot is required.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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The MODE4 pin is held low on the board. This causes the second XCore to boot from
a link connected to first XCore, rather than its own SPI FLASH.
4
USB Connector and Transceiver [19 & I]
The board uses a standard USB series B receptacle for USB connectivity.
The high-speed USB signals are connected to an SMSC® USB3318 USB transceiver
which provides a ULPI connection to XCore 0 of the XS1-L2.
On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L2 is
ready to begin USB activity. The USB transceiver reset pin is connected to port X0P1M
of the XS1-L2 in order that it can be controlled by software.
The transceiver uses the 13MHz clock provided by a discrete oscillator which doubles
as the reference clock for the XS1-L2.
5
Audio CODEC [C]
The board is equiped with a 24 bit, 192kHz multi-channel audio CODEC (Cirrus
Logic® CS42448).
The CODEC is configured via an I2C serial configuration interface with slave address
0x48.
The CODEC can be configured to provide audio clocks (master mode) or with all
clocks being inputs (slave mode).
The CODEC has seperate LRCLK and SCLK I/Os for ADC and DAC. These are both
connected to a single I/O pin on the XCore. Clock buffers are provided for SCLK and
LRCLK I/Os to remove any potential contention issues.
The control pin (CODEC_MODE) for the buffers is mapped to bit 1 of port X1P4A on
the XS1-L2.
CODEC_MODE
Clock Mode
0
Clocks Connected
1
Clocks Disconnected
When using the codec in slave mode the clocks should be connected together.
The CODEC has three internal modes depending on the sampling rate used. These
change the oversampling ratio used internally in the CODEC. The three modes are
shown below:
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 10/32
CODEC mode
CODEC sample rate range
Single speed
4-50kHz
Double speed
50-100kHz
Quad speed
100-200kHz
The reset input to the CODEC is mapped to bit 3 of port X1P4A on the XS1-L2.
The interrupt output from the CODEC is mapped to bit 3 of port X1P4B on the XS1-L2.
5.1
Analogue Audio I/O [4 - 12]
3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio inputs and
outputs. The layout of the audio jacks is shown in the connector diagram of the
board.
A simple passive AC-coupling and low pass filter circuit is used on input and output.
The circuit is configured such that the audio output will produce approximately
0.94VRMS (-0.54dBV) for a digital full scale signal. Due to the output coupling
capacitors, the output impedance falls with frequency and is approximately 1k
@
35Hz falling to 576
@ 1kHz.
The input circuit contains an attenuator such that a 1.62VRMS (+4.2dBV) signal will
produce a full scale digital output. The input impedance is approximately 9k .
The CODEC microphone and instrument inputs are AC-coupled to low noise op-amp
pre-amplifiers before being AC-coupled onto the CODEC inputs. These are set with
gains of -1 and -10 for the instrument and microphone inputs respectively.
A 3.5mm Tip Ring Sleeve (TRS) audio jack is provided for the stereo headphone out,
which is powered by a 75mW TI TPA152 stereo headphone amplifier. This is the a
capable of driving a minimum load of 32 . It is configured with a gain of -1.
6
Digital Audio Output [13 & 14]
Optical and coaxial digital audio transmitters are used to provide digital audio output
in formats such as IEC60958 consumer mode (S/PDIF) and ADAT. The signals are
generated from two 1-bit ports on the XS1-L2 as defined in the port map.
The data streams from the XS1-L2 are re-clocked using the external master clock
to synchronise the data into the audio clock domain. This is achieved using simple
external D-type flip-flops.
The optical output uses a TOSLINK optical connector with an integrated LED and
differential driving circuit. The coaxial output uses an RCA connector and is isolated
via a transformer.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 11/32
7
Digital Audio Input [15 & 16]
Digital audio input is provided to allow formats such as IEC60958 consumer mode
(S/PDIF) or ADAT to be connected to the device via either optical or coaxial mediums.
The optical input uses a TOSLINK optical connector with an integrated photodiode
and receiver circuit. The coaxial input uses an RCA connector and is AC-coupled into
a 75
terminator.
This gives a signal level of 0.5Vp-p, which is fed into a differential line receiver.
The input signals are fed into two 1-bit ports on the processor as defined in the port
map.
8
MIDI I/O [2]
Musical Instrument Digital Interface input and output is provided on the board via a
standard Gameport connector. The signals are buffered using 5V line drivers and are
then connected to 1-bit ports on the XS1-L2, via a 5V to 3.3V buffer.
10K
pull ups are placed on the MIDI IN signal from the connector and on the MIDI
OUT signal from the XCore. These stop glitches on startup and when no MIDI devices
are connected to the board.
The MIDI input and output signals are connected to the XS1-L2 as follows:
Port
Signal
X1P1P
MIDI_IN
X1P1O
MIDI_OUT
Standard MIDI devices (using DIN 5/180 connectors) are attached using a Gameport
to dual DIN MIDI cable. This is not included in the kit, but are easily purchased from
other suppliers.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 12/32
9
Audio Clocking [3 & K]
In order to accommodate a multitude of clocking options, the low-jitter master clock
(e.g. 256 x fs), is generated locally using a fractional-N frequency multiplier PLL chip.
The source for the PLL is either the SYNC_OUT signal from the XS1-L2 or the word
clock input as controlled by the SYNC_SEL signal.
The SYNC_SEL signal is mapped to bit 0 of port X1P4A on the XS1-L2 as shown in the
port map.
The behaviour of this select signal is as follows:
SYNC_SEL
PLL clock source
0
XS1-L2 SYNC_OUT
1
Word Clock Input
The Cirrus Logic CS2300-CP PLL chip generates a low-jitter output of between 6-
75MHz from any 50Hz-30MHz input clock.
A variety of clock sources can be used, including:
· Local crystal oscillator, via XCore clock block (which divides 13MHz down to the
SYNC_OUT signal).
· S/PDIF software recovered clock (which then drives the SYNC_OUT signal).
· Word clock input.
The SYNC_OUT signal is connected to both cores of the XS1-L2, but a DNF resistor
(R102) normally only allows XCore 1 to output the signal. Fit a 0R 0603 resistor to
enable XCore 0 to output the signal.
The audio master clock is connected to both cores of the XS1-L2 on ports X0P1L and
X1P1L, to allow the audio output streams on that XCore to be synchronized.
The CS2300-CP is configured over the I2C bus (shared with the CODEC) at slave
address 0x47.
The CS2300-CP auxiliary output drives an LED to indicate the state of the signal. For
example, this could show if the PLL is locked or not.
A 75
terminated BNC input is provided for an external word clock ("house clock")
input. The input accepts a 0-5V (5Vp-p, 2.5V offset) signal, which is low-pass filtered
to remove high frequency components, and schmitt triggered to remove problems
with noise and non-monotonic edges.
This signal is also fed to a 1-bit port on the XS1-L2. This allows the application code
to detect if a word clock input signal is present.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 13/32
10
SPI Flash Memory [L]
A 4Mbit FLASH memory device is provided, connected via a standard Serial Peripheral
Interface (SPI).
The FLASH is connected to four 1-bit ports as shown in the table below. These are
the standard ports the processor will try to boot from in SPI boot mode.
Port
SPI Signal
X0P1A
MISO
X0P1B
SS
X0P1C
CLK
X0P1D
MOSI
The XMOS development tools include the XFLASH utility for programming compiled
programs into the flash memory via the XS1-L2. Software may also access the FLASH
memory at run-time by interfacing with the above ports.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 14/32
11
XSYS Interface [18]
A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory via the XS1-L2 and selection of boot
mode. It is not recommended to use an original (FTDI based) XTAG with the L2
device, as this is not as fast as the XTAG2 and can have signal drive strength issues.
A 20-way IDC header is used as the physical connector and the pinout of this is
shown below:
Signal
Pin
Description
TRST_N
3
JTAG Test Reset. Active low
TMS
7
JTAG Test Mode Select
TCK
9
JTAG Test Clock
TD1
5
JTAG Test Data. From debug adapter to XS1-L2
TD2
13
JTAG Test Data. From XS1-L2 to debug adapter
SRST_N
15
System Reset. Active low. Resets XS1-L2 device
DEBUG
11
XS1-L2 DEBUG Interrupt line
XMOS-LINK
6, 10, 14, 18
This is a 2-wire XMOS-Link for advanced debug
GND
4, 8, 12, 16, 20
Ground
NC
1, 2, 17, 19
These pins are not connected
As discussed in the Boot section the XS1-L2 MODE2 and MODE3 pins are connected
to the TRST_N signal.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 15/32
12
User LEDs [I]
The board provides eight user LEDs that can be driven by software. These are marked
on the board as LED 0 though to LED 7. The LEDs are connected to port X1P8B, the
bit mapping is shown in the table below:
Port
LED
X1P8B0
LED 0
X1P8B1
LED 1
X1P8B2
LED 2
X1P8B3
LED 3
X1P8B4
LED 4
X1P8B5
LED 5
X1P8B6
LED 6
X1P8B7
LED 7
The LED connections are also shown in the port map. Setting the relevant bit high
will turn the LED on.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 16/32
13
Expansion Header [17]
The board provides a general purpose input/output expansion header to allow
interfacing to custom boards. For example, this could be an I2C display, eight LEDs
and four buttons to make a user interface.
The header contains the following:
· +3V3 power pin.
· Ground pin.
· I2C bus (as used to configure the PLL and CODEC).
· One 4-bit GPIO port (X1P4F).
· One 8-bit GPIO port, which is also shared with the LED outputs (X1P8B).
A 16-way IDC header is used as the physical connector and the pinout of this is
shown below:
Pin
Port
Signal
1
NA
+3V3
2
X1P8B7
LED_7
3
NA
GND
4
X1P8B6
LED_6
5
X1P1C0
I2C_SDA
6
X1P8B5
LED_5
7
X1P1D0
I2C_SCL
8
X1P8B4
LED_4
9
X1P4F0
GPIO_0
10
X1P8B3
LED_3
11
X1P4F1
GPIO_1
12
X1P8B2
LED_2
13
X1P4F2
GPIO_2
14
X1P8B1
LED_1
15
X1P4F3
GPIO_3
16
X1P8B0
LED_0
Each IO pin can source or sink a maximum of 4mA.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 17/32
14
Power [1, G, H, J, M & Q]
The board is powered from the onboard +5V DC power connector or from the USB
bus. Note that the board has not been designed as a bus-powered device due to
pre-enumeration current limits.
The two different power supplies are "ORd" together using Schottky diodes with a
maximum voltage drop of 0.34V. A 750mA resettable polyfuse and reverse polarity
protection, via a bidirectional zener diode, is provided. Ferrite beads are used on the
+5V VBus and +5V DC power input to prevent switching noise propagating down the
USB and power cables.
A latching push-button power switch is fitted to the board that activates a p-channel
MOSFET (which has an Rds(on) of approximately 80m ). A soft start circuit is
included to limit the inrush current.
When powered from the USB bus all the power used by the board is derived from the
nominally +5V VBus supply from the USB connector. The board will use approximately
300mA when fully configured and operating.
The required core and IO voltages for the XS1-L2 are derived from 5V as follows:
· A low cost 1.5A buck switching regulator is used to generate the 1.0V core
supply for the XS1-L2.
· A low cost 600mA buck switching regulator is used to generate the global 3.3V
supply.
Switching regulators are used on these power supplies due to their high efficiency.
The power supplies are sequenced using a 3.0V voltage supervisor on the 3.3V
supply output, to drive the enable input on the 1.0V supply. This makes sure that
the 3.3V supply is up and stable, before the 1.0V supply comes up and also provides
predictable behaviour under brownout conditions, by causing a reset if the supplies
droop significantly.
A simple low drop out (LDO) linear regulator is used to generate the 1.8V supply
required by the USB3318 USB transceiver.
A low noise LDO regulator is used to generate the analogue supply for the Audio
CODEC. The CODEC offers higher audio performance at higher supply voltages so the
voltage for this supply is set at 4.1V. This allows some headroom between the 4.5V
minimum VBus voltage and the approx 350mV dropout of the LDO + RC pre-filter.
When the board is correctly connected to a USB source the USB VBUS Power LED is
illuminated.
When the board is powered on the Power LED is illuminated.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 18/32
15
Printed Circuit Board
The PCB is a 1.6mm four layer design in a XMOS XS1-G Development Kit form factor
with dimensions of 180 x 120mm. It is made from FR4 (r = 4.5) material and
finished in immersion gold. The mounting holes are 3.2mm in diameter.
Signal stack up is as follows:
· Top signal
· Ground plane
· Power plane
· Bottom signal
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 19/32
16
Test Points
16.1
Test Points by ID
Test Point
Port
Signal
TP1
NA
+5V
TP2
NA
+4V1A
TP3
NA
+3V3
TP4
NA
+1V8
TP5
NA
+1V0
TP6
NA
OSC_13M
TP8
NA
PLL_WCLK
TP9
NA
VBUS
TP10
X0P1J0
OPTICAL_RX
TP11
X1P1N0
DAC_SD4
TP12
X1P1H0
DAC_SD3
TP13
X1P1F0
DAC_SD2
TP14
X1P1M0
DAC_SD1
TP15
X1P1I0
CODEC_SCLK
TP16
X1P1E0
CODEC_LRCK
TP17
X1P1D0
I2C_SCL
TP18
X1P1C0
I2C_SDA
TP19
X1P4A3
CODEC_RSTN
TP20
X1P1B0
ADC_SD3
TP21
X1P1A0
ADC_SD2
TP22
X1P1G0
ADC_SD1
TP23
X1P4B3
CODEC_INT
TP24
X0P1L0 & X1P1L0
XCORE_MCLK
TP25
X0P1C0 & X1P4E0
SYNC_OUT
TP26
X1P4A0
SYNC_SEL
TP27
X1P1K0
COAXIAL_TX
TP28
X1P4A1
CODEC_MODE
TP29
X1P4B1
PLL_LOCK
TP30
X0P1K0
COAXIAL_RX
TP31
X1P1J0
OPTICAL_TX
TP34
X1P1O0
MIDI_OUT
TP35
X1P1P0
MIDI_IN
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 20/32
16.2
Test Points by Signal
16.2.1
Power
Signal
Port
Test Point
+1V0
NA
TP5
+1V8
NA
TP4
+3V3
NA
TP3
+4V1A
NA
TP2
+5V
NA
TP1
VBUS
NA
TP9
16.2.2
XS1-L2 System
Signal
Port
Test Point
OSC_13M
NA
TP6
PLL_LOCK
X1P4B1
TP29
16.2.3
Audio Clocking
Signal
Port
Test Point
SYNC_SEL
X1P4A0
TP26
PLL_WCLK
NA
TP8
SYNC_OUT
X0P1C0 * & X1P4E0
TP25
XCORE_MCLK
X0P1L0 & X1P1L0
TP24
* Enabled via DNF resistor R102.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 21/32
16.2.4
Codec Audio
Signal
Port
Test Point
ADC_SD1
X1P1G0
TP22
ADC_SD2
X1P1A0
TP21
ADC_SD3
X1P1B0
TP20
DAC_SD1
X1P1M0
TP14
DAC_SD2
X1P1F0
TP13
DAC_SD3
X1P1H0
TP12
DAC_SD4
X1P1N0
TP11
CODEC_LRCLK
X1P1E0
TP16
CODEC_SCLK
X1P1I0
TP15
16.2.5
Codec Config/Status
Signal
Port
Test Point
CODEC_INT
X1P4B3
TP23
CODEC_MODE
X1P4A1
TP28
CODEC_RST
X1P4A3
TP19
I2C_SCL
X1P1D0
TP17
I2C_SDA
X1P1C0
TP18
16.2.6
Digital Audio
Signal
Port
Test Point
OPTICAL_RX
X0P1J0
TP10
OPTICAL_TX
X1P1J0
TP31
COAXIAL_RX
X0P1K0
TP30
COAXIAL_TX
X1P1K0
TP27
16.2.7
MIDI
Signal
Port
Test Point
MIDI_OUT
X1P1O0
TP34
MIDI_IN
X1P1P0
TP35
Unmarked test points are connected to ground.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 22/32
17
Port Map
The table below provides a full description of the port to signal mappings used on
the board.
Pin
Port
XCore
1b
4b
8b
16b
0
1
XD0
P1A0
SPI_MISO
ADC_SD2
XD1
P1B0
SPI_SS
ADC_SD3
XD2
P4A0
P8A0
P16A0
SYNC_SEL
NA
XD3
P4A1
P8A1
P16A1
CODEC_MODE
XD4
P4B0
P8A2
P16A2
NA
XD5
P4B1
P8A3
P16A3
PLL_LOCK
XSYS Link
XD6
P4B2
P8A4
P16A4
WORD_CLK
XD7
P4B3
P8A5
P16A5
CODEC_INT
XD8
P4A2
P8A6
P16A6
NA
NA
XD9
P4A3
P8A7
P16A7
CODEC_RST_N
XD10
P1C0
SPI_CLK / SYNC_OUT *
I2C_SDA
XD11
P1D0
SPI_MOSI
I2C_SCL
XD12
P1E0
ULPI_STP
CODEC_LRCK
XD13
P1F0
ULPI_NXT
DAC_SD2
XD14
P4C0
P8B0
P16A8
XD15
P4C1
P8B1
P16A9
XD16
P4D0
P8B2
P16A10
XD17
P4D1
P8B3
P16A11
ULPI_DATA[0:7]
LEDS[0:7]
XD18
P4D2
P8B4
P16A12
XD19
P4D3
P8B5
P16A13
XD20
P4C2
P8B6
P16A14
XD21
P4C3
P8B7
P16A15
XD22
P1G0
ULPI_DIR
ADC_SD1
XD23
P1H0
ULPI_CLK
DAC_SD3
XD24
P1I0
WORD_CLK
CODEC_SCLK
XD25
P1J0
OPTICAL_RX
OPTICAL_TX
XD26
P4E0
P8C0
P16B0
SYNC_OUT
XD27
P4E1
P8C1
P16B1
NA
XD28
P4F0
P8C2
P16B2
XD29
P4F1
P8C3
P16B3
NA
GPIO[0:3]
XD30
P4F2
P8C4
P16B4
XD31
P4F3
P8C5
P16B5
XD32
P4E2
P8C6
P16B6
NA
XD33
P4E3
P8C7
P16B7
XD34
P1K0
COAXIAL_RX
COAXIAL_TX
XD35
P1L0
MCLK_IN
MCLK_IN
XD36
P1M0
P8D0
P16B8
ULPI_RST
DAC_SD1
XD37
P1N0
P8D1
P16B9
DAC_SD4
XD38
P1O0
P8D2
P16B10
MIDI_OUT
XD39
P1P0
P8D3
P16B11
MIDI_IN
XD40
P8D4
P16B12
NA
XD41
P8D5
P16B13
NA
XD42
P8D6
P16B14
XD43
P8D7
P16B15
* Enabled via DNF resistor R102.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 23/32
18
Schematics
1
REV
1V2
OF
1
+4V1A
+1V8
VBUS
1K
+5V
R30
SHEET
D13
+5V
+3V3
+1V0
OSC_13M
PLL_WCLK
OPTICAL_RX
COAXIAL_RX
GREEN
1K
SHEET NAME
TP1
TP2
TP3
TP4
TP5
TP9
TP6
TP8
PROJECT NAME
TP10
TP30
VBUS
R91
POWER LEDS
D8
TOP_LEVEL
Copyright (c) 2009 XMOS Ltd.
GREEN
FIDUCIALS & TPS
JUN 29 2010
XR-USB-AUDIO-2.0-MC
FM1
FM2
FM3
FM4
FM5
FM6
SIZE
A3
DATE
TP20
TP21
TP22
TP29
TP26
TP25
TP31
TP27
TP28
TP23
JP1
1
2
+5V
XL_UP1
XL_UP0
XL_DN0
XL_DN1
CLK_13M
ADC_SD3
ADC_SD2
ADC_SD1
XS1_SYSTEM
10K
PLL_LOCK
SYNC_SEL
SYNC_OUT
WORD_CLK
CODEC_INT
OPTICAL_TX
COAXIAL_TX
CODEC_MODE
+5V
R104
BLEEDER R
OSC_13M
NC
POWER_ON_N
ADC_SD3
ADC_SD2
ADC_SD1
PLL_LOCK
SYNC_SEL
SYNC_OUT
WORD_CLK
1
2
3
CODEC_INT
XL_UP1
XL_UP0
XL_DN0
XL_DN1
OPTICAL_TX
COAXIAL_TX
CODEC_MODE
OSC_13M
SW1
MECH1
SWITCH_CAP
PN12SHNA03QE
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
MCLK_IN
I2C_SCL
I2C_SDA
CODEC_RSTN
WORD_CLK
SYNC_OUT
MCLK_IN
OPTICAL_RX
COAXIAL_RX
XS1_CORE1
XS1_CORE0
+5V
3
D
C5
G
MTH4
MTH3
MTH2
MTH1
1
100N
2
S
PTH_M3
PTH_M3
PTH_M3
PTH_M3
Q1
NTR4101P
MOUNTING HOLES
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
XCORE_MCLK
I2C_SCL
I2C_SDA
CODEC_RSTN
OPTICAL_RX
COAXIAL_RX
1K
R2
R3
10K
TP11
TP12
TP13
TP14
TP15
TP16
TP24
TP17
TP18
TP19
I2C_SCL
I2C_SDA
WORD_CLK
SYNC_OUT
SYNC_SEL
PLL_LOCK
PLL_WCLK
D1
DIGI_MCLK
XCORE_MCLK
CODEC_MCLK
SMBJ5.0A
SUB SHEETS & CODEC TPS
F1
0.75A
POWER_ON_N
I2C_SCL
I2C_SDA
TP55
TP56
TP57
TP58
TP59
WORD_CLK
SYNC_OUT
SYNC_SEL
PLL_LOCK
PLL_WCLK
ADC_SD3
ADC_SD2
ADC_SD1
DIGI_MCLK
XCORE_MCLK
CODEC_MCLK
CODEC_INT
CODEC_MODE
D2
D3
MBR120VLSFT
MBR120VLSFT
TP50
CLOCKING
TP51
TP52
TP53
TP54
INT
C3
100N
MODE
5V DC POWER INPUT, PROTECTION, FILTERING & SWITCH
ADC_SD3
ADC_SD2
ADC_SD1
VBUS
330R
1700mA
TP45
TP46
TP47
TP48
TP49
FB2
C4
100N
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
SCLK
LRCK
MCLK
I2C_SCL
I2C_SDA
RST_N
MCLK
OPTICAL_RX
COAXIAL_RX
OPTICAL_TX
COAXIAL_TX
CODEC
DIGITAL_IO
GROUND TEST POINTS
TP38
TP41
TP42
TP43
TP44
2
1A
1B
3
J1
PJ-014D-SMT
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
CODEC_MCLK
I2C_SCL
I2C_SDA
CODEC_RSTN
DIGI_MCLK
OPTICAL_RX
COAXIAL_RX
OPTICAL_TX
COAXIAL_TX
TP7
TP32
TP33
TP36
TP37
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 24/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
CODEC
PROJECT NAME
J8
SJ-3524-SMT
J9
SJ-3524-SMT
J10
SJ-3524-SMT
J11
SJ-3524-SMT
2
3
1
2
3
1
2
3
1
2
3
1
Copyright (c) 2009 XMOS Ltd.
10
10
10
10
JUN 29 2010
NC
NC
NC
NC
XR-USB-AUDIO-2.0-MC
R31
33R
R29
33R
1K
C34
2N2
C35
2N2
C37
2N2
C36
2N2
C38
2N2
C39
2N2
1K
R17
R16
SIZE
A2
DATE
100U
100U
R52
470R
R53
470R
R55
R54
470R
470R
R56
470R
R57
470R
C61
C64
20K
4U7
4U7
4U7
4U7
4U7
4U7
10K
10K
10K
10K
10K
10K
R10
R19
R20
R22
R21
R23
R24
20K
C55
C56
C58
C57
C59
C60
R11
+4V1A
6
1
5
7
VDD
VO1
VO2
GND
R12
20K
R13
20K
C53
4U7
U6
MUTE
IN1-
IN2-
BYPASS
TPA152
2
8
4
3
C13
1U
C50
4U7
C24
100N
HEADPHONE AMP
+4V1A
C63
100U
C21
100N
R15
20K
R14
20K
AIN6B
AIN5B
+4V1A
C23
100N
4U7
4U7
MIC_IN
INST_IN
C52
C54
C62
100U
PREAMPS
C31
2N2
C33
2N2
PREAMP
C22
100N
R50
NC
NC
NC
NC
NC
NC
NC
NC
NC
470R
R51
470R
26
25
27
28
30
29
31
32
34
33
36
37
39
38
40
41
35
43
55
54
VQ
MUTEC
AOUT1P
AOUT1N
AOUT2P
AOUT2N
AOUT3P
AOUT3N
AOUT4P
AOUT4N
AOUT5P
AOUT5N
AOUT6P
AOUT6N
AOUT7P
AOUT7N
AOUT8P
AOUT8N
CS42448
FILTP_ADC
FILTP_DAC
C110
2U2
C16
100N
+4V1A
VA_5353
VA_44
AGND_56
44
56AGND_42
42
C15
100N
C18
100N
+4V1A
C108
100P
VD_2424
VD_6
DGND_62
6
62DGND_23
10K
4K3
23
VLS
DGND_7
8
7
C14
100N
C17
100N
R26
R27
VLC4
+3V3
C25
4U7
C26
4U7
+3V3
+4V1A
C109
100N
6
5
4
U3
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
AIN5P/AIN5A
AIN5N/AIN5B
AIN6P/AIN6A
AIN6N/AIN6B
AUX_SDIN
AUX_SCLK
AUX_LRCK
ADC_SDOUT3
ADC_SDOUT2
ADC_SDOUT1
ADC_SCLK
ADC_LRCK
DAC_SDIN4
DAC_SDIN3
DAC_SDIN2
DAC_SDIN1
DAC_SCLK
DAC_LRCK
MCLK
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS_N
INT
RST_N
9
5
2
1
3
46
45
48
47
50
49
52
51
58
57
60
59
22
21
20
11
12
13
14
15
16
17
18
19
10
63
64
61
FB
NR
OUT
4K7
R46
NC
NC
AIN5B
AIN6B
INT
U21
TPS73001
IN
EN
GND
R49
4K7
RST_N
1
3
2
ADC_SCLK
ADC_LRCK
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
4K7
R43
4K7
C107
4U7
SCLK
LRCK
MCLK
ADC_SD3
ADC_SD2
ADC_SD1
C45
4U7
R42
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
4V1A LDO REGULATOR
I2C_SCL
I2C_SDA
R1
1R
C44
4U7
VREF = 1.225V
VOUT = 1.225 * (1 + 10K/4K3) = 4.07V
C1
100N
4K7
R44
+3V3
C43
4U7
4K7
R45
+3V3
470R
500mA
C42
4U7
FB1
C2
100N
+5V
I2C Chip Address is 1001000X (X is R/nW bit)
I2C_SCL
I2C_SDA
C32
2N2
C40
2N2
C28
2N2
C27
2N2
C29
2N2
C30
2N2
C51
C41
C46
C47
C49
C48
C19
100N
+3V3
4U7
4U7
4U7
4U7
4U7
4U7
4K7
4K7
4K7
4K7
4K7
4K7
R48
R33
R37
R34
R38
R41
C20
100N
+3V3
R47
4K7
R32
4K7
R36
4K7
R35
4K7
R39
4K7
R40
4K7
ADC_SCLK
ADC_LRCK
+3V3
+3V3
NC
NC
NC
5
4
3
5
4
3
Y
Y
VCC
GND
VCC
GND
2
10
3
1
2
10
3
1
2
10
3
1
J6
J7
J12
U5
NC7SZ125
U4
NC7SZ125
SJ-3524-SMT
SJ-3524-SMT
SJ-3524-SMT
1
2
1
2
ADC CLK BUFFERS
OE_N
A
OE_N
A
10K
R18
+3V3
MODE
SCLK
LRCK
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 25/32
1
REV
1V2
OF
1
+3V3
SHEET
X0D0
8
2
4
SO
VCC
GND
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET NAME
PROJECT NAME
100N
Copyright (c) 2009 XMOS Ltd.
XS1_XCORE0
C75
U10
AT25DF041A
SI
SCK
WP_N
HOLD_N
CS_N
4MBIT
JUN 29 2010
5
6
3
7
1
R71
33R
R72
33R
R73
33R
R74
33R
XR-USB-AUDIO-2.0-MC
XSYS XMOS-LINK
10K
SPI BOOT FLASH
X0D4
X0D5
X0D6
X0D7
R69
+3V3
SIZE
A3
DATE
X0D11
X0D10
X0D1
J15
USB_B
VBUS
1U
C73
VBUS
DM
DP
GND
S1
S2
1
2
3
4
5
6
R75
+3V3
DNP
C77
100N
1700mA
330R
C74
10N
C76
FB5
100N
VBUS
X0D36
OSC_13M
+1V8
R68
1K
R70
C79
100N
NC
NC
10K
+3V3
DM
DP
C80
2U2
3
4
17
21
2
5
6
1
7
23
22
U8
DM
DP
ID
+1V8
VBAT
VBUS
CPEN
VDD33
VDDIO
VDD18
REFCLK
RESETB
USB3318
USB PHY
NC
5
4
NC
VOUT
1V8 LDO & DECOUPLING
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
STP
NXT
DIR
CLKOUT
RBIAS
GND
9
8
GND
16
15
14
13
11
10
20
18
19
12
24
25
2
U11
NCP699SN18
VIN
EN
1
3
R67
8K06
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D12
X0D13
X0D22
X0D23
+5V
C78
100N
WORD_CLK
OPTICAL_RX
COAXIAL_RX
MCLK_IN
SYNC_OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
X0D0
X0D1
X0D4
X0D5
X0D6
X0D7
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D36
DNP
R102
XCORE
A15
A16
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A55
A57
A58
A59
A60
A61
A63
A64
A65
A66
A56
A62
A54
A67
B38
B39
B40
B41
B44
B45
B46
B47
A4
A3
B48
B49
B50
B51
B52
B53
B54
B55
X0D10
U9
X0D0
X0D1
X0D2
X0D3
X0D4
X0D5
X0D6
X0D7
X0D8
X0D9
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
XS1_L2_124LGA
IO_XCORE0
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 26/32
1
REV
1V2
OF
1
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET
CLK_13M
NC
C83
100N
+3V3
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET NAME
PROJECT NAME
2
4
6
8
10
12
14
16
18
20
470R
Copyright (c) 2009 XMOS Ltd.
CLK_13M
XS1_SYSTEM
C98
33P
J16
R84
1
3
5
7
9
11
13
15
17
19
HEADER_RA
JUN 29 2010
4
U12
NC7SZU04
XR-USB-AUDIO-2.0-MC
5
3
X1
R76
2M2
13M
XSYS HEADER
+3V3
ABLS2
2
13MHz OSCILLATOR
NC
TRST_N
TDI
TMS
TCK
DEBUG
TDO
RST_N
NC
NC
C99
33P
SIZE
A3
DATE
10K
R80
+5V NC, So Cannot Be Powered By XTAG2
+3V3
2R2
C81
1U
R82
+1V0
C93
4U7
+1V0
C85
100N
+3V3
NC
NC
CLK_13M
C84
100N
10N
B32
B4
B5
B3
B2
B6
A38
A37
A1
A18
A52
PAD
CONFIG
C87
100N
C111
GND_A1
PCU_VDD
PCU_CLK
GND_A18
GND_A52
GND_PAD
PCU_GATE
PCU_WAKE
PLL_AVDD
PLL_AGND
OTP_VDDIO
PCU_VDDIO
+1V0
C86
100N
2
5
3
U9
XS1_L2_124LGA
MODE0
MODE1
MODE2
MODE3
MODE4
DEBUG
RST_N
CLK
TDO
TDI
TMS
TCK
TRST_N
CD
U23
GND
B8
B7
B9
POWER
B33
B34
B35
B36
A35
B37
B12
B11
B10
B13
INPUT
C94
4U7
NCP303LSN09
C89
100N
TRST_N
DEBUG
RST_N
CLK_13M
TDO
TDI
TMS
TCK
TRST_N
RST_OUT
NC
C88
100N
1
4
U9
XS1_L2_124LGA
VDDIO_A2
VDDIO_A17
VDDIO_A36
VDDIO_A51
VDDIO_B1
VDDIO_B14
VDDIO_B29
VDDIO_B42
VDD_A19
VDD_A34
VDD_A53
VDD_A68
VDD_B15
VDD_B28
VDD_B43
VDD_B56
A2
B1
A17
A36
A51
B14
B29
B42
A19
A34
A53
A68
B15
B28
B43
B56
NC
SYSTEM SERVICES & DECOUPLING
C90
100N
+3V3
C91
100N
+3V3
1V0_PG
+1V0
+3V3
47K
R79
1V0 RESET SUPERVISOR
C112
10U
C97
10U
+3V3
1
3
A1
A2
+5V
U13
C92
10U
C82
330P
+1V0
NC7WZ07
1K8
6K8
10K
R101
R77
R81
6K8
1K5
R78
R83
VCC
Y1
Y2
GND
5
6
4
2
L2
3U3
L1
3V3_PG
NC
2U2
+3V3
1
4
3
1
NC
SW
FB
5
TRST_N
4
RST_N
RST_OUT
LX
FB
GND
2
U15
FAN2012
PVIN
VIN
EN
PGND
AGND
4
5
6
2
7
POWER SUPPLIES
U14
NCP1521B
VIN
EN
1
3
U22
NCP303LSN30
INPUT
CD
GND
2
5
3
3V3_PG
+3V3
NC
C95
4U7
+5V
+5V
C96
10U
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 27/32
1
REV
1V2
OF
1K
1
+3V3
R103
D15
GREEN
SHEET
C101
100N
PLL_LOCK
C102
100N
SHEET NAME
PROJECT NAME
CLOCKING
Copyright (c) 2009 XMOS Ltd.
DECOUPLING
C104
100N
JUN 29 2010
+3V3
XR-USB-AUDIO-2.0-MC
DIGI_MCLK
CODEC_MCLK
XCORE_MCLK
SIZE
A3
DATE
33R
33R
33R
R90
R89
R88
+3V3
8
7
5
2
4
1Y
2Y
3Y
VCC
GND
WORD_CLK
PLL_WCLK
U18
1A
2A
3A
NC7NZ34
1
3
6
+3V3
NC
BAV99
D4
1
2
WORD_CLK
PLL_WCLK
3
33R
33R
100N
1K
R28
C100
PLL_LOCK
R87
R25
+3V3
5
6
4
2
1
3
4
2
Y1
Y2
VCC
GND
VD
GND
CLK_OUT
AUX_OUT
U19
A1
A2
NC7WZ17
1
3
I2C CHIP ADDRESS = 1001110X
U16
CLK_IN
SDA/CDIN
SCL/CCLK
AD0/CS_N
FILTP
FILTN
CS2300-CP
5
9
8
6
7
10
C105
22P
PLL, INPUT SELECTION, OUTPUT BUFFERING & LOCK LED
C103
100N
I2C_SDA
I2C_SCL
1K
R86
LP -3dB Point: 7.2MHz
EXTERNAL WORD CLOCK INPUT
+3V3
5
4
2
Q
VCC
GND
0
1
75R
R85
U17
S
I0
I1
NC7SZ157
6
3
1
Signal: 2.5V p-p
2
1A
1B
1C
1D
Diode drop on supply to approx. 2V5 makes switching point more central
SYNC_SEL
SYNC_OUT
PLL_WCLK
J17
SYNC_SEL
SYNC_OUT
5-1634513-1
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 28/32
1
REV
1V2
OF
TP35
1
X1D21
X1D20
X1D19
X1D18
X1D17
X1D16
X1D15
X1D14
SHEET
MIDI_OUT_X
2
4
6
8
10
12
14
16
X1D39
J19
1
3
5
7
9
11
13
15
HEADER_RA
+3V3
5
6
4
2
SHEET NAME
Y1
Y2
PROJECT NAME
VCC
GND
Copyright (c) 2009 XMOS Ltd.
XS1_XCORE1
I2C_SDA
I2C_SCL
GPIO_0
GPIO_1
GPIO_2
GPIO_3
EXPANSION HEADER
JUN 29 2010
U2
A1
A2
NC7WZ17
XR-USB-AUDIO-2.0-MC
1
3
+3V3
X1D38
X1D38
10K
R109
SIZE
A3
DATE
MIDI_IN_X
+3V3
TP34
1K
R98
D9
+5V
NC
NC
X1D21
GREEN
1K
14
3
6
8
11
7
R97
1Y
2Y
3Y
4Y
VCC
GND
D10
X1D20
GREEN
1K
R96
U20
74HCT125
1OE_N
1A
2OE_N
2A
3OE_N
3A
4OE_N
4A
1
2
4
5
9
D11
10
13
12
X1D19
GREEN
1K
R95
+5V
D12
MIDI_OUT_X
MIDI_IN
X1D18
GREEN
1K
10K
R105
R94
MIDI IO + TEST POINTS + SIGNAL PULLUPS
D5
STATUS LEDS
NC
NC
NC
MIDI_OUT
NC
NC
X1D17
GREEN
1K
DNP
9
10
11
12
13
14
15
R93
17
D6
R99
J18
16
NC
ZDA15S
1
2
3
4
5
6
7
8
X1D16
GREEN
1K
R92
C106
100N
NC
NC
NC
NC
NC
NC
D7
+5V
X1D15
GREEN
1K
+5V
C8
100N
R100
+3V3
D14
X1D14
GREEN
ADC_SD2
ADC_SD3
SYNC_SEL
CODEC_MODE
PLL_LOCK
WORD_CLK
CODEC_INT
CODEC_RSTN
I2C_SDA
I2C_SCL
CODEC_LRCK
DAC_SD2
ADC_SD1
DAC_SD3
CODEC_SCLK
OPTICAL_TX
SYNC_OUT
COAXIAL_TX
MCLK_IN
DAC_SD1
DAC_SD4
NC
NC
NC
NC
NC
X1D14
X1D15
X1D16
X1D17
X1D18
X1D19
X1D20
X1D21
X1D38
X1D39
GPIO_0
GPIO_1
GPIO_2
GPIO_3
ADC_SD2
ADC_SD3
I2C_SDA
I2C_SCL
DAC_SD2
ADC_SD1
DAC_SD3
MCLK_IN
DAC_SD1
DAC_SD4
SYNC_SEL
PLL_LOCK
WORD_CLK
SYNC_OUT
CODEC_INT
CODEC_MODE
CODEC_RSTN
CODEC_LRCK
CODEC_SCLK
OPTICAL_TX
COAXIAL_TX
XCORE
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A21
A23
A24
A25
A26
A27
A29
A30
A31
A32
A22
A28
A20
A33
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B30
B31
U9
X1D0
X1D1
X1D2
X1D3
X1D4
X1D5
X1D6
X1D7
X1D8
X1D9
X1D10
X1D11
X1D12
X1D13
X1D14
X1D15
X1D16
X1D17
X1D18
X1D19
X1D20
X1D21
X1D22
X1D23
X1D24
X1D25
X1D26
X1D27
X1D28
X1D29
X1D30
X1D31
X1D32
X1D33
X1D34
X1D35
X1D36
X1D37
X1D38
X1D39
XS1_L2_124LGA
IO_XCORE1
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 29/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
PROJECT NAME
Copyright (c) 2009 XMOS Ltd.
DIGITAL_IO
JUN 29 2010
XR-USB-AUDIO-2.0-MC
SIZE
A3
DATE
+3V3
C12
100N
OPTICAL_RX
COAXIAL_RX
OPTICAL
COAXIAL
R4
33R
J2
RCJ-014
5
U25
FIN1002
1
2
+3V3
2
3
4
J5
VCC
IN
GND
TOTX147PL
1A
1B
1C
2
3
1
NC
NC
C116
C117
R107
470R
R106
470R
100N
100N
C11
33P
6
4
C10
T1
100N
C119
100N
FB4
DA102C
1
3
470R
R108
470R
500mA
107R
+3V3
R6
R8
820R
+3V3
C113
100N
+3V3
47P
+3V3
C114
R5
470R
500mA
R9
232R
91R
FB3
+3V3
D16
C7
100N
100N
C9
C6
PESD0603-240
100N
DIGITAL OUT - OPTICAL & COAXIAL
DIGITAL IN - OPTICAL & COAXIAL
R7
0R
+3V3
+3V3
NC
NC
5
4
2
5
4
2
3
1
2
Q
Q
2
1A
1B
1C
VCC
GND
VCC
GND
VCC
OUT
GND
Q
Q
C
C
D
D
J4
TORX147PL
J3
U24
C_N
D
CP
NC7SZ175
U1
C_N
D
CP
NC7SZ175
6
3
1
6
3
1
RCJ-014
+3V3
+3V3
MCLK
MCLK
MCLK
OPTICAL
COAXIAL
OPTICAL_TX
COAXIAL_TX
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 30/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
PROJECT NAME
PREAMP
Copyright (c) 2009 XMOS Ltd.
JUN 29 2010
XR-USB-AUDIO-2.0-MC
SIZE
A3
DATE
C65
100N
+4V1A
MIC_IN
INST_IN
C66
2N2
C68
4U7
C67
2N2
C71
GAIN IS -(200/20) = -10
R65
470R
4U7
GAIN IS -(100/100) = -1
R66
470R
7
LMV722
R60
200K
1
6
5
LMV722
U7
R62
8
4
100K
V+
V-
+4V1A
2
3
BIAS
U7
INSTRUMENT PRE AMP
MICROPHONE PRE AMP
R58
20K
BIAS
C72
4U7
R61
100K
C69
4K7
4K7
C70
4U7
R64
R63
+4V1A
2K2
4U7
R59
+4V1A
NC
NC
NC
NC
NC
NC
NC
NC
2
10
3
1
9
8
7
3
2
4
5
6
1
J13
J14
KLBRSS3
SJ-3524-SMT
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 31/32
19
Board Revision Changes
This sections lists the changes between revisions of the PCB.
19.1
Changes From 1V0 To 1V1
· Swapped R62 and R66 silkscreen labels to correct error.
· Removed GPIO test points and added GPIO connector
· Split digital I/O to use seperate ports, rather than outputs being identical and the input
being selected by a switch.
· Added testpoints for new digital I/O signals.
· Added PLL AUX LED.
· Added power sequencing to power supplies.
· Moved R75, C75 and 13M oscillator to add power sequencing.
· Changed layout of 1V0 SMPS.
· Changed L2 footprint to improve solderability.
· General tidy up and minor track changes.
19.2
Changes From 1V1 To 1V2
· Added buffer for MIDI I/O to correct 5V going into XS1-L2 I/Os.
· Added pull ups on MIDI signals to stop startup glitches.
· Added 47pf cap to slow coax output and tidied up digital out layout.
· Redesigned coaxial input for better performance and reduced cost.
· Moved the optical input track away from the 1V0 SMPS inductor.
· Moved bulk 1V0 decoupler (C93) across to far corner of L2.
· Changed most 0402 decouplers to 0603.
· Changed layout of the 13M oscillator.
· Added 5 more ground test points (next to CLK, VBUS, MIDI, DIGITAL IN and DIGITAL
OUT).
· Added silkscreen labels to all test points, apart from the codec signals in the middle of
the board.
· Added silkscreen labels for 5V DC, POWER SW, USB, XSYS and GPIO.
· Moved around R19, R52 and C34 to make it in line with other analogue outputs.
· Tidied up teardrops and changed them to curved shape.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 32/32
20
Related Documents
The following documents provide more information on designing with XMOS technol-
ogy:
· Programming XC on XMOS Devices: Explains how to program XMOS event-driven
processor devices using the XC language.
· XCore XS1 Architecture Tutorial: Provides an overview of the XS1 instruction
set architecture.
· XS1 XSystem-L: Provides an introduction on how to boot the XS1-L devices.
· XMOS Tools User Guide: Explains how to use the XMOS Tools to program XMOS
event-driven processor devices.
For the most up-to-date information including schematics and product datasheets, is
please visit:
· http://www.xmos.com/usbaudio2/
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively, the
"Information") and is providing it to you "AS IS" with no warranty of any kind, express or
implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation
that the Information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
Copyright © 2010 XMOS Ltd. All Rights Reserved. XMOS and the XMOS logo are registered
trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used
without written permission. Company and product names mentioned in this document are the
trademarks or registered trademarks of their respective owners. Where those designations
appear in this document, and XMOS was aware of a trademark claim, the designations have
been printed with initial capital letters or in all capitals.
www.xmos.com
Hardware Manual
Version 1.6
Part Number: XR-USB-AUDIO-2.0-MC
Board Version: 1V2
Publication Date: 2010/06/29
Copyright © 2010 XMOS Ltd. All Rights Reserved.
Contents
1
Release History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
3
XS1-L2 Device [A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
4
USB Connector and Transceiver [19 & I] . . . . . . . . . . . . . . . . . .
9
5
Audio CODEC [C]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
6
Digital Audio Output [13 & 14] . . . . . . . . . . . . . . . . . . . . . . .
10
7
Digital Audio Input [15 & 16]
. . . . . . . . . . . . . . . . . . . . . . . .
11
8
MIDI I/O [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
9
Audio Clocking [3 & K] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
10
SPI Flash Memory [L]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
11
XSYS Interface [18]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
12
User LEDs [I] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
13
Expansion Header [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
14
Power [1, G, H, J, M & Q] . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
15
Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
16
Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
17
Port Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
18
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
19
Board Revision Changes . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
20
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
www.xmos.com
1
Release History
Date
Version
Description
28/01/10
1.0
Initial version
05/02/10
1.1
Revisions following interval review
24/02/10
1.2
Revisions for power supply sequencing
02/03/10
1.3
Revisions for board release 1V1
27/04/10
1.4
Revisions for R102
28/05/10
1.5
Revisions for MIDI, PLL & XTAG2
29/06/10
1.6
Revisions for board release 1V2
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
4/32
2
Introduction
The USB Audio 2.0 Reference Design, XS1-L2 Edition (hereafter "the board") is a
hardware reference design for a multi-channel USB audio interface using the XMOS
XS1-L2 dual-core event-driven processor. It contains a single XS1-L2 device enabling
implementation of a complete USB 2.0 high-speed device compliant with release 2.0
of the USB Audio Class specification.
A block diagram of the design is shown below:
¼"
Pre-Amp
Mono
TRS Jack
Word Clock
User
XSYS
4Mbit
GPIO
PLL
MCLK
BNC Input
LEDs
Debug
FLASH Header
3.5mm
Pre-Amp
Mono
GPIO
JTAG
SPI
GPIO
TRS Jack
SYNC OUT & I2C
I2C
3.5mm
Passive
13MHz
Stereo
MCLK
LPF
Oscil ator
TRS Jack
USB
High Speed
USB
480Mb/s
USB
ULPI
Series B
Transciever
XMOS
3.5mm
I2S
Passive
Stereo
LPF
24 bit
TRS Jack
t
Receptacle
USB3318
XS1-L2-124QFN
192kHz
u
3.5mm
O
I2C
Audio
Passive
&
CODEC
Stereo
I
n
LPF
g
MIDI
TRS Jack
l
o
a
n
CS4244
A
Passive
3.5mm
1.8V LDO
MIDI
LPF &
Stereo
In/Out
HP Amp
TRS Jack
MCLK
3.5mm
+3V3D
Resync
Passive
3.3V DC-DC
Stereo
LPF
TRS Jack
+5V IN
3.5mm
L1 Core
Passive
1.0V DC-DC
Supply
Stereo
LPF
TRS Jack
Optical
Coaxial
Optical
Coaxial
CODEC
Digital
Digital
Digital
Digital
3.5mm
RC LP Filter
Analogue
Passive
Audio Rx
Audio Rx
Audio Tx
Audio Tx
Stereo
Supply
LPF
TRS Jack
The XS1-L2 event-driven processor communicates with the USB host via a ULPI USB
transceiver at the 480Mb/s high-speed rate. The XS1-L2 controls the streaming of
audio data over the USB connection and direct I2S interface to the audio CODEC, digital
streams and MIDI communications. Multiple additional functions (e.g. Mixers/DSP
etc.) can be implemented by modifications to the standard software.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2.1
Feature Overview
Key features of the board are as follows:
· Support for standard sample rates - 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
176.4kHz, 192kHz
· Six channels of analogue line level input
· Eight channels of analogue line level output
· Optical and coaxial digital audio input (S/PDIF or ADAT)
· Optical and coaxial digital audio output (S/PDIF or ADAT)
· MIDI input and output
· Word (house) clock input to allow synchronization to an external clock
· Integrated instrument and microphone pre-amplifier
· Integrated headphone amplifier on analogue outputs 1/2
· Powered via USB bus or external 5V source
· XMOS XSYS debug header for easy programming/debug from the host using the
XMOS XTAG2 debug adapter
· Eight LEDs for programmable use
· Expansion header with I2C and twelve general purpose IOs for programmable use
· Multiple test-points to allow connection of custom ADC/DAC hardware etc
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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2.2
Board Components
The diagram below shows the layout of the main components of the board:
D
C
B
E
F
P
G
H
A
I
O
Q
J
L
M
K
N
A
XS1-L2 Device
J
1V0 Core Supply
B
Audio CODEC
K
13MHz Oscillator
C
Headphone Pre-Amp
L
4Mb SPI FLASH
D
Instrument & Mic Pre-Amp
M
Power Supply Protection & Fuse
E
Audio CODEC Clock Buffers
N
Case LED Power Connector
F
PLL & Clock Distribution
O
8 x User Programmable LEDs
G
4V1 Analogue Supply
P
PLL Auxiliary Output LED
H
3V3 Digital Supply
Q
USB & Power On LEDs
I
USB Transceiver
The rest of this document provides a detailed description of each of the main board
components.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
7/32
2.3
Connectors
The diagram below shows the layout of the connectors on the board:
5
6
7
8
9
10
11
12
4
13
3
14
15
2
16
20
19
1
18
17
1
5V DC Power In
11
Analogue 5/6 OUT (Stereo 3.5mm
Jack)
2
MIDI Input & Output (Via Gameport)
12
Analogue 7/8 OUT (Stereo 3.5mm
Jack)
3
75
BNC Word Clock Input
13
Optical Digital Output
4
Instrument IN (Mono 1/4" Jack)
14
Coaxial Digital Output
5
Microphone IN (Mono 3.5mm Jack)
15
Optical Digital Input
6
Analogue 1/2 IN (Stereo 3.5mm Jack)
16
Coaxial Digital Input
7
Analogue 3/4 IN (Stereo 3.5mm Jack)
17
Expansion Header
8
Analogue 5/6 IN (Stereo 3.5mm Jack)
18
XSYS Debug Interface
9
Analogue 1/2 OUT (Stereo 3.5mm
19
USB B Connector
Jack)
10
Analogue 3/4 OUT (Stereo 3.5mm
20
Push Button Power Switch
Jack)
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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3
XS1-L2 Device [A]
The board is based on a single XS1-L2 device in a 124 pin QFN package.
The XS1-L2 consists of a two XCore processors. Each XCore comprises an event-
driven multi-threaded processor with tightly integrated general purpose I/O pins, 64
KBytes of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
XCore processors have time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports are provided in
Programming XC on XMOS Devices available from www.xmos.com.
3.1
Clocking [K]
A discrete 13MHz pierce oscillator is used to feed the XS1-L2 reference clock input
and also the USB3318 USB transceiver. The L2 has MODE1 and MODE0 pins wired to
ground which sets the internal XS1-L2 PLL multiplication factor to 30.75. This results
in a default core clock frequency of 399.75MHz and an I/O reference clock frequency
of 99.9375MHz.
3.2
Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide
a reset to the L2. This ensures the device is reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset over
the XSYS debug interface.
3.3
Boot
The boot mode of the XS1-L2 is set by the MODE3 and MODE2 pins which are
connected together on the board.
With MODE3 and MODE2 both high (default), the device will boot from the 4Mb SPI
FLASH on the board. With MODE3 and MODE2 both low, the device will not boot
from SPI FLASH, thus instead allowing boot via JTAG using the XSYS debug link.
To allow automatic boot mode selection based on debug hardware presence the
MODE2 and MODE3 pins are connected to the TRST_N of the debug connector.
Without debug hardware connected to the XSYS interface, the board will boot from
SPI FLASH. With the XTAG2 connected to the XSYS interface, the host can control the
boot mode of the device by way of the TRST_N line. This functionality is provided
purely for developer convenience. A typical production board might use a jumper or
switch for manual boot mode selection if JTAG boot is required.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6)
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The MODE4 pin is held low on the board. This causes the second XCore to boot from
a link connected to first XCore, rather than its own SPI FLASH.
4
USB Connector and Transceiver [19 & I]
The board uses a standard USB series B receptacle for USB connectivity.
The high-speed USB signals are connected to an SMSC® USB3318 USB transceiver
which provides a ULPI connection to XCore 0 of the XS1-L2.
On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L2 is
ready to begin USB activity. The USB transceiver reset pin is connected to port X0P1M
of the XS1-L2 in order that it can be controlled by software.
The transceiver uses the 13MHz clock provided by a discrete oscillator which doubles
as the reference clock for the XS1-L2.
5
Audio CODEC [C]
The board is equiped with a 24 bit, 192kHz multi-channel audio CODEC (Cirrus
Logic® CS42448).
The CODEC is configured via an I2C serial configuration interface with slave address
0x48.
The CODEC can be configured to provide audio clocks (master mode) or with all
clocks being inputs (slave mode).
The CODEC has seperate LRCLK and SCLK I/Os for ADC and DAC. These are both
connected to a single I/O pin on the XCore. Clock buffers are provided for SCLK and
LRCLK I/Os to remove any potential contention issues.
The control pin (CODEC_MODE) for the buffers is mapped to bit 1 of port X1P4A on
the XS1-L2.
CODEC_MODE
Clock Mode
0
Clocks Connected
1
Clocks Disconnected
When using the codec in slave mode the clocks should be connected together.
The CODEC has three internal modes depending on the sampling rate used. These
change the oversampling ratio used internally in the CODEC. The three modes are
shown below:
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 10/32
CODEC mode
CODEC sample rate range
Single speed
4-50kHz
Double speed
50-100kHz
Quad speed
100-200kHz
The reset input to the CODEC is mapped to bit 3 of port X1P4A on the XS1-L2.
The interrupt output from the CODEC is mapped to bit 3 of port X1P4B on the XS1-L2.
5.1
Analogue Audio I/O [4 - 12]
3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio inputs and
outputs. The layout of the audio jacks is shown in the connector diagram of the
board.
A simple passive AC-coupling and low pass filter circuit is used on input and output.
The circuit is configured such that the audio output will produce approximately
0.94VRMS (-0.54dBV) for a digital full scale signal. Due to the output coupling
capacitors, the output impedance falls with frequency and is approximately 1k
@
35Hz falling to 576
@ 1kHz.
The input circuit contains an attenuator such that a 1.62VRMS (+4.2dBV) signal will
produce a full scale digital output. The input impedance is approximately 9k .
The CODEC microphone and instrument inputs are AC-coupled to low noise op-amp
pre-amplifiers before being AC-coupled onto the CODEC inputs. These are set with
gains of -1 and -10 for the instrument and microphone inputs respectively.
A 3.5mm Tip Ring Sleeve (TRS) audio jack is provided for the stereo headphone out,
which is powered by a 75mW TI TPA152 stereo headphone amplifier. This is the a
capable of driving a minimum load of 32 . It is configured with a gain of -1.
6
Digital Audio Output [13 & 14]
Optical and coaxial digital audio transmitters are used to provide digital audio output
in formats such as IEC60958 consumer mode (S/PDIF) and ADAT. The signals are
generated from two 1-bit ports on the XS1-L2 as defined in the port map.
The data streams from the XS1-L2 are re-clocked using the external master clock
to synchronise the data into the audio clock domain. This is achieved using simple
external D-type flip-flops.
The optical output uses a TOSLINK optical connector with an integrated LED and
differential driving circuit. The coaxial output uses an RCA connector and is isolated
via a transformer.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 11/32
7
Digital Audio Input [15 & 16]
Digital audio input is provided to allow formats such as IEC60958 consumer mode
(S/PDIF) or ADAT to be connected to the device via either optical or coaxial mediums.
The optical input uses a TOSLINK optical connector with an integrated photodiode
and receiver circuit. The coaxial input uses an RCA connector and is AC-coupled into
a 75
terminator.
This gives a signal level of 0.5Vp-p, which is fed into a differential line receiver.
The input signals are fed into two 1-bit ports on the processor as defined in the port
map.
8
MIDI I/O [2]
Musical Instrument Digital Interface input and output is provided on the board via a
standard Gameport connector. The signals are buffered using 5V line drivers and are
then connected to 1-bit ports on the XS1-L2, via a 5V to 3.3V buffer.
10K
pull ups are placed on the MIDI IN signal from the connector and on the MIDI
OUT signal from the XCore. These stop glitches on startup and when no MIDI devices
are connected to the board.
The MIDI input and output signals are connected to the XS1-L2 as follows:
Port
Signal
X1P1P
MIDI_IN
X1P1O
MIDI_OUT
Standard MIDI devices (using DIN 5/180 connectors) are attached using a Gameport
to dual DIN MIDI cable. This is not included in the kit, but are easily purchased from
other suppliers.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 12/32
9
Audio Clocking [3 & K]
In order to accommodate a multitude of clocking options, the low-jitter master clock
(e.g. 256 x fs), is generated locally using a fractional-N frequency multiplier PLL chip.
The source for the PLL is either the SYNC_OUT signal from the XS1-L2 or the word
clock input as controlled by the SYNC_SEL signal.
The SYNC_SEL signal is mapped to bit 0 of port X1P4A on the XS1-L2 as shown in the
port map.
The behaviour of this select signal is as follows:
SYNC_SEL
PLL clock source
0
XS1-L2 SYNC_OUT
1
Word Clock Input
The Cirrus Logic CS2300-CP PLL chip generates a low-jitter output of between 6-
75MHz from any 50Hz-30MHz input clock.
A variety of clock sources can be used, including:
· Local crystal oscillator, via XCore clock block (which divides 13MHz down to the
SYNC_OUT signal).
· S/PDIF software recovered clock (which then drives the SYNC_OUT signal).
· Word clock input.
The SYNC_OUT signal is connected to both cores of the XS1-L2, but a DNF resistor
(R102) normally only allows XCore 1 to output the signal. Fit a 0R 0603 resistor to
enable XCore 0 to output the signal.
The audio master clock is connected to both cores of the XS1-L2 on ports X0P1L and
X1P1L, to allow the audio output streams on that XCore to be synchronized.
The CS2300-CP is configured over the I2C bus (shared with the CODEC) at slave
address 0x47.
The CS2300-CP auxiliary output drives an LED to indicate the state of the signal. For
example, this could show if the PLL is locked or not.
A 75
terminated BNC input is provided for an external word clock ("house clock")
input. The input accepts a 0-5V (5Vp-p, 2.5V offset) signal, which is low-pass filtered
to remove high frequency components, and schmitt triggered to remove problems
with noise and non-monotonic edges.
This signal is also fed to a 1-bit port on the XS1-L2. This allows the application code
to detect if a word clock input signal is present.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 13/32
10
SPI Flash Memory [L]
A 4Mbit FLASH memory device is provided, connected via a standard Serial Peripheral
Interface (SPI).
The FLASH is connected to four 1-bit ports as shown in the table below. These are
the standard ports the processor will try to boot from in SPI boot mode.
Port
SPI Signal
X0P1A
MISO
X0P1B
SS
X0P1C
CLK
X0P1D
MOSI
The XMOS development tools include the XFLASH utility for programming compiled
programs into the flash memory via the XS1-L2. Software may also access the FLASH
memory at run-time by interfacing with the above ports.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 14/32
11
XSYS Interface [18]
A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory via the XS1-L2 and selection of boot
mode. It is not recommended to use an original (FTDI based) XTAG with the L2
device, as this is not as fast as the XTAG2 and can have signal drive strength issues.
A 20-way IDC header is used as the physical connector and the pinout of this is
shown below:
Signal
Pin
Description
TRST_N
3
JTAG Test Reset. Active low
TMS
7
JTAG Test Mode Select
TCK
9
JTAG Test Clock
TD1
5
JTAG Test Data. From debug adapter to XS1-L2
TD2
13
JTAG Test Data. From XS1-L2 to debug adapter
SRST_N
15
System Reset. Active low. Resets XS1-L2 device
DEBUG
11
XS1-L2 DEBUG Interrupt line
XMOS-LINK
6, 10, 14, 18
This is a 2-wire XMOS-Link for advanced debug
GND
4, 8, 12, 16, 20
Ground
NC
1, 2, 17, 19
These pins are not connected
As discussed in the Boot section the XS1-L2 MODE2 and MODE3 pins are connected
to the TRST_N signal.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 15/32
12
User LEDs [I]
The board provides eight user LEDs that can be driven by software. These are marked
on the board as LED 0 though to LED 7. The LEDs are connected to port X1P8B, the
bit mapping is shown in the table below:
Port
LED
X1P8B0
LED 0
X1P8B1
LED 1
X1P8B2
LED 2
X1P8B3
LED 3
X1P8B4
LED 4
X1P8B5
LED 5
X1P8B6
LED 6
X1P8B7
LED 7
The LED connections are also shown in the port map. Setting the relevant bit high
will turn the LED on.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 16/32
13
Expansion Header [17]
The board provides a general purpose input/output expansion header to allow
interfacing to custom boards. For example, this could be an I2C display, eight LEDs
and four buttons to make a user interface.
The header contains the following:
· +3V3 power pin.
· Ground pin.
· I2C bus (as used to configure the PLL and CODEC).
· One 4-bit GPIO port (X1P4F).
· One 8-bit GPIO port, which is also shared with the LED outputs (X1P8B).
A 16-way IDC header is used as the physical connector and the pinout of this is
shown below:
Pin
Port
Signal
1
NA
+3V3
2
X1P8B7
LED_7
3
NA
GND
4
X1P8B6
LED_6
5
X1P1C0
I2C_SDA
6
X1P8B5
LED_5
7
X1P1D0
I2C_SCL
8
X1P8B4
LED_4
9
X1P4F0
GPIO_0
10
X1P8B3
LED_3
11
X1P4F1
GPIO_1
12
X1P8B2
LED_2
13
X1P4F2
GPIO_2
14
X1P8B1
LED_1
15
X1P4F3
GPIO_3
16
X1P8B0
LED_0
Each IO pin can source or sink a maximum of 4mA.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 17/32
14
Power [1, G, H, J, M & Q]
The board is powered from the onboard +5V DC power connector or from the USB
bus. Note that the board has not been designed as a bus-powered device due to
pre-enumeration current limits.
The two different power supplies are "ORd" together using Schottky diodes with a
maximum voltage drop of 0.34V. A 750mA resettable polyfuse and reverse polarity
protection, via a bidirectional zener diode, is provided. Ferrite beads are used on the
+5V VBus and +5V DC power input to prevent switching noise propagating down the
USB and power cables.
A latching push-button power switch is fitted to the board that activates a p-channel
MOSFET (which has an Rds(on) of approximately 80m ). A soft start circuit is
included to limit the inrush current.
When powered from the USB bus all the power used by the board is derived from the
nominally +5V VBus supply from the USB connector. The board will use approximately
300mA when fully configured and operating.
The required core and IO voltages for the XS1-L2 are derived from 5V as follows:
· A low cost 1.5A buck switching regulator is used to generate the 1.0V core
supply for the XS1-L2.
· A low cost 600mA buck switching regulator is used to generate the global 3.3V
supply.
Switching regulators are used on these power supplies due to their high efficiency.
The power supplies are sequenced using a 3.0V voltage supervisor on the 3.3V
supply output, to drive the enable input on the 1.0V supply. This makes sure that
the 3.3V supply is up and stable, before the 1.0V supply comes up and also provides
predictable behaviour under brownout conditions, by causing a reset if the supplies
droop significantly.
A simple low drop out (LDO) linear regulator is used to generate the 1.8V supply
required by the USB3318 USB transceiver.
A low noise LDO regulator is used to generate the analogue supply for the Audio
CODEC. The CODEC offers higher audio performance at higher supply voltages so the
voltage for this supply is set at 4.1V. This allows some headroom between the 4.5V
minimum VBus voltage and the approx 350mV dropout of the LDO + RC pre-filter.
When the board is correctly connected to a USB source the USB VBUS Power LED is
illuminated.
When the board is powered on the Power LED is illuminated.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 18/32
15
Printed Circuit Board
The PCB is a 1.6mm four layer design in a XMOS XS1-G Development Kit form factor
with dimensions of 180 x 120mm. It is made from FR4 (r = 4.5) material and
finished in immersion gold. The mounting holes are 3.2mm in diameter.
Signal stack up is as follows:
· Top signal
· Ground plane
· Power plane
· Bottom signal
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 19/32
16
Test Points
16.1
Test Points by ID
Test Point
Port
Signal
TP1
NA
+5V
TP2
NA
+4V1A
TP3
NA
+3V3
TP4
NA
+1V8
TP5
NA
+1V0
TP6
NA
OSC_13M
TP8
NA
PLL_WCLK
TP9
NA
VBUS
TP10
X0P1J0
OPTICAL_RX
TP11
X1P1N0
DAC_SD4
TP12
X1P1H0
DAC_SD3
TP13
X1P1F0
DAC_SD2
TP14
X1P1M0
DAC_SD1
TP15
X1P1I0
CODEC_SCLK
TP16
X1P1E0
CODEC_LRCK
TP17
X1P1D0
I2C_SCL
TP18
X1P1C0
I2C_SDA
TP19
X1P4A3
CODEC_RSTN
TP20
X1P1B0
ADC_SD3
TP21
X1P1A0
ADC_SD2
TP22
X1P1G0
ADC_SD1
TP23
X1P4B3
CODEC_INT
TP24
X0P1L0 & X1P1L0
XCORE_MCLK
TP25
X0P1C0 & X1P4E0
SYNC_OUT
TP26
X1P4A0
SYNC_SEL
TP27
X1P1K0
COAXIAL_TX
TP28
X1P4A1
CODEC_MODE
TP29
X1P4B1
PLL_LOCK
TP30
X0P1K0
COAXIAL_RX
TP31
X1P1J0
OPTICAL_TX
TP34
X1P1O0
MIDI_OUT
TP35
X1P1P0
MIDI_IN
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 20/32
16.2
Test Points by Signal
16.2.1
Power
Signal
Port
Test Point
+1V0
NA
TP5
+1V8
NA
TP4
+3V3
NA
TP3
+4V1A
NA
TP2
+5V
NA
TP1
VBUS
NA
TP9
16.2.2
XS1-L2 System
Signal
Port
Test Point
OSC_13M
NA
TP6
PLL_LOCK
X1P4B1
TP29
16.2.3
Audio Clocking
Signal
Port
Test Point
SYNC_SEL
X1P4A0
TP26
PLL_WCLK
NA
TP8
SYNC_OUT
X0P1C0 * & X1P4E0
TP25
XCORE_MCLK
X0P1L0 & X1P1L0
TP24
* Enabled via DNF resistor R102.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 21/32
16.2.4
Codec Audio
Signal
Port
Test Point
ADC_SD1
X1P1G0
TP22
ADC_SD2
X1P1A0
TP21
ADC_SD3
X1P1B0
TP20
DAC_SD1
X1P1M0
TP14
DAC_SD2
X1P1F0
TP13
DAC_SD3
X1P1H0
TP12
DAC_SD4
X1P1N0
TP11
CODEC_LRCLK
X1P1E0
TP16
CODEC_SCLK
X1P1I0
TP15
16.2.5
Codec Config/Status
Signal
Port
Test Point
CODEC_INT
X1P4B3
TP23
CODEC_MODE
X1P4A1
TP28
CODEC_RST
X1P4A3
TP19
I2C_SCL
X1P1D0
TP17
I2C_SDA
X1P1C0
TP18
16.2.6
Digital Audio
Signal
Port
Test Point
OPTICAL_RX
X0P1J0
TP10
OPTICAL_TX
X1P1J0
TP31
COAXIAL_RX
X0P1K0
TP30
COAXIAL_TX
X1P1K0
TP27
16.2.7
MIDI
Signal
Port
Test Point
MIDI_OUT
X1P1O0
TP34
MIDI_IN
X1P1P0
TP35
Unmarked test points are connected to ground.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 22/32
17
Port Map
The table below provides a full description of the port to signal mappings used on
the board.
Pin
Port
XCore
1b
4b
8b
16b
0
1
XD0
P1A0
SPI_MISO
ADC_SD2
XD1
P1B0
SPI_SS
ADC_SD3
XD2
P4A0
P8A0
P16A0
SYNC_SEL
NA
XD3
P4A1
P8A1
P16A1
CODEC_MODE
XD4
P4B0
P8A2
P16A2
NA
XD5
P4B1
P8A3
P16A3
PLL_LOCK
XSYS Link
XD6
P4B2
P8A4
P16A4
WORD_CLK
XD7
P4B3
P8A5
P16A5
CODEC_INT
XD8
P4A2
P8A6
P16A6
NA
NA
XD9
P4A3
P8A7
P16A7
CODEC_RST_N
XD10
P1C0
SPI_CLK / SYNC_OUT *
I2C_SDA
XD11
P1D0
SPI_MOSI
I2C_SCL
XD12
P1E0
ULPI_STP
CODEC_LRCK
XD13
P1F0
ULPI_NXT
DAC_SD2
XD14
P4C0
P8B0
P16A8
XD15
P4C1
P8B1
P16A9
XD16
P4D0
P8B2
P16A10
XD17
P4D1
P8B3
P16A11
ULPI_DATA[0:7]
LEDS[0:7]
XD18
P4D2
P8B4
P16A12
XD19
P4D3
P8B5
P16A13
XD20
P4C2
P8B6
P16A14
XD21
P4C3
P8B7
P16A15
XD22
P1G0
ULPI_DIR
ADC_SD1
XD23
P1H0
ULPI_CLK
DAC_SD3
XD24
P1I0
WORD_CLK
CODEC_SCLK
XD25
P1J0
OPTICAL_RX
OPTICAL_TX
XD26
P4E0
P8C0
P16B0
SYNC_OUT
XD27
P4E1
P8C1
P16B1
NA
XD28
P4F0
P8C2
P16B2
XD29
P4F1
P8C3
P16B3
NA
GPIO[0:3]
XD30
P4F2
P8C4
P16B4
XD31
P4F3
P8C5
P16B5
XD32
P4E2
P8C6
P16B6
NA
XD33
P4E3
P8C7
P16B7
XD34
P1K0
COAXIAL_RX
COAXIAL_TX
XD35
P1L0
MCLK_IN
MCLK_IN
XD36
P1M0
P8D0
P16B8
ULPI_RST
DAC_SD1
XD37
P1N0
P8D1
P16B9
DAC_SD4
XD38
P1O0
P8D2
P16B10
MIDI_OUT
XD39
P1P0
P8D3
P16B11
MIDI_IN
XD40
P8D4
P16B12
NA
XD41
P8D5
P16B13
NA
XD42
P8D6
P16B14
XD43
P8D7
P16B15
* Enabled via DNF resistor R102.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 23/32
18
Schematics
1
REV
1V2
OF
1
+4V1A
+1V8
VBUS
1K
+5V
R30
SHEET
D13
+5V
+3V3
+1V0
OSC_13M
PLL_WCLK
OPTICAL_RX
COAXIAL_RX
GREEN
1K
SHEET NAME
TP1
TP2
TP3
TP4
TP5
TP9
TP6
TP8
PROJECT NAME
TP10
TP30
VBUS
R91
POWER LEDS
D8
TOP_LEVEL
Copyright (c) 2009 XMOS Ltd.
GREEN
FIDUCIALS & TPS
JUN 29 2010
XR-USB-AUDIO-2.0-MC
FM1
FM2
FM3
FM4
FM5
FM6
SIZE
A3
DATE
TP20
TP21
TP22
TP29
TP26
TP25
TP31
TP27
TP28
TP23
JP1
1
2
+5V
XL_UP1
XL_UP0
XL_DN0
XL_DN1
CLK_13M
ADC_SD3
ADC_SD2
ADC_SD1
XS1_SYSTEM
10K
PLL_LOCK
SYNC_SEL
SYNC_OUT
WORD_CLK
CODEC_INT
OPTICAL_TX
COAXIAL_TX
CODEC_MODE
+5V
R104
BLEEDER R
OSC_13M
NC
POWER_ON_N
ADC_SD3
ADC_SD2
ADC_SD1
PLL_LOCK
SYNC_SEL
SYNC_OUT
WORD_CLK
1
2
3
CODEC_INT
XL_UP1
XL_UP0
XL_DN0
XL_DN1
OPTICAL_TX
COAXIAL_TX
CODEC_MODE
OSC_13M
SW1
MECH1
SWITCH_CAP
PN12SHNA03QE
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
MCLK_IN
I2C_SCL
I2C_SDA
CODEC_RSTN
WORD_CLK
SYNC_OUT
MCLK_IN
OPTICAL_RX
COAXIAL_RX
XS1_CORE1
XS1_CORE0
+5V
3
D
C5
G
MTH4
MTH3
MTH2
MTH1
1
100N
2
S
PTH_M3
PTH_M3
PTH_M3
PTH_M3
Q1
NTR4101P
MOUNTING HOLES
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
XCORE_MCLK
I2C_SCL
I2C_SDA
CODEC_RSTN
OPTICAL_RX
COAXIAL_RX
1K
R2
R3
10K
TP11
TP12
TP13
TP14
TP15
TP16
TP24
TP17
TP18
TP19
I2C_SCL
I2C_SDA
WORD_CLK
SYNC_OUT
SYNC_SEL
PLL_LOCK
PLL_WCLK
D1
DIGI_MCLK
XCORE_MCLK
CODEC_MCLK
SMBJ5.0A
SUB SHEETS & CODEC TPS
F1
0.75A
POWER_ON_N
I2C_SCL
I2C_SDA
TP55
TP56
TP57
TP58
TP59
WORD_CLK
SYNC_OUT
SYNC_SEL
PLL_LOCK
PLL_WCLK
ADC_SD3
ADC_SD2
ADC_SD1
DIGI_MCLK
XCORE_MCLK
CODEC_MCLK
CODEC_INT
CODEC_MODE
D2
D3
MBR120VLSFT
MBR120VLSFT
TP50
CLOCKING
TP51
TP52
TP53
TP54
INT
C3
100N
MODE
5V DC POWER INPUT, PROTECTION, FILTERING & SWITCH
ADC_SD3
ADC_SD2
ADC_SD1
VBUS
330R
1700mA
TP45
TP46
TP47
TP48
TP49
FB2
C4
100N
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
SCLK
LRCK
MCLK
I2C_SCL
I2C_SDA
RST_N
MCLK
OPTICAL_RX
COAXIAL_RX
OPTICAL_TX
COAXIAL_TX
CODEC
DIGITAL_IO
GROUND TEST POINTS
TP38
TP41
TP42
TP43
TP44
2
1A
1B
3
J1
PJ-014D-SMT
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
CODEC_SCLK
CODEC_LRCK
CODEC_MCLK
I2C_SCL
I2C_SDA
CODEC_RSTN
DIGI_MCLK
OPTICAL_RX
COAXIAL_RX
OPTICAL_TX
COAXIAL_TX
TP7
TP32
TP33
TP36
TP37
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 24/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
CODEC
PROJECT NAME
J8
SJ-3524-SMT
J9
SJ-3524-SMT
J10
SJ-3524-SMT
J11
SJ-3524-SMT
2
3
1
2
3
1
2
3
1
2
3
1
Copyright (c) 2009 XMOS Ltd.
10
10
10
10
JUN 29 2010
NC
NC
NC
NC
XR-USB-AUDIO-2.0-MC
R31
33R
R29
33R
1K
C34
2N2
C35
2N2
C37
2N2
C36
2N2
C38
2N2
C39
2N2
1K
R17
R16
SIZE
A2
DATE
100U
100U
R52
470R
R53
470R
R55
R54
470R
470R
R56
470R
R57
470R
C61
C64
20K
4U7
4U7
4U7
4U7
4U7
4U7
10K
10K
10K
10K
10K
10K
R10
R19
R20
R22
R21
R23
R24
20K
C55
C56
C58
C57
C59
C60
R11
+4V1A
6
1
5
7
VDD
VO1
VO2
GND
R12
20K
R13
20K
C53
4U7
U6
MUTE
IN1-
IN2-
BYPASS
TPA152
2
8
4
3
C13
1U
C50
4U7
C24
100N
HEADPHONE AMP
+4V1A
C63
100U
C21
100N
R15
20K
R14
20K
AIN6B
AIN5B
+4V1A
C23
100N
4U7
4U7
MIC_IN
INST_IN
C52
C54
C62
100U
PREAMPS
C31
2N2
C33
2N2
PREAMP
C22
100N
R50
NC
NC
NC
NC
NC
NC
NC
NC
NC
470R
R51
470R
26
25
27
28
30
29
31
32
34
33
36
37
39
38
40
41
35
43
55
54
VQ
MUTEC
AOUT1P
AOUT1N
AOUT2P
AOUT2N
AOUT3P
AOUT3N
AOUT4P
AOUT4N
AOUT5P
AOUT5N
AOUT6P
AOUT6N
AOUT7P
AOUT7N
AOUT8P
AOUT8N
CS42448
FILTP_ADC
FILTP_DAC
C110
2U2
C16
100N
+4V1A
VA_5353
VA_44
AGND_56
44
56AGND_42
42
C15
100N
C18
100N
+4V1A
C108
100P
VD_2424
VD_6
DGND_62
6
62DGND_23
10K
4K3
23
VLS
DGND_7
8
7
C14
100N
C17
100N
R26
R27
VLC4
+3V3
C25
4U7
C26
4U7
+3V3
+4V1A
C109
100N
6
5
4
U3
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
AIN5P/AIN5A
AIN5N/AIN5B
AIN6P/AIN6A
AIN6N/AIN6B
AUX_SDIN
AUX_SCLK
AUX_LRCK
ADC_SDOUT3
ADC_SDOUT2
ADC_SDOUT1
ADC_SCLK
ADC_LRCK
DAC_SDIN4
DAC_SDIN3
DAC_SDIN2
DAC_SDIN1
DAC_SCLK
DAC_LRCK
MCLK
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS_N
INT
RST_N
9
5
2
1
3
46
45
48
47
50
49
52
51
58
57
60
59
22
21
20
11
12
13
14
15
16
17
18
19
10
63
64
61
FB
NR
OUT
4K7
R46
NC
NC
AIN5B
AIN6B
INT
U21
TPS73001
IN
EN
GND
R49
4K7
RST_N
1
3
2
ADC_SCLK
ADC_LRCK
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
4K7
R43
4K7
C107
4U7
SCLK
LRCK
MCLK
ADC_SD3
ADC_SD2
ADC_SD1
C45
4U7
R42
DAC_SD4
DAC_SD3
DAC_SD2
DAC_SD1
4V1A LDO REGULATOR
I2C_SCL
I2C_SDA
R1
1R
C44
4U7
VREF = 1.225V
VOUT = 1.225 * (1 + 10K/4K3) = 4.07V
C1
100N
4K7
R44
+3V3
C43
4U7
4K7
R45
+3V3
470R
500mA
C42
4U7
FB1
C2
100N
+5V
I2C Chip Address is 1001000X (X is R/nW bit)
I2C_SCL
I2C_SDA
C32
2N2
C40
2N2
C28
2N2
C27
2N2
C29
2N2
C30
2N2
C51
C41
C46
C47
C49
C48
C19
100N
+3V3
4U7
4U7
4U7
4U7
4U7
4U7
4K7
4K7
4K7
4K7
4K7
4K7
R48
R33
R37
R34
R38
R41
C20
100N
+3V3
R47
4K7
R32
4K7
R36
4K7
R35
4K7
R39
4K7
R40
4K7
ADC_SCLK
ADC_LRCK
+3V3
+3V3
NC
NC
NC
5
4
3
5
4
3
Y
Y
VCC
GND
VCC
GND
2
10
3
1
2
10
3
1
2
10
3
1
J6
J7
J12
U5
NC7SZ125
U4
NC7SZ125
SJ-3524-SMT
SJ-3524-SMT
SJ-3524-SMT
1
2
1
2
ADC CLK BUFFERS
OE_N
A
OE_N
A
10K
R18
+3V3
MODE
SCLK
LRCK
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 25/32
1
REV
1V2
OF
1
+3V3
SHEET
X0D0
8
2
4
SO
VCC
GND
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET NAME
PROJECT NAME
100N
Copyright (c) 2009 XMOS Ltd.
XS1_XCORE0
C75
U10
AT25DF041A
SI
SCK
WP_N
HOLD_N
CS_N
4MBIT
JUN 29 2010
5
6
3
7
1
R71
33R
R72
33R
R73
33R
R74
33R
XR-USB-AUDIO-2.0-MC
XSYS XMOS-LINK
10K
SPI BOOT FLASH
X0D4
X0D5
X0D6
X0D7
R69
+3V3
SIZE
A3
DATE
X0D11
X0D10
X0D1
J15
USB_B
VBUS
1U
C73
VBUS
DM
DP
GND
S1
S2
1
2
3
4
5
6
R75
+3V3
DNP
C77
100N
1700mA
330R
C74
10N
C76
FB5
100N
VBUS
X0D36
OSC_13M
+1V8
R68
1K
R70
C79
100N
NC
NC
10K
+3V3
DM
DP
C80
2U2
3
4
17
21
2
5
6
1
7
23
22
U8
DM
DP
ID
+1V8
VBAT
VBUS
CPEN
VDD33
VDDIO
VDD18
REFCLK
RESETB
USB3318
USB PHY
NC
5
4
NC
VOUT
1V8 LDO & DECOUPLING
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
STP
NXT
DIR
CLKOUT
RBIAS
GND
9
8
GND
16
15
14
13
11
10
20
18
19
12
24
25
2
U11
NCP699SN18
VIN
EN
1
3
R67
8K06
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D12
X0D13
X0D22
X0D23
+5V
C78
100N
WORD_CLK
OPTICAL_RX
COAXIAL_RX
MCLK_IN
SYNC_OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
X0D0
X0D1
X0D4
X0D5
X0D6
X0D7
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D36
DNP
R102
XCORE
A15
A16
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A55
A57
A58
A59
A60
A61
A63
A64
A65
A66
A56
A62
A54
A67
B38
B39
B40
B41
B44
B45
B46
B47
A4
A3
B48
B49
B50
B51
B52
B53
B54
B55
X0D10
U9
X0D0
X0D1
X0D2
X0D3
X0D4
X0D5
X0D6
X0D7
X0D8
X0D9
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
XS1_L2_124LGA
IO_XCORE0
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 26/32
1
REV
1V2
OF
1
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET
CLK_13M
NC
C83
100N
+3V3
XL_UP1
XL_UP0
XL_DN0
XL_DN1
SHEET NAME
PROJECT NAME
2
4
6
8
10
12
14
16
18
20
470R
Copyright (c) 2009 XMOS Ltd.
CLK_13M
XS1_SYSTEM
C98
33P
J16
R84
1
3
5
7
9
11
13
15
17
19
HEADER_RA
JUN 29 2010
4
U12
NC7SZU04
XR-USB-AUDIO-2.0-MC
5
3
X1
R76
2M2
13M
XSYS HEADER
+3V3
ABLS2
2
13MHz OSCILLATOR
NC
TRST_N
TDI
TMS
TCK
DEBUG
TDO
RST_N
NC
NC
C99
33P
SIZE
A3
DATE
10K
R80
+5V NC, So Cannot Be Powered By XTAG2
+3V3
2R2
C81
1U
R82
+1V0
C93
4U7
+1V0
C85
100N
+3V3
NC
NC
CLK_13M
C84
100N
10N
B32
B4
B5
B3
B2
B6
A38
A37
A1
A18
A52
PAD
CONFIG
C87
100N
C111
GND_A1
PCU_VDD
PCU_CLK
GND_A18
GND_A52
GND_PAD
PCU_GATE
PCU_WAKE
PLL_AVDD
PLL_AGND
OTP_VDDIO
PCU_VDDIO
+1V0
C86
100N
2
5
3
U9
XS1_L2_124LGA
MODE0
MODE1
MODE2
MODE3
MODE4
DEBUG
RST_N
CLK
TDO
TDI
TMS
TCK
TRST_N
CD
U23
GND
B8
B7
B9
POWER
B33
B34
B35
B36
A35
B37
B12
B11
B10
B13
INPUT
C94
4U7
NCP303LSN09
C89
100N
TRST_N
DEBUG
RST_N
CLK_13M
TDO
TDI
TMS
TCK
TRST_N
RST_OUT
NC
C88
100N
1
4
U9
XS1_L2_124LGA
VDDIO_A2
VDDIO_A17
VDDIO_A36
VDDIO_A51
VDDIO_B1
VDDIO_B14
VDDIO_B29
VDDIO_B42
VDD_A19
VDD_A34
VDD_A53
VDD_A68
VDD_B15
VDD_B28
VDD_B43
VDD_B56
A2
B1
A17
A36
A51
B14
B29
B42
A19
A34
A53
A68
B15
B28
B43
B56
NC
SYSTEM SERVICES & DECOUPLING
C90
100N
+3V3
C91
100N
+3V3
1V0_PG
+1V0
+3V3
47K
R79
1V0 RESET SUPERVISOR
C112
10U
C97
10U
+3V3
1
3
A1
A2
+5V
U13
C92
10U
C82
330P
+1V0
NC7WZ07
1K8
6K8
10K
R101
R77
R81
6K8
1K5
R78
R83
VCC
Y1
Y2
GND
5
6
4
2
L2
3U3
L1
3V3_PG
NC
2U2
+3V3
1
4
3
1
NC
SW
FB
5
TRST_N
4
RST_N
RST_OUT
LX
FB
GND
2
U15
FAN2012
PVIN
VIN
EN
PGND
AGND
4
5
6
2
7
POWER SUPPLIES
U14
NCP1521B
VIN
EN
1
3
U22
NCP303LSN30
INPUT
CD
GND
2
5
3
3V3_PG
+3V3
NC
C95
4U7
+5V
+5V
C96
10U
=
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 27/32
1
REV
1V2
OF
1K
1
+3V3
R103
D15
GREEN
SHEET
C101
100N
PLL_LOCK
C102
100N
SHEET NAME
PROJECT NAME
CLOCKING
Copyright (c) 2009 XMOS Ltd.
DECOUPLING
C104
100N
JUN 29 2010
+3V3
XR-USB-AUDIO-2.0-MC
DIGI_MCLK
CODEC_MCLK
XCORE_MCLK
SIZE
A3
DATE
33R
33R
33R
R90
R89
R88
+3V3
8
7
5
2
4
1Y
2Y
3Y
VCC
GND
WORD_CLK
PLL_WCLK
U18
1A
2A
3A
NC7NZ34
1
3
6
+3V3
NC
BAV99
D4
1
2
WORD_CLK
PLL_WCLK
3
33R
33R
100N
1K
R28
C100
PLL_LOCK
R87
R25
+3V3
5
6
4
2
1
3
4
2
Y1
Y2
VCC
GND
VD
GND
CLK_OUT
AUX_OUT
U19
A1
A2
NC7WZ17
1
3
I2C CHIP ADDRESS = 1001110X
U16
CLK_IN
SDA/CDIN
SCL/CCLK
AD0/CS_N
FILTP
FILTN
CS2300-CP
5
9
8
6
7
10
C105
22P
PLL, INPUT SELECTION, OUTPUT BUFFERING & LOCK LED
C103
100N
I2C_SDA
I2C_SCL
1K
R86
LP -3dB Point: 7.2MHz
EXTERNAL WORD CLOCK INPUT
+3V3
5
4
2
Q
VCC
GND
0
1
75R
R85
U17
S
I0
I1
NC7SZ157
6
3
1
Signal: 2.5V p-p
2
1A
1B
1C
1D
Diode drop on supply to approx. 2V5 makes switching point more central
SYNC_SEL
SYNC_OUT
PLL_WCLK
J17
SYNC_SEL
SYNC_OUT
5-1634513-1
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 28/32
1
REV
1V2
OF
TP35
1
X1D21
X1D20
X1D19
X1D18
X1D17
X1D16
X1D15
X1D14
SHEET
MIDI_OUT_X
2
4
6
8
10
12
14
16
X1D39
J19
1
3
5
7
9
11
13
15
HEADER_RA
+3V3
5
6
4
2
SHEET NAME
Y1
Y2
PROJECT NAME
VCC
GND
Copyright (c) 2009 XMOS Ltd.
XS1_XCORE1
I2C_SDA
I2C_SCL
GPIO_0
GPIO_1
GPIO_2
GPIO_3
EXPANSION HEADER
JUN 29 2010
U2
A1
A2
NC7WZ17
XR-USB-AUDIO-2.0-MC
1
3
+3V3
X1D38
X1D38
10K
R109
SIZE
A3
DATE
MIDI_IN_X
+3V3
TP34
1K
R98
D9
+5V
NC
NC
X1D21
GREEN
1K
14
3
6
8
11
7
R97
1Y
2Y
3Y
4Y
VCC
GND
D10
X1D20
GREEN
1K
R96
U20
74HCT125
1OE_N
1A
2OE_N
2A
3OE_N
3A
4OE_N
4A
1
2
4
5
9
D11
10
13
12
X1D19
GREEN
1K
R95
+5V
D12
MIDI_OUT_X
MIDI_IN
X1D18
GREEN
1K
10K
R105
R94
MIDI IO + TEST POINTS + SIGNAL PULLUPS
D5
STATUS LEDS
NC
NC
NC
MIDI_OUT
NC
NC
X1D17
GREEN
1K
DNP
9
10
11
12
13
14
15
R93
17
D6
R99
J18
16
NC
ZDA15S
1
2
3
4
5
6
7
8
X1D16
GREEN
1K
R92
C106
100N
NC
NC
NC
NC
NC
NC
D7
+5V
X1D15
GREEN
1K
+5V
C8
100N
R100
+3V3
D14
X1D14
GREEN
ADC_SD2
ADC_SD3
SYNC_SEL
CODEC_MODE
PLL_LOCK
WORD_CLK
CODEC_INT
CODEC_RSTN
I2C_SDA
I2C_SCL
CODEC_LRCK
DAC_SD2
ADC_SD1
DAC_SD3
CODEC_SCLK
OPTICAL_TX
SYNC_OUT
COAXIAL_TX
MCLK_IN
DAC_SD1
DAC_SD4
NC
NC
NC
NC
NC
X1D14
X1D15
X1D16
X1D17
X1D18
X1D19
X1D20
X1D21
X1D38
X1D39
GPIO_0
GPIO_1
GPIO_2
GPIO_3
ADC_SD2
ADC_SD3
I2C_SDA
I2C_SCL
DAC_SD2
ADC_SD1
DAC_SD3
MCLK_IN
DAC_SD1
DAC_SD4
SYNC_SEL
PLL_LOCK
WORD_CLK
SYNC_OUT
CODEC_INT
CODEC_MODE
CODEC_RSTN
CODEC_LRCK
CODEC_SCLK
OPTICAL_TX
COAXIAL_TX
XCORE
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A21
A23
A24
A25
A26
A27
A29
A30
A31
A32
A22
A28
A20
A33
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B30
B31
U9
X1D0
X1D1
X1D2
X1D3
X1D4
X1D5
X1D6
X1D7
X1D8
X1D9
X1D10
X1D11
X1D12
X1D13
X1D14
X1D15
X1D16
X1D17
X1D18
X1D19
X1D20
X1D21
X1D22
X1D23
X1D24
X1D25
X1D26
X1D27
X1D28
X1D29
X1D30
X1D31
X1D32
X1D33
X1D34
X1D35
X1D36
X1D37
X1D38
X1D39
XS1_L2_124LGA
IO_XCORE1
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 29/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
PROJECT NAME
Copyright (c) 2009 XMOS Ltd.
DIGITAL_IO
JUN 29 2010
XR-USB-AUDIO-2.0-MC
SIZE
A3
DATE
+3V3
C12
100N
OPTICAL_RX
COAXIAL_RX
OPTICAL
COAXIAL
R4
33R
J2
RCJ-014
5
U25
FIN1002
1
2
+3V3
2
3
4
J5
VCC
IN
GND
TOTX147PL
1A
1B
1C
2
3
1
NC
NC
C116
C117
R107
470R
R106
470R
100N
100N
C11
33P
6
4
C10
T1
100N
C119
100N
FB4
DA102C
1
3
470R
R108
470R
500mA
107R
+3V3
R6
R8
820R
+3V3
C113
100N
+3V3
47P
+3V3
C114
R5
470R
500mA
R9
232R
91R
FB3
+3V3
D16
C7
100N
100N
C9
C6
PESD0603-240
100N
DIGITAL OUT - OPTICAL & COAXIAL
DIGITAL IN - OPTICAL & COAXIAL
R7
0R
+3V3
+3V3
NC
NC
5
4
2
5
4
2
3
1
2
Q
Q
2
1A
1B
1C
VCC
GND
VCC
GND
VCC
OUT
GND
Q
Q
C
C
D
D
J4
TORX147PL
J3
U24
C_N
D
CP
NC7SZ175
U1
C_N
D
CP
NC7SZ175
6
3
1
6
3
1
RCJ-014
+3V3
+3V3
MCLK
MCLK
MCLK
OPTICAL
COAXIAL
OPTICAL_TX
COAXIAL_TX
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 30/32
1
REV
1V2
OF
1
SHEET
SHEET NAME
PROJECT NAME
PREAMP
Copyright (c) 2009 XMOS Ltd.
JUN 29 2010
XR-USB-AUDIO-2.0-MC
SIZE
A3
DATE
C65
100N
+4V1A
MIC_IN
INST_IN
C66
2N2
C68
4U7
C67
2N2
C71
GAIN IS -(200/20) = -10
R65
470R
4U7
GAIN IS -(100/100) = -1
R66
470R
7
LMV722
R60
200K
1
6
5
LMV722
U7
R62
8
4
100K
V+
V-
+4V1A
2
3
BIAS
U7
INSTRUMENT PRE AMP
MICROPHONE PRE AMP
R58
20K
BIAS
C72
4U7
R61
100K
C69
4K7
4K7
C70
4U7
R64
R63
+4V1A
2K2
4U7
R59
+4V1A
NC
NC
NC
NC
NC
NC
NC
NC
2
10
3
1
9
8
7
3
2
4
5
6
1
J13
J14
KLBRSS3
SJ-3524-SMT
=
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USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 31/32
19
Board Revision Changes
This sections lists the changes between revisions of the PCB.
19.1
Changes From 1V0 To 1V1
· Swapped R62 and R66 silkscreen labels to correct error.
· Removed GPIO test points and added GPIO connector
· Split digital I/O to use seperate ports, rather than outputs being identical and the input
being selected by a switch.
· Added testpoints for new digital I/O signals.
· Added PLL AUX LED.
· Added power sequencing to power supplies.
· Moved R75, C75 and 13M oscillator to add power sequencing.
· Changed layout of 1V0 SMPS.
· Changed L2 footprint to improve solderability.
· General tidy up and minor track changes.
19.2
Changes From 1V1 To 1V2
· Added buffer for MIDI I/O to correct 5V going into XS1-L2 I/Os.
· Added pull ups on MIDI signals to stop startup glitches.
· Added 47pf cap to slow coax output and tidied up digital out layout.
· Redesigned coaxial input for better performance and reduced cost.
· Moved the optical input track away from the 1V0 SMPS inductor.
· Moved bulk 1V0 decoupler (C93) across to far corner of L2.
· Changed most 0402 decouplers to 0603.
· Changed layout of the 13M oscillator.
· Added 5 more ground test points (next to CLK, VBUS, MIDI, DIGITAL IN and DIGITAL
OUT).
· Added silkscreen labels to all test points, apart from the codec signals in the middle of
the board.
· Added silkscreen labels for 5V DC, POWER SW, USB, XSYS and GPIO.
· Moved around R19, R52 and C34 to make it in line with other analogue outputs.
· Tidied up teardrops and changed them to curved shape.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 32/32
20
Related Documents
The following documents provide more information on designing with XMOS technol-
ogy:
· Programming XC on XMOS Devices: Explains how to program XMOS event-driven
processor devices using the XC language.
· XCore XS1 Architecture Tutorial: Provides an overview of the XS1 instruction
set architecture.
· XS1 XSystem-L: Provides an introduction on how to boot the XS1-L devices.
· XMOS Tools User Guide: Explains how to use the XMOS Tools to program XMOS
event-driven processor devices.
For the most up-to-date information including schematics and product datasheets, is
please visit:
· http://www.xmos.com/usbaudio2/
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively, the
"Information") and is providing it to you "AS IS" with no warranty of any kind, express or
implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation
that the Information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
Copyright © 2010 XMOS Ltd. All Rights Reserved. XMOS and the XMOS logo are registered
trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used
without written permission. Company and product names mentioned in this document are the
trademarks or registered trademarks of their respective owners. Where those designations
appear in this document, and XMOS was aware of a trademark claim, the designations have
been printed with initial capital letters or in all capitals.
www.xmos.com
Document Outline
- Release History
- Introduction
- XS1-L2 Device [A]
- USB Connector and Transceiver [19 & I]
- Audio CODEC [C]
- Digital Audio Output [13 & 14]
- Digital Audio Input [15 & 16]
- MIDI I/O [2]
- Audio Clocking [3 & K]
- SPI Flash Memory [L]
- XSYS Interface [18]
- User LEDs [I]
- Expansion Header [17]
- Power [1, G, H, J, M & Q]
- Printed Circuit Board
- Test Points
- Port Map
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