XS3 definitions

Processor state registers

Processor State Registers (also called “processor status registers” or “processor configuration registers”) are registers that exist on a specific tile, and can be accessed with a single instruction (either getps or setps). From C, getps() and setps() can be used.

group xs3a PS Registers

PS_DBG_SCRATCH

A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG.

This is the same set of registers as the Debug Scratch registers in the xCORE tile configuration.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_SCRATCH

XS1_PS_DBG_SCRATCH_0

PS_DBG_SCRATCH 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_1

PS_DBG_SCRATCH 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_2

PS_DBG_SCRATCH 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_3

PS_DBG_SCRATCH 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_4

PS_DBG_SCRATCH 4 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_5

PS_DBG_SCRATCH 5 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_6

PS_DBG_SCRATCH 6 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_7

PS_DBG_SCRATCH 7 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_IBREAK_ADDR

This register contains the address of the instruction breakpoint.

If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_IBREAK_ADDR

XS1_PS_DBG_IBREAK_ADDR_0

PS_DBG_IBREAK_ADDR 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_1

PS_DBG_IBREAK_ADDR 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_2

PS_DBG_IBREAK_ADDR 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_3

PS_DBG_IBREAK_ADDR 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_IBREAK_CTRL

This register controls which logical cores may take an instruction breakpoint, and under which condition.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

IBRK_CONDITION When 0 break when PC == IBREAK_ADDR. When 1 = break when PC != IBREAK_ADDR.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_IBREAK_CTRL

XS1_PS_DBG_IBREAK_CTRL_0

PS_DBG_IBREAK_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_1

PS_DBG_IBREAK_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_2

PS_DBG_IBREAK_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_3

PS_DBG_IBREAK_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_ADDR1

This set of registers contains the first address for the four data watchpoints.

Condition A of a watchpoint is met if the effective address of an instruction is greater than or equal to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition A or B, or both A and B.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_DWATCH_ADDR1

XS1_PS_DBG_DWATCH_ADDR1_0

PS_DBG_DWATCH_ADDR1 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_1

PS_DBG_DWATCH_ADDR1 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_2

PS_DBG_DWATCH_ADDR1 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_3

PS_DBG_DWATCH_ADDR1 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_ADDR2

This set of registers contains the second address for the four data watchpoints.

Condition B of a watchpoint is met if the effective address of an instruction is less than or equal to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition A or B, or both A and B.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_DWATCH_ADDR2

XS1_PS_DBG_DWATCH_ADDR2_0

PS_DBG_DWATCH_ADDR2 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_1

PS_DBG_DWATCH_ADDR2 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_2

PS_DBG_DWATCH_ADDR2 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_3

PS_DBG_DWATCH_ADDR2 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_CTRL

This set of registers controls each of the four data watchpoints.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

DBRK_CONDITION Determines the break condition: 0 = A AND B, 1 = A OR B.

BRK_LOAD When 1 the breakpoints will be be triggered on loads.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_DWATCH_CTRL

XS1_PS_DBG_DWATCH_CTRL_0

PS_DBG_DWATCH_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_1

PS_DBG_DWATCH_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_2

PS_DBG_DWATCH_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_3

PS_DBG_DWATCH_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_ADDR1

This set of registers contains the mask for the four resource watchpoints.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_RWATCH_ADDR1

XS1_PS_DBG_RWATCH_ADDR1_0

PS_DBG_RWATCH_ADDR1 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_1

PS_DBG_RWATCH_ADDR1 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_2

PS_DBG_RWATCH_ADDR1 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_3

PS_DBG_RWATCH_ADDR1 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_ADDR2

This set of registers contains the value for the four resource watchpoints.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_RWATCH_ADDR2

XS1_PS_DBG_RWATCH_ADDR2_0

PS_DBG_RWATCH_ADDR2 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_1

PS_DBG_RWATCH_ADDR2 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_2

PS_DBG_RWATCH_ADDR2 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_3

PS_DBG_RWATCH_ADDR2 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_CTRL

This set of registers controls each of the four resource watchpoints.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

RBRK_CONDITION When 0 break when condition A is met. When 1 = break when condition B is met.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_RWATCH_CTRL

XS1_PS_DBG_RWATCH_CTRL_0

PS_DBG_RWATCH_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_1

PS_DBG_RWATCH_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_2

PS_DBG_RWATCH_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_3

PS_DBG_RWATCH_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

Defines

XS1_PS_RAM_BASE

PS_RAM_BASE processor state register ID.

Use getps() and setps() to access.

This register contains the base address of the RAM. It is initialized to 0x00080000.

Sub-Fields:

WORD_ADDRESS_BITS Most significant 16 bits of all addresses.

XS1_PS_VECTOR_BASE

PS_VECTOR_BASE processor state register ID.

Use getps() and setps() to access.

Base address of event vectors in each resource. On an interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least significant 16 bits come from the event vector.

Sub-Fields:

VECTOR_BASE The event and interrupt vectors.

XS1_PS_XCORE_CTRL0

PS_XCORE_CTRL0 processor state register ID.

Use getps() and setps() to access.

Register to control features in the xCORE tile

Sub-Fields:

XCORE_CTRL0_EXTMEM_ENABLE Enable External memory interface

XCORE_CTRL0_USB_ENABLE Enable the USB hardware support module

XCORE_CTRL0_CLK_DIVIDER_EN Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes.

XCORE_CTRL0_CLK_DIVIDER_DYN Select the dynamic mode (1) for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active threads are paused. In static mode the clock divider is always enabled.

XCORE_CTRL0_MIPI_ENABLE Enable MIPI interface periph ports

XCORE_CTRL0_MEMSLEEP_ENABLE Enable memory auto-sleep feature

XCORE_CTRL0_RAMSHUTDOWN Disable RAMs to save power (contents will be lost)

XCORE_CTRL0_EXTMEM_DEVICE_SIZE Specify size of a connected LPDDR device (options are: 128,256,512Mbits, 1Gbit),

XS1_PS_BOOT_CONFIG

PS_BOOT_CONFIG processor state register ID.

Use getps() to access.

This read-only register describes the boot status of the xCORE tile.

Sub-Fields:

BOOT_CONFIG_PLL_MODE_PINS The boot PLL mode pin value.

BOOT_CONFIG_BOOT_FROM_JTAG Boot ROM boots from JTAG

BOOT_CONFIG_BOOT_FROM_RAM Boot ROM boots from RAM

BOOT_CONFIG_DISABLE_OTP_POLL Cause the ROM to not poll the OTP for correct read levels

BOOT_CONFIG_SECURE_BOOT Overwrite BOOT_MODE.

BOOT_CONFIG_PROCESSOR Processor number.

XS1_PS_BOOT_STATUS

PS_BOOT_STATUS processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

BOOT_STATUS_LEDS Boot status LED value.

BOOT_STATUS_BITS Other boot status LED bits.

XS1_PS_SECURITY_CONFIG

PS_SECURITY_CONFIG processor state register ID.

Use getps() and setps() to access.

Copy of the security register as read from OTP.

Sub-Fields:

SECUR_CFG_DISABLE_XCORE_JTAG Disable access to XCore’s JTAG debug TAP

SECUR_CFG_DISABLE_PLL_JTAG Disable JTAG access to the PLL/BOOT configuration registers

SECUR_CFG_SECURE_BOOT Override boot mode and read boot image from OTP

SECUR_CFG_OTP_COMBINED Combine OTP into a single address-space for reading.

SECUR_CFG_OTP_PROGRAM_DISABLE Prevent access to OTP SBPI interface to prevent programming and other functions.

SECUR_CFG_OTP_READ_LOCK Disable read access to OTP.

SECUR_CFG_DISABLE_GLOBAL_DEBUG Disable access to XCore’s global debug

SECUR_CFG_DISABLE_ACCESS Disables write permission on this register

XS1_PS_RING_OSC_CTRL

PS_RING_OSC_CTRL processor state register ID.

Use getps() and setps() to access.

There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator has been stopped for at least 10 core clock cycles (this can be achieved by inserting two nop instructions between the SETPS and GETPS). The counter values can be read using two subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits.

Sub-Fields:

RING_OSC_PERPH_ENABLE Set to 1 to enable the core peripheral ring oscillator.

RING_OSC_CORE_ENABLE Core ring oscillator enable.

XS1_PS_RING_OSC_DATA0

PS_RING_OSC_DATA0 processor state register ID.

Use getps() to access.

This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA1

PS_RING_OSC_DATA1 processor state register ID.

Use getps() to access.

This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA2

PS_RING_OSC_DATA2 processor state register ID.

Use getps() to access.

This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA3

PS_RING_OSC_DATA3 processor state register ID.

Use getps() to access.

This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_UNAVAILABLE_RESOURCE

PS_UNAVAILABLE_RESOURCE processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

RAM_MASK Blocks of 64k rams unavailable

CORE1_DISABLE Core 1’s clock is gated off

THREAD_MASK Threads unavailable

XS1_PS_RAM_SIZE

PS_RAM_SIZE processor state register ID.

Use getps() to access.

The size of the RAM in bytes

Sub-Fields:

WORD_ADDRESS_BITS Most significant 16 bits of all addresses.

XS1_PS_ROM_RMA

PS_ROM_RMA processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

RTSEL ROM debug timing adjust.

PTSEL ROM debug timing adjust.

TRB ROM debug timing adjust.

XS1_PS_DBG_SSR

PS_DBG_SSR processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SSR register when the debugger was called.

Sub-Fields:

SR_EEBLE 1 when events are enabled for the thread.

SR_IEBLE 1 when interrupts are enabled for the thread.

SR_INENB 1 when in an event enabling sequence.

SR_ININT 1 when in an interrupt handler.

SR_INK 1 when in kernel mode.

SR_WAITING 1 when the thread is paused waiting for events, a lock or another resource.

SR_FAST 1 when the thread is in fast mode and will continually issue.

SR_DI 1 when in dual issue mode.

SR_KEDI 1 if, on kernel entry, the thread will switch to dual issue.

SR_QUEUE 1 if in high priority mode

XS1_PS_DBG_SPC

PS_DBG_SPC processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SPC register when the debugger was called.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_SSP

PS_DBG_SSP processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SSP register when the debugger was called.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_T_NUM

PS_DBG_T_NUM processor state register ID.

Use getps() to access. Only accessible in debug mode.

The resource ID of the logical core whose state is to be read.

Sub-Fields:

DBG_T_NUM_NUM Thread number to be read

XS1_PS_DBG_T_REG

PS_DBG_T_REG processor state register ID.

Use getps() to access. Only accessible in debug mode.

Register number to be read by DGETREG

Sub-Fields:

DBG_T_REG_REG Register number to be read

XS1_PS_DBG_TYPE

PS_DBG_TYPE processor state register ID.

Use getps() to access. Only accessible in debug mode.

Register that specifies what activated the debug interrupt.

Sub-Fields:

DBG_TYPE_CAUSE Indicates the cause of the debug interrupt

1: Host initiated a debug interrupt through JTAG

2: Program executed a DCALL instruction

3: Instruction breakpoint

4: Data watch point

5: Resource watch point

DBG_TYPE_T_NUM Number of thread which caused the debug interrupt (always 0 in the case of =HOST=).

DBG_TYPE_HW_NUM Number of the hardware breakpoint/watchpoint which caused the interrupt (always 0 for =HOST= and =DCALL=). If multiple breakpoints/watchpoints trigger at once, the lowest number is taken.

XS1_PS_DBG_DATA

PS_DBG_DATA processor state register ID.

Use getps() to access. Only accessible in debug mode.

On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger. On a resource watchpoint, it countains the resource identifier.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_RUN_CTRL

PS_DBG_RUN_CTRL processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented.

Sub-Fields:

DBG_RUN_CTRL_STOP 1-hot vector defining which threads are stopped when not in debug mode. Every bit which is set prevents the respective thread from running.

XS1_PS_CACHE_MISS_CNT

PS_CACHE_MISS_CNT processor state register ID.

Use getps() to access.

This is a free running, unresetable, read-only counter incremented on every cache miss by any thread to either SWMEM or EXTMEM.

Sub-Fields:

ALL_BITS Value.

XS1_PS_CACHE_ACCESS_CNT

PS_CACHE_ACCESS_CNT processor state register ID.

Use getps() to access.

This is a free running, unresetable, read-only counter incremented on every cache access by any thread to either SWMEM or EXTMEM.

Sub-Fields:

ALL_BITS Value.

Processor switch registers

Processor Switch Registers (also called “PSWITCH registers” or “tile configuration registers”) are registers that exist on a specific tile, and can be accessed using channels. From C, read_pswitch_reg() and write_pswitch_reg() can be used.

group xs3a PSWITCH Registers

PSWITCH_DBG_SCRATCH

A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch.

This is the same set of registers as the Debug Scratch registers in the processor status.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PSWITCH_DBG_SCRATCH

XS1_PSWITCH_DBG_SCRATCH_0_NUM

PSWITCH_DBG_SCRATCH 0 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_1_NUM

PSWITCH_DBG_SCRATCH 1 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_2_NUM

PSWITCH_DBG_SCRATCH 2 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_3_NUM

PSWITCH_DBG_SCRATCH 3 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_4_NUM

PSWITCH_DBG_SCRATCH 4 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_5_NUM

PSWITCH_DBG_SCRATCH 5 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_6_NUM

PSWITCH_DBG_SCRATCH 6 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_7_NUM

PSWITCH_DBG_SCRATCH 7 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Defines

XS1_PSWITCH_DEVICE_ID0_NUM

PSWITCH_DEVICE_ID0 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register identifies the xCORE Tile

Sub-Fields:

DEVICE_ID0_VERSION XCore version.

DEVICE_ID0_REVISION XCore revision.

DEVICE_ID0_NODE Number of the node in which this XCore is located.

DEVICE_ID0_PID Processor ID of this XCore.

XS1_PSWITCH_DEVICE_ID1_NUM

PSWITCH_DEVICE_ID1 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile.

Sub-Fields:

DEVICE_ID1_NUM_THREADS Number of threads.

DEVICE_ID1_NUM_SYNCS Number of synchronisers.

DEVICE_ID1_NUM_LOCKS Number of the locks.

DEVICE_ID1_NUM_CHANENDS Number of channel ends.

XS1_PSWITCH_DEVICE_ID2_NUM

PSWITCH_DEVICE_ID2 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register describes the number of timers and clock blocks available on this xCORE tile.

Sub-Fields:

DEVICE_ID2_NUM_TIMERS Number of timers.

DEVICE_ID2_NUM_CLKBLKS Number of clock blocks.

XS1_PSWITCH_DEVICE_ID3_NUM

PSWITCH_DEVICE_ID3 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_CTRL_NUM

PSWITCH_DBG_CTRL processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile configuration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect.

Sub-Fields:

DBG_CTRL_PSWITCH_RO_EXT When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch

DBG_CTRL_PSWITCH_RO When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch, XCore(PS_DBG_Scratch) and JTAG

XS1_PSWITCH_DBG_INT_NUM

PSWITCH_DBG_INT processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register can be used to raise a debug interrupt in this xCORE tile.

Sub-Fields:

DBG_INT_REQ_DBG Request a debug interrupt on the processor.

DBG_INT_IN_DBG 1 when the processor is in debug mode.

XS1_PSWITCH_PLL_CLK_DIVIDER_NUM

PSWITCH_PLL_CLK_DIVIDER processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register

Sub-Fields:

PLL_CLK_DIVIDER Clock divider.

PLL_CLK_DISABLE Clock disable. Writing ‘1’ will remove the clock to the tile.

XS1_PSWITCH_SECU_CONFIG_NUM

PSWITCH_SECU_CONFIG processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Copy of the security register as read from OTP.

Sub-Fields:

SECUR_CFG_DISABLE_XCORE_JTAG Disable access to XCore’s JTAG debug TAP

SECUR_CFG_DISABLE_PLL_JTAG Disable JTAG access to the PLL/BOOT configuration registers

SECUR_CFG_SECURE_BOOT Override boot mode and read boot image from OTP

SECUR_CFG_OTP_COMBINED Combine OTP into a single address-space for reading.

SECUR_CFG_OTP_PROGRAM_DISABLE Prevent access to OTP SBPI interface to prevent programming and other functions.

SECUR_CFG_OTP_READ_LOCK Disable read access to OTP.

SECUR_CFG_DISABLE_GLOBAL_DEBUG Disable access to XCore’s global debug

SECUR_CFG_DISABLE_ACCESS Disables write permission on this register

XS1_PSWITCH_T0_PC_NUM

PSWITCH_T0_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 0.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T1_PC_NUM

PSWITCH_T1_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 1.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T2_PC_NUM

PSWITCH_T2_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 2.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T3_PC_NUM

PSWITCH_T3_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 3.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T4_PC_NUM

PSWITCH_T4_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 4.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T5_PC_NUM

PSWITCH_T5_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 5.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T6_PC_NUM

PSWITCH_T6_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 6.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T7_PC_NUM

PSWITCH_T7_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 7.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T0_SR_NUM

PSWITCH_T0_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 0

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T1_SR_NUM

PSWITCH_T1_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 1

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T2_SR_NUM

PSWITCH_T2_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 2

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T3_SR_NUM

PSWITCH_T3_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 3

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T4_SR_NUM

PSWITCH_T4_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 4

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T5_SR_NUM

PSWITCH_T5_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 5

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T6_SR_NUM

PSWITCH_T6_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 6

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T7_SR_NUM

PSWITCH_T7_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 7

Sub-Fields:

ALL_BITS Value.

System switch registers

System Switch Registers (also called “SSWITCH registers” or “node configuration registers”) are registers that are shared between all tiles on a chip, and can be accessed through the interconnect using channels. From C, read_sswitch_reg() and write_sswitch_reg() can be used.

group xs3a SSWITCH Registers

SSWITCH_SLINK

These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of.

The registers control links 0..7.

Sub-Fields:

LINK_SRC_INUSE 1 when the source side of the link is in use.

LINK_DST_INUSE 1 when the dest side of the link is in use.

LINK_JUNK 1 when the current packet is considered junk and will be thrown away.

LINK_NETWORK Determines the network to which this link belongs, reset as 0.

LINK_DIRECTION The direction that this link operates in.

SLINK_SRC_TARGET_ID When the link is in use, this is the destination link number to which all packets are sent.

SLINK_SRC_TARGET_TYPE Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_NUM_SSWITCH_SLINK

XS1_SSWITCH_SLINK_0_NUM

SSWITCH_SLINK 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_1_NUM

SSWITCH_SLINK 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_2_NUM

SSWITCH_SLINK 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_3_NUM

SSWITCH_SLINK 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_4_NUM

SSWITCH_SLINK 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_5_NUM

SSWITCH_SLINK 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_6_NUM

SSWITCH_SLINK 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_7_NUM

SSWITCH_SLINK 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_8_NUM

SSWITCH_SLINK 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_PLINK

These registers contain status information and the network number that each processor-link belongs to.

Sub-Fields:

LINK_SRC_INUSE 1 when the source side of the link is in use.

LINK_DST_INUSE 1 when the dest side of the link is in use.

LINK_JUNK 1 when the current packet is considered junk and will be thrown away.

LINK_NETWORK Determines the network to which this link belongs, reset as 0.

PLINK_SRC_TARGET_ID When the link is in use, this is the destination link number to which all packets are sent.

PLINK_SRC_TARGET_TYPE Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_NUM_SSWITCH_PLINK

XS1_SSWITCH_PLINK_0_NUM

SSWITCH_PLINK 0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_1_NUM

SSWITCH_PLINK 1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_2_NUM

SSWITCH_PLINK 2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_3_NUM

SSWITCH_PLINK 3 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_4_NUM

SSWITCH_PLINK 4 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_5_NUM

SSWITCH_PLINK 5 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_6_NUM

SSWITCH_PLINK 6 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_7_NUM

SSWITCH_PLINK 7 system switch register number.

Use read_sswitch_reg() to access.

SSWITCH_XLINK

These registers contain configuration and debugging information specific to external links.

The link speed and width can be set, the link can be initialized, and the link status can be monitored. The registers control links 0..7.

Sub-Fields:

XLINK_INTER_TOKEN_DELAY Specify min. number of idle system clocks between two continuous transmit tokens -1.

XLINK_INTRA_TOKEN_DELAY Specify min. number of idle system clocks between two continuous symbols witin a transmit token -1.

XLINK_RX_RESET Reset the receiver. The next symbol that is detected will be the first symbol in a token.

XLINK_HELLO Clear this end of the xlink’s credit and issue a HELLO token.

TX_CREDIT This end of the xlink has credit to allow it to transmit.

RX_CREDIT This end of the xlink has issued credit to allow the remote end to transmit

XLINK_RX_ERROR Rx buffer overflow or illegal token encoding received.

XLINK_WIDE 0: operate in 2 wire mode; 1: operate in 5 wire mode

XLINK_ENABLE Write to this bit with ‘1’ will enable the XLink, writing ‘0’ will disable it. This bit controls the muxing of ports with overlapping xlinks.

XS1_NUM_SSWITCH_XLINK

XS1_SSWITCH_XLINK_0_NUM

SSWITCH_XLINK 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_1_NUM

SSWITCH_XLINK 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_2_NUM

SSWITCH_XLINK 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_3_NUM

SSWITCH_XLINK 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_4_NUM

SSWITCH_XLINK 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_5_NUM

SSWITCH_XLINK 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_6_NUM

SSWITCH_XLINK 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_7_NUM

SSWITCH_XLINK 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_8_NUM

SSWITCH_XLINK 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_XSTATIC

These registers are used for static (ie, non-routed) links.

When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order.

Sub-Fields:

XSTATIC_DEST_CHAN_END The destination channel end on this node that packets received in static mode are forwarded to.

XSTATIC_DEST_PROC The destination processor on this node that packets received in static mode are forwarded to.

XSTATIC_ENABLE Enable static forwarding.

XS1_NUM_SSWITCH_XSTATIC

XS1_SSWITCH_XSTATIC_0_NUM

SSWITCH_XSTATIC 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_1_NUM

SSWITCH_XSTATIC 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_2_NUM

SSWITCH_XSTATIC 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_3_NUM

SSWITCH_XSTATIC 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_4_NUM

SSWITCH_XSTATIC 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_5_NUM

SSWITCH_XSTATIC 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_6_NUM

SSWITCH_XSTATIC 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_7_NUM

SSWITCH_XSTATIC 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_MIPI_XCFGI_REG

Internal MIPI config registers

XS1_NUM_SSWITCH_MIPI_XCFGI_REG

XS1_SSWITCH_MIPI_XCFGI_REG_0_NUM

SSWITCH_MIPI_XCFGI_REG 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_1_NUM

SSWITCH_MIPI_XCFGI_REG 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_2_NUM

SSWITCH_MIPI_XCFGI_REG 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_3_NUM

SSWITCH_MIPI_XCFGI_REG 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_4_NUM

SSWITCH_MIPI_XCFGI_REG 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_5_NUM

SSWITCH_MIPI_XCFGI_REG 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_6_NUM

SSWITCH_MIPI_XCFGI_REG 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_7_NUM

SSWITCH_MIPI_XCFGI_REG 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_8_NUM

SSWITCH_MIPI_XCFGI_REG 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_9_NUM

SSWITCH_MIPI_XCFGI_REG 9 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_10_NUM

SSWITCH_MIPI_XCFGI_REG 10 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_11_NUM

SSWITCH_MIPI_XCFGI_REG 11 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_12_NUM

SSWITCH_MIPI_XCFGI_REG 12 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_13_NUM

SSWITCH_MIPI_XCFGI_REG 13 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_14_NUM

SSWITCH_MIPI_XCFGI_REG 14 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_15_NUM

SSWITCH_MIPI_XCFGI_REG 15 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_16_NUM

SSWITCH_MIPI_XCFGI_REG 16 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_17_NUM

SSWITCH_MIPI_XCFGI_REG 17 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_18_NUM

SSWITCH_MIPI_XCFGI_REG 18 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_MIPI_XCFGO_REG

Internal MIPI config registers

XS1_NUM_SSWITCH_MIPI_XCFGO_REG

XS1_SSWITCH_MIPI_XCFGO_REG_0_NUM

SSWITCH_MIPI_XCFGO_REG 0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGO_REG_1_NUM

SSWITCH_MIPI_XCFGO_REG 1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGO_REG_2_NUM

SSWITCH_MIPI_XCFGO_REG 2 system switch register number.

Use read_sswitch_reg() to access.

Defines

XS1_SSWITCH_DEVICE_ID0_NUM

SSWITCH_DEVICE_ID0 system switch register number.

Use read_sswitch_reg() to access.

This register contains version and revision identifiers and the mode-pins as sampled at boot-time.

Sub-Fields:

SS_DEVICE_ID0_VERSION SSwitch version.

SS_DEVICE_ID0_REVISION SSwitch revision.

SS_DEVICE_ID0_BOOT_CTRL Sampled values of BootCtl pins on Power On Reset.

XS1_SSWITCH_DEVICE_ID1_NUM

SSWITCH_DEVICE_ID1 system switch register number.

Use read_sswitch_reg() to access.

This register specifies the number of processors and links that are connected to this switch.

Sub-Fields:

SS_DEVICE_ID1_NUM_PLINKS_PER_PROC Number of processors on the device.

SS_DEVICE_ID1_NUM_PROCESSORS Number of processors on the SSwitch.

SS_DEVICE_ID1_NUM_SLINKS Number of SLinks on the SSwitch.

XS1_SSWITCH_DEVICE_ID2_NUM

SSWITCH_DEVICE_ID2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_DEVICE_ID3_NUM

SSWITCH_DEVICE_ID3 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_NODE_CONFIG_NUM

SSWITCH_NODE_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode.

Sub-Fields:

SS_NODE_CONFIG_HEADERS 0 = 2-byte headers, 1 = 1-byte headers (reset as 0).

SS_NODE_CONFIG_DISABLE_PLL_CTL_REG 0 = PLL_CTL_REG has write access. 1 = PLL_CTL_REG can not be written to.

SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE 0 = SSCTL registers have write access. 1 = SSCTL registers can not be written to.

XS1_SSWITCH_NODE_ID_NUM

SSWITCH_NODE_ID system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains the node identifier.

Sub-Fields:

SS_NODE_ID_ID The unique ID of this node.

XS1_SSWITCH_PLL_CTL_NUM

SSWITCH_PLL_CTL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset.

Sub-Fields:

SS_PLL_CTL_INPUT_DIVISOR Oscilator input divider value range from 0 (0x00) to 63 (0x3F). R value.

SS_PLL_CTL_FEEDBACK_MUL Feedback multiplication ratio, range from 1 (0x0001) to 8191 (0x1FFF). F value.

SS_PLL_CTL_POST_DIVISOR Output divider value range from 0 to 7. OD value.

SS_PLL_CTL_DISABLE If set to 1, the PLL is disabled.

SS_TEST_MODE_BOOT_RAM If set to 1, set the boot mode to jump to RAM

SS_TEST_MODE_PLL_BYPASS If set to 1, set the PLL to be bypassed

SS_TEST_MODE_BOOT_JTAG If set to 1, set the boot mode to boot from JTAG

SS_PLL_CTL_NLOCK If set to 1, the chip will not wait for the PLL to re-lock. Only use this if a gradual change is made to the PLL

SS_PLL_CTL_NRESET If set to 1, the chip will not be reset

XS1_SSWITCH_CLK_DIVIDER_NUM

SSWITCH_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL clock and the switch clock.

Sub-Fields:

SS_CLK_DIVIDER_CLK_DIV SSwitch clock divider

XS1_SSWITCH_REF_CLK_DIVIDER_NUM

SSWITCH_REF_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL clock and the reference clock used by the node.

Sub-Fields:

SS_SSWITCH_REF_CLK_DIV Software reference clock divider

XS1_SSWITCH_JTAG_DEVICE_ID_NUM

SSWITCH_JTAG_DEVICE_ID system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

SS_JTAG_DEVICE_ID_CONST_VAL

SS_JTAG_DEVICE_ID_MANU_ID

SS_JTAG_DEVICE_ID_PART_NUM

SS_JTAG_DEVICE_ID_VERSION

XS1_SSWITCH_JTAG_USERCODE_NUM

SSWITCH_JTAG_USERCODE system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

SS_JTAG_USERCODE_MASKID metal fixable ID code

SS_JTAG_USERCODE_OTP JTAG USERCODE value programmed into OTP SR

XS1_SSWITCH_DDR_CLK_DIVIDER_NUM

SSWITCH_DDR_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL/APP PLL clock and the LPDDR clock. There is a divide by 2 permanently after the clock divider to create a matched mark space ratio. The LPDDR clock needs to be set to be twice the frequency required.

Sub-Fields:

SS_DDR_CLK_DIV LPDDR clock divider. When set to X the input clock is divided by 2(X+1).

SS_DDR_CLK_DIV_DISABLE LPDDR clock divider disable. When set to 0, the divider is enabled.

SS_DDR_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the LPDDR clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_DIMENSION_DIRECTION0_NUM

SSWITCH_DIMENSION_DIRECTION0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains eight directions, for packets with a mismatch in bits 7..0 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit.

Sub-Fields:

DIM0_DIR The direction for packets whose dimension is 0.

DIM1_DIR The direction for packets whose dimension is 1.

DIM2_DIR The direction for packets whose dimension is 2.

DIM3_DIR The direction for packets whose dimension is 3.

DIM4_DIR The direction for packets whose dimension is 4.

DIM5_DIR The direction for packets whose dimension is 5.

DIM6_DIR The direction for packets whose dimension is 6.

DIM7_DIR The direction for packets whose dimension is 7.

XS1_SSWITCH_DIMENSION_DIRECTION1_NUM

SSWITCH_DIMENSION_DIRECTION1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit.

Sub-Fields:

DIM8_DIR The direction for packets whose dimension is 8.

DIM9_DIR The direction for packets whose dimension is 9.

DIMA_DIR The direction for packets whose dimension is A.

DIMB_DIR The direction for packets whose dimension is B.

DIMC_DIR The direction for packets whose dimension is C.

DIMD_DIR The direction for packets whose dimension is D.

DIME_DIR The direction for packets whose dimension is E.

DIMF_DIR The direction for packets whose dimension is F.

XS1_SSWITCH_SS_APP_CLK_DIVIDER_NUM

SSWITCH_SS_APP_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

The clock divider and output of the secondary PLL can be set in this register

Sub-Fields:

SS_APP_CLK_DIV Application clock divider. When set to X, the output of the secondary PLL will be divided by 2(X+1) in order to form the output on the output pin

SS_APP_CLK_DIV_DISABLE Application clock divider disable. When set to 0, the divider is enabled, and pin X1D11 will be connected to the application clock rather than to port 1D.

SS_APP_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the application clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_SS_APP_PLL_CTL_NUM

SSWITCH_SS_APP_PLL_CTL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

A secondary on-chip PLL multiplies the input clock up to a higher frequency clock. See Section secondary-pll.

Sub-Fields:

SS_PLL_CTL_INPUT_DIVISOR Oscilator input divider value range from 0 (0x00) to 63 (0x3F). R value.

SS_PLL_CTL_FEEDBACK_MUL Feedback multiplication ratio, range from 1 (0x0001) to 8191 (0x1FFF). F value.

SS_PLL_CTL_POST_DIVISOR Output divider value range from 0 to 7. OD value.

SS_APP_PLL_ENABLE If set to 1, enable the secondary PLL

SS_APP_PLL_INPUT_FROM_SYS_PLL If set to 1, use the output of the core PLL as input, otherwise use the crystal oscillator as input.

SS_APP_PLL_BYPASS If set to 1, set the APP PLL to be bypassed

XS1_SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG_NUM

SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

if DEBUGN Configures the behavior of the DEBUG_N pin.else Reserved.

Sub-Fields:

GLOBAL_DEBUG_ENABLE_INDEBUG if DEBUGN Set 1 to enable inDebug bit to drive GlobalDebug.else Reserved.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ if DEBUGN Set 1 to enable GlobalDebug to generate debug request to XCore.else Reserved.

XS1_SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG_NUM

SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

if DEBUGN Configures the behavior of the DEBUG_N pin.else Reserved.

Sub-Fields:

GLOBAL_DEBUG_ENABLE_INDEBUG if DEBUGN Set 1 to enable inDebug bit to drive GlobalDebug.else Reserved.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ if DEBUGN Set 1 to enable GlobalDebug to generate debug request to XCore.else Reserved.

XS1_SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER_NUM

SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls an optional fractional N Divider on the secondary PLL. When enabled, the multiplier F for the secondary PLL will effectively become F+\frac{f+1}{p+1}, f must be less than p. This is achieved by running the PLL with a divider F for the first part of the fractional period, and then F+1 for the remainder of the period. The period is measured in input clocks divided by R+1.

Sub-Fields:

SS_FRAC_N_PERIOD_CYC_CNT The p value for the fractional divider. The period over which the fractional N divider oscillates between F and F+1 is p+1

SS_FRAC_N_F_HIGH_CYC_CNT The f value for the fractional divider. The number of clock cycles in the period that a divider F+1 is used is f+1.

SS_FRAC_N_ENABLE When set to 1, the secondary PLL will be a fractional N divided PLL

XS1_SSWITCH_SS_LPDDR_CONTROLLER_CONFIG_NUM

SSWITCH_SS_LPDDR_CONTROLLER_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls whether LPDDR Controller is enabled, and which core it is accessible to through the mux.

Sub-Fields:

SS_LPDDR_ENABLE When set to 1 this will allow the LPDDR controller to access the pads

SS_LPDDR_MUXTO_CORE1 Defines which xCORE has access to the LPDDR controller via the mux

XS1_SSWITCH_MIPI_CLK_DIVIDER_NUM

SSWITCH_MIPI_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the clock to the MIPI shim, the hardware block interfacing the MIPI PHY to the xCORE.

Sub-Fields:

SS_SSWITCH_MIPI_CLK_DIV MIPI shim clock divider. When set to X the input clock is divided by 2(X+1).

SS_SSWITCH_MIPI_CLK_DIV_DISABLE MIPI clock divider disable. When set to 0, the divider is enabled.

SS_MIPI_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the MIPI shim clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_MIPI_CFG_CLK_DIVIDER_NUM

SSWITCH_MIPI_CFG_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the clock to the MIPI PHY.

Sub-Fields:

SS_MIPI_CFG_CLK_DIV MIPI PHY clock divider. When set to X, the input clock will be divided by 2(X+1).

SS_MIPI_CFG_CLK_DIV_DISABLE MIPI PHY clock divider disable. When set to 0, the divider is enabled.

SS_MIPI_CFG_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the MIPI PHY clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_GLOBAL_DEBUG_SOURCE_NUM

SSWITCH_GLOBAL_DEBUG_SOURCE system switch register number.

Use read_sswitch_reg() to access.

Contains the source of the most recent debug event.

Sub-Fields:

GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG If set, XCore0 is the source of last GlobalDebug event.

GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG If set, XCore1 is the source of last GlobalDebug event.

GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG if DEBUGN If set, external pin, is the source of last GlobalDebug event.else Reserved.

XS1_SSWITCH_USB_XCFGI_REG0_NUM

SSWITCH_USB_XCFGI_REG0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFGI_REG1_NUM

SSWITCH_USB_XCFGI_REG1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFGI_REG2_NUM

SSWITCH_USB_XCFGI_REG2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_COARSE_TUNE_NUM

SSWITCH_USB_XCFG_COARSE_TUNE system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_FINE_TUNE_NUM

SSWITCH_USB_XCFG_FINE_TUNE system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MAX_NUM

SSWITCH_USB_XCFG_LOCK_RANGE_MAX system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MIN_NUM

SSWITCH_USB_XCFG_LOCK_RANGE_MIN system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_CFG0_NUM

SSWITCH_USB_PHY_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register configures the UTMI signals to the USB PHY. See the UTMI specification for more details. The oscillator speed should be set to match the crystal on XIN/XOUT.

Sub-Fields:

USB_PHY_CFG0_UTMI_XCVRSELECT Value of the UTMI XCVRSelect signals to the USB Phy

USB_PHY_CFG0_UTMI_TERMSELECT Value of the UTMI Terminal Select signal to the USB Phy

USB_PHY_CFG0_UTMI_OPMODE Value of the UTMI OpMode signals to the USB Phy

USB_PHY_CFG0_UTMI_SUSPENDM Value of the UTMI SuspendM signal to the USB Phy

USB_PHY_CFG0_DPPULLDOWN Set to 1 to enable the DP Pulldown

USB_PHY_CFG0_DMPULLDOWN Set to 1 to enable the DM Pulldown

USB_PHY_CFG0_TXBITSTUFF_EN Set to 1 to enable USB Tx BitStuffing

USB_PHY_CFG0_PLL_EN Set to 1 to enable the USB PLL

USB_PHY_CFG0_LPM_ALIVE Set to 1 to enable USB LPM

USB_PHY_CFG0_IDPAD_EN Set to 1 to enable the ID PAD

USB_PHY_CFG0_XTLSEL Oscillator freqeuncy. Set to: 0 (10MHz), 1 (12MHz), 2 (25MHz), 3~(30MHz), 4 (19.2MHz), 5 (24MHz), 6 (27MHz), or 7 (40MHz).

XS1_SSWITCH_USB_PHY_CFG1_NUM

SSWITCH_USB_PHY_CFG1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_CFG2_NUM

SSWITCH_USB_PHY_CFG2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

USB_PHY_CFG2_PONRST USB PHY reset, set to 1 to take the PHY out of reset

USB_PHY_CFG2_UTMI_RESET UTMI reset, set to 0 to take UTMI out of reset

XS1_SSWITCH_USB_PHY_CFG3_NUM

SSWITCH_USB_PHY_CFG3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

USB_PHY_CFG3_VCONTROL USB VCONTROL

USB_PHY_CFG3_EXTERNAL_TEST_MODE USB EXTERNAL TEST MODE

USB_PHY_CFG3_LS_EN USB LS Enable

USB_PHY_CFG3_UTMI_VCONTROLLOADM USB UTMI VCONTROLLOADM

USB_PHY_CFG3_HS_BIST_MODE USB HS BIST Mode

XS1_SSWITCH_USB_SHIM_CFG_NUM

SSWITCH_USB_SHIM_CFG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains the hardware interfacing the USB PHY and the xCORE. It governs how the rxActive, rxValid, and line-state signals are mapped onto two one-bit ports.

Sub-Fields:

USB_SHIM_CFG_AND_RXV_RXA When enabled RxValid output to xCore is AND’d with RxActive

USB_SHIM_CFG_FLAG_MODE USB flag mode selection: 1 selects linestate; 0 selects RxActive and RxValid

XS1_SSWITCH_USB_PHY_XCFGO_REG0_NUM

SSWITCH_USB_PHY_XCFGO_REG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_STATUS_NUM

SSWITCH_USB_PHY_STATUS system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

USB_PHY_STATUS_UTMI_LINESTATE The UTMI line state; 0: SE0, 1: J, 2: K, 3: SE1

USB_PHY_STATUS_HOSTDISCONNECT Set to 1 if no peripheral is connected

USB_PHY_STATUS_IDPAD 1 if resistance of IDPAD to ground is > 100 kOhm (mini B plug)

USB_PHY_STATUS_BIST_OK 1 if BIST succeeded

USB_PHY_STATUS_DEBUG_OUT Debug output signals

XS1_SSWITCH_USB_SHIM_STATUS_NUM

SSWITCH_USB_SHIM_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register does not do anything

XS1_SSWITCH_USB_STATUS_CLR_NUM

SSWITCH_USB_STATUS_CLR system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register does not do anything

XS1_SSWITCH_WATCHDOG_CFG_NUM

SSWITCH_WATCHDOG_CFG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to control the watchdog. By default the watchdog is neither counting, nor triggering. When used as a watchdog it should be set to both count and trigger a reset on reaching 0. It can be set to just count for debugging purposes

Sub-Fields:

WATCHDOG_COUNT_ENABLE Set this bit to 1 to enable the watchdog counter.

WATCHDOG_TRIGGER_ENABLE Set this bit to 1 to enable the watchdog to actually reset the chip.

XS1_SSWITCH_WATCHDOG_PRESCALER_NUM

SSWITCH_WATCHDOG_PRESCALER system switch register number.

Use read_sswitch_reg() to access.

Register to read out the current divider counter. Can be used to implement a timer that is independent of the PLL.

Sub-Fields:

WATCHDOG_PRESCALER_VALUE This is the current count of the prescaler. One is added one every input clock edge on the oscillator (XIN). When it reaches the prescaler wrap value (see below), it resets to zero and one is subtracted from the watchdog count (see below).

XS1_SSWITCH_WATCHDOG_PRESCALER_WRAP_NUM

SSWITCH_WATCHDOG_PRESCALER_WRAP system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to set the watchdog pre-scale divider value.

Sub-Fields:

WATCHDOG_PRESCALER_WRAP_VALUE This is the prescaler divider. The input clock on XIN is divided by this value plus one, before being used to adjust the watchdog count (see below).

XS1_SSWITCH_WATCHDOG_COUNT_NUM

SSWITCH_WATCHDOG_COUNT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to set the value at which the watchdog timer should time out. This register must be overwritten regularly to stop the watchdog from resetting the chip.

Sub-Fields:

WATCHDOG_COUNT_VALUE This is the watchdog counter. It counts down every PRESCALER_WRAP_VALUE input clock edges. When it reaches zero the chip is reset. The maximum time for the watchdog is 2^{12} \times 2^{16} = 2^{28} = 268,435,456 input clocks.

XS1_SSWITCH_WATCHDOG_STATUS_NUM

SSWITCH_WATCHDOG_STATUS system switch register number.

Use read_sswitch_reg() to access.

Register that can be used to inspect whether the watchdog has triggered.

Sub-Fields:

WATCHDOG_HAS_TRIGGERED When 1, the watchdog has been triggered. This bit is only reset to 0 on a power-on-reset.

XS1_SSWITCH_MIPI_STATUS0_NUM

SSWITCH_MIPI_STATUS0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_STATUS0_OSC_CLK_ACT Test mode osc clock act

MIPI_STATUS0_OSC_CLK_READY Test mode osc clock ready

MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G Test mode bit clk greater than 2400G

MIPI_STATUS0_DATA_CORRECT_LAN0 Test mode data correct lan0

MIPI_STATUS0_DATA_CORRECT_LAN1 Test mode data correct lan1

MIPI_STATUS0_DATA_CORRECT_LAN2 Test mode data correct lan2

MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C Test mode da cdphy r100 control0 2d1c

MIPI_STATUS0_STOPSTATE_CLK Clock lane is in the stop state

MIPI_STATUS0_STOPSTATE_LAN0 Lane 0 is in the stop state

MIPI_STATUS0_STOPSTATE_LAN1 Lane 1 is in the stop state

XS1_SSWITCH_MIPI_SHIM_STATUS_NUM

SSWITCH_MIPI_SHIM_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register provides status for the MIPI demuxing logic

Sub-Fields:

MIPI_SHIM_STATUS_REG Set to 1 if an overflow has been detected in the DEMUXER. This is not recoverable, and indicates that the MIPI_CLK is too slow for the rate at which data is received.

XS1_SSWITCH_MIPI_DPHY_CFG0_NUM

SSWITCH_MIPI_DPHY_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls the reset signals to the MIPI D-PHY

Sub-Fields:

MIPI_DPHY_CFG0_HW_RSTN Reset, set to 1 to take the MIPI PHY out of reset

MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON Set to 1

XS1_SSWITCH_MIPI_DPHY_CFG1_NUM

SSWITCH_MIPI_DPHY_CFG1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG1_MP_TEST_EN MIPI dphy config1 mp test mode enable

MIPI_DPHY_CFG1_MP_TEST_MODE_SEL MIPI dphy config1 mp test mode select

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN MIPI dphy config1 cdphy r100 control 0 2d1c efuse enable

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN MIPI dphy config1 cdphy r100 control 0 2d1c efuse in

XS1_SSWITCH_MIPI_DPHY_CFG2_NUM

SSWITCH_MIPI_DPHY_CFG2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG2_PLL_CLK_SEL MIPI dphy config2 pll clock select

XS1_SSWITCH_MIPI_DPHY_CFG3_NUM

SSWITCH_MIPI_DPHY_CFG3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the settings for the three lanes, in particular, where the wires appear on the physical interfaces and which ones are enabled.

Sub-Fields:

MIPI_DPHY_CFG3_LANE_SWAP_CLK The DP/DN pair over which to input the clock

MIPI_DPHY_CFG3_LANE_SWAP_LAN0 The DP/DN pair over which to input lane 0

MIPI_DPHY_CFG3_LANE_SWAP_LAN1 The DP/DN pair over which to input lane 1 (if two lanes are needed)

MIPI_DPHY_CFG3_DPDN_SWAP_CLK Set to 1 to swap the DN/DP pair on the clock lane

MIPI_DPHY_CFG3_DPDN_SWAP_LAN0 Set to 1 to swap the DN/DP pair on the lane 0

MIPI_DPHY_CFG3_DPDN_SWAP_LAN1 Set to 1 to swap the DN/DP pair on the lane 1

MIPI_DPHY_CFG3_ENABLE_CLK Set to 0 to disable the clock lane receiver

MIPI_DPHY_CFG3_ENABLE_LAN0 Set to 0 to disable lane 0 receiver

MIPI_DPHY_CFG3_ENABLE_LAN1 Set to 0 to disable lane 1 receiver

XS1_SSWITCH_MIPI_DPHY_CFG4_NUM

SSWITCH_MIPI_DPHY_CFG4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK MIPI dphy Tclk-settle for clock

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0 MIPI dphy Tclk-settle in lane 0

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1 MIPI dphy Tclk-settle in lane 1

XS1_SSWITCH_MIPI_DPHY_CFG5_NUM

SSWITCH_MIPI_DPHY_CFG5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG5_DEBUG_MODE_SEL MIPI dphy debug mode select

XS1_SSWITCH_MIPI_SHIM_CFG0_NUM

SSWITCH_MIPI_SHIM_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register is used to configure the MIPI shim, the hardware block interfacing the MIPI D-PHY to the xCORE. By default the MIPI shim just passes the data from the MIPI D-PHY straight through to the receiver. This register enables you to demultiplex 10-bit, 12-bit, 14-bit and 565-data into 16-bit and 8-bit values. When the demultiplexer is enabled, you must specify the CSI-2 packet type that demultiplexing should apply to. Optionally, you can choose to align add an extra fourth byte for RGB formats, or you can choose to bias the data so that all the data values are signed.

Sub-Fields:

MIPI_SHIM_CFG0_PIXEL_DEMUX_EN Set to 1 to enable the MIPI shim to demultiplex data according to the demux mode and stuff fields. Demuxing is only applied to packets that have the correct datatype.

MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE This field needs to be set to the CSI-2 packet type that needs to be demuxed. Only packets with a matching type are demultiplexed.

MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE Specifies how the demultiplexer operates. The modes supported are 10to16, 12to16, 14to16, rgb565to888, rgb888to888.

MIPI_SHIM_DEMUX_STUFF Set to 1 to add an extra data byte after every RGB565 or RGB888 pixel. This will align pixels to a 32-bit word.

MIPI_SHIM_BIAS Set to 1 to offset the output pixels with -0x80 (for 8-bit outputs) or -0x8000 (for 16-bit outputs). This can be used to make unsigned data signed around zero.

MIPI_SHIM_CFG0_SEL_DEBUG_OUT MIPI shim config0 sel debug out

MIPI_SHIM_CFG0_SEL_DEBUG MIPI shim config0 sel debug

XS1_SSWITCH_LPDDR_IID_ENABLE_NUM

SSWITCH_LPDDR_IID_ENABLE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register is used to enable one or more threads to route its requests through specified queues. There are three queues (one read-only queue, RO, and two read-write queues, RW0/RW1) and for each thread instruction accesses and data accesses can be routed through specified queues.

Sub-Fields:

LPDDR_IID_ENABLE Two 8-bit masks, one bit per thread. Top eight bits enable instructions to be routed through a specified queue, bottom eight bits enable data to be routed through a specified queue.

XS1_SSWITCH_LPDDR_IID_0_7_NUM

SSWITCH_LPDDR_IID_0_7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

For each thread, this register specifies which queue a data access should be routed through.

Sub-Fields:

LPDDR_IID_0_7 Four bits per thread. Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_SSWITCH_LPDDR_IID_8_15_NUM

SSWITCH_LPDDR_IID_8_15 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

For each thread, this register specifies which queue an instruction access should be routed through.

Sub-Fields:

LPDDR_IID_8_15 Four bits per thread. Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_SSWITCH_LPDDR_QUEUE_CONT_NUM

SSWITCH_LPDDR_QUEUE_CONT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_QUEUE_CONT Slow sys clock. Set this bit if the tile clock is less than the LPDDR clock.

XS1_SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY_NUM

SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_RO_PRI Priority for RO queue. Zero is lowest priority.

XS1_SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY_NUM

SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_RW0_PRI Priority for RW queue 0. Zero is lowest priority.

LPDDR_RW1_PRI Priority for RW queue 1. Zero is lowest priority.

XS1_SSWITCH_LPDDR_ARBITRATION_TIMEOUT_NUM

SSWITCH_LPDDR_ARBITRATION_TIMEOUT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Setting this to a non-zero value guarantees that each queue is served at least every N transactions and prevents starvation.

Sub-Fields:

LPDDR_TOUT Maximum number of transactions until a queue is served. Set to 0 to disable a timeout

XS1_SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND_NUM

SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_MTG_CMD MTG Commands status for CSR Read

XS1_SSWITCH_LPDDR_DLL_CONTROL_NUM

SSWITCH_LPDDR_DLL_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_CONTROL DLL Control

XS1_SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS_NUM

SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_MEASUREMENT_STATUS Measurement status of the DLL

XS1_SSWITCH_LPDDR_DLL_MANUAL_CONTROL_NUM

SSWITCH_LPDDR_DLL_MANUAL_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_MANUAL_CONTROL DLL Manual Control

XS1_SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA_NUM

SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_PHY_CALIBRATION_DATA DLL Calibration Data

XS1_SSWITCH_LPDDR_PHY_CONTROL_NUM

SSWITCH_LPDDR_PHY_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_PHY_CONTROL PHY Control

XS1_SSWITCH_LPDDR_LMR_OPCODE_NUM

SSWITCH_LPDDR_LMR_OPCODE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_LMR_OPCODE LMR opcode

XS1_SSWITCH_LPDDR_EMR_OPCODE_NUM

SSWITCH_LPDDR_EMR_OPCODE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_EMR_OPCODE EMR opcode

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0_NUM

SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register used to set the tREFI, tRAS, tXSR, and tWR timings, all measured in terms of LPDDR clocks

Sub-Fields:

LPDDR_PE_TREFI_CNT LPDDR tREFI clock count

LPDDR_PE_TRAS_CNT LPDDR tRAS clock count

LPDDR_PE_TXSR_CNT LPDDR tXSR clock count

LPDDR_PE_TWR_CNT LPDDR tWR clock count

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1_NUM

SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register used to set the tRRC, tRCD, tRP, tRFC, and tRRD timings, all measured in terms of LPDDR clocks. This register is also used to configure the use of 256 bit memories.

Sub-Fields:

LPDDR_PE_TRC_CNT LPDDR tRC clock count

LPDDR_PE_TRCD_CNT LPDDR tRCD clock count

LPDDR_PE_TRP_CNT LPDDR tRP clock count

LPDDR_PE_TRFC_CNT LPDDR tRFC clock count

LPDDR_PE_TRRD_CNT LPDDR tRRD clock count

LPDDR_PE_EN_256M_DEV_SIZE Enable 256 Mbit device

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS_NUM

SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_PADCTRL_CLK_NUM

SSWITCH_PADCTRL_CLK system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CLK and CLK_N pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CKE_NUM

SSWITCH_PADCTRL_CKE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CKE pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CS_N_NUM

SSWITCH_PADCTRL_CS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_WE_N_NUM

SSWITCH_PADCTRL_WE_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the WE_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CAS_N_NUM

SSWITCH_PADCTRL_CAS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CAS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_RAS_N_NUM

SSWITCH_PADCTRL_RAS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the RAS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_ADDR_NUM

SSWITCH_PADCTRL_ADDR system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the A0-A13 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_BA_NUM

SSWITCH_PADCTRL_BA system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the BA0 and BA1 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DQ_NUM

SSWITCH_PADCTRL_DQ system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the DQ0-DQ15 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DQS_NUM

SSWITCH_PADCTRL_DQS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the UDQS and LDQS pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DM_NUM

SSWITCH_PADCTRL_DM system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the UDM and LDM pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

Register bitfields

These definitions allow packing and unpacking subfields from the other registers.

group xs3a Register Bitfields

VSR_HEADROOM

Max headroom seen on VST

XS1_VSR_HEADROOM_SHIFT

XS1_VSR_HEADROOM_SIZE

XS1_VSR_HEADROOM_MASK

XS1_VSR_HEADROOM(x)

Extract the VSR_HEADROOM bitfield from a packed word x and return it.

XS1_VSR_HEADROOM_SET(x, v)

Pack the value (v) of the VSR_HEADROOM bitfield into a packed word x and return the packed field.

VSR_SHIFT

Shift none/left/right on VLBUT

XS1_VSR_SHIFT_SHIFT

XS1_VSR_SHIFT_SIZE

XS1_VSR_SHIFT_MASK

XS1_VSR_SHIFT(x)

Extract the VSR_SHIFT bitfield from a packed word x and return it.

XS1_VSR_SHIFT_SET(x, v)

Pack the value (v) of the VSR_SHIFT bitfield into a packed word x and return the packed field.

VSR_TYPE

Data type of VC, VD, RC

XS1_VSR_TYPE_SHIFT

XS1_VSR_TYPE_SIZE

XS1_VSR_TYPE_MASK

XS1_VSR_TYPE(x)

Extract the VSR_TYPE bitfield from a packed word x and return it.

XS1_VSR_TYPE_SET(x, v)

Pack the value (v) of the VSR_TYPE bitfield into a packed word x and return the packed field.

VSR_LENGTH

Log2(convolution length)

XS1_VSR_LENGTH_SHIFT

XS1_VSR_LENGTH_SIZE

XS1_VSR_LENGTH_MASK

XS1_VSR_LENGTH(x)

Extract the VSR_LENGTH bitfield from a packed word x and return it.

XS1_VSR_LENGTH_SET(x, v)

Pack the value (v) of the VSR_LENGTH bitfield into a packed word x and return the packed field.

SR_EEBLE

1 when events are enabled for the thread.

XS1_SR_EEBLE_SHIFT

XS1_SR_EEBLE_SIZE

XS1_SR_EEBLE_MASK

XS1_SR_EEBLE(x)

Extract the SR_EEBLE bitfield from a packed word x and return it.

XS1_SR_EEBLE_SET(x, v)

Pack the value (v) of the SR_EEBLE bitfield into a packed word x and return the packed field.

SR_IEBLE

1 when interrupts are enabled for the thread.

XS1_SR_IEBLE_SHIFT

XS1_SR_IEBLE_SIZE

XS1_SR_IEBLE_MASK

XS1_SR_IEBLE(x)

Extract the SR_IEBLE bitfield from a packed word x and return it.

XS1_SR_IEBLE_SET(x, v)

Pack the value (v) of the SR_IEBLE bitfield into a packed word x and return the packed field.

SR_INENB

1 when in an event enabling sequence.

XS1_SR_INENB_SHIFT

XS1_SR_INENB_SIZE

XS1_SR_INENB_MASK

XS1_SR_INENB(x)

Extract the SR_INENB bitfield from a packed word x and return it.

XS1_SR_INENB_SET(x, v)

Pack the value (v) of the SR_INENB bitfield into a packed word x and return the packed field.

SR_ININT

1 when in an interrupt handler.

XS1_SR_ININT_SHIFT

XS1_SR_ININT_SIZE

XS1_SR_ININT_MASK

XS1_SR_ININT(x)

Extract the SR_ININT bitfield from a packed word x and return it.

XS1_SR_ININT_SET(x, v)

Pack the value (v) of the SR_ININT bitfield into a packed word x and return the packed field.

SR_INK

1 when in kernel mode.

XS1_SR_INK_SHIFT

XS1_SR_INK_SIZE

XS1_SR_INK_MASK

XS1_SR_INK(x)

Extract the SR_INK bitfield from a packed word x and return it.

XS1_SR_INK_SET(x, v)

Pack the value (v) of the SR_INK bitfield into a packed word x and return the packed field.

SR_SINK

Copy of the SSR INK bit.

XS1_SR_SINK_SHIFT

XS1_SR_SINK_SIZE

XS1_SR_SINK_MASK

XS1_SR_SINK(x)

Extract the SR_SINK bitfield from a packed word x and return it.

XS1_SR_SINK_SET(x, v)

Pack the value (v) of the SR_SINK bitfield into a packed word x and return the packed field.

SR_WAITING

1 when the thread is paused waiting for events, a lock or another resource.

XS1_SR_WAITING_SHIFT

XS1_SR_WAITING_SIZE

XS1_SR_WAITING_MASK

XS1_SR_WAITING(x)

Extract the SR_WAITING bitfield from a packed word x and return it.

XS1_SR_WAITING_SET(x, v)

Pack the value (v) of the SR_WAITING bitfield into a packed word x and return the packed field.

SR_FAST

1 when the thread is in fast mode and will continually issue.

XS1_SR_FAST_SHIFT

XS1_SR_FAST_SIZE

XS1_SR_FAST_MASK

XS1_SR_FAST(x)

Extract the SR_FAST bitfield from a packed word x and return it.

XS1_SR_FAST_SET(x, v)

Pack the value (v) of the SR_FAST bitfield into a packed word x and return the packed field.

SR_DI

1 when in dual issue mode.

XS1_SR_DI_SHIFT

XS1_SR_DI_SIZE

XS1_SR_DI_MASK

XS1_SR_DI(x)

Extract the SR_DI bitfield from a packed word x and return it.

XS1_SR_DI_SET(x, v)

Pack the value (v) of the SR_DI bitfield into a packed word x and return the packed field.

SR_KEDI

1 if, on kernel entry, the thread will switch to dual issue.

XS1_SR_KEDI_SHIFT

XS1_SR_KEDI_SIZE

XS1_SR_KEDI_MASK

XS1_SR_KEDI(x)

Extract the SR_KEDI bitfield from a packed word x and return it.

XS1_SR_KEDI_SET(x, v)

Pack the value (v) of the SR_KEDI bitfield into a packed word x and return the packed field.

SR_QUEUE

1 if in high priority mode

XS1_SR_QUEUE_SHIFT

XS1_SR_QUEUE_SIZE

XS1_SR_QUEUE_MASK

XS1_SR_QUEUE(x)

Extract the SR_QUEUE bitfield from a packed word x and return it.

XS1_SR_QUEUE_SET(x, v)

Pack the value (v) of the SR_QUEUE bitfield into a packed word x and return the packed field.

ID_ID

Number of the thread.

XS1_ID_ID_SHIFT

XS1_ID_ID_SIZE

XS1_ID_ID_MASK

XS1_ID_ID(x)

Extract the ID_ID bitfield from a packed word x and return it.

XS1_ID_ID_SET(x, v)

Pack the value (v) of the ID_ID bitfield into a packed word x and return the packed field.

EXCEPTION_TYPE

The exception type.

XS1_EXCEPTION_TYPE_SHIFT

XS1_EXCEPTION_TYPE_SIZE

XS1_EXCEPTION_TYPE_MASK

XS1_EXCEPTION_TYPE(x)

Extract the EXCEPTION_TYPE bitfield from a packed word x and return it.

XS1_EXCEPTION_TYPE_SET(x, v)

Pack the value (v) of the EXCEPTION_TYPE bitfield into a packed word x and return the packed field.

DBG_T_NUM_NUM

Thread number to be read

XS1_DBG_T_NUM_NUM_SHIFT

XS1_DBG_T_NUM_NUM_SIZE

XS1_DBG_T_NUM_NUM_MASK

XS1_DBG_T_NUM_NUM(x)

Extract the DBG_T_NUM_NUM bitfield from a packed word x and return it.

XS1_DBG_T_NUM_NUM_SET(x, v)

Pack the value (v) of the DBG_T_NUM_NUM bitfield into a packed word x and return the packed field.

DBG_T_REG_REG

Register number to be read

XS1_DBG_T_REG_REG_SHIFT

XS1_DBG_T_REG_REG_SIZE

XS1_DBG_T_REG_REG_MASK

XS1_DBG_T_REG_REG(x)

Extract the DBG_T_REG_REG bitfield from a packed word x and return it.

XS1_DBG_T_REG_REG_SET(x, v)

Pack the value (v) of the DBG_T_REG_REG bitfield into a packed word x and return the packed field.

BRK_ENABLE

When 1 the breakpoint is enabled.

XS1_BRK_ENABLE_SHIFT

XS1_BRK_ENABLE_SIZE

XS1_BRK_ENABLE_MASK

XS1_BRK_ENABLE(x)

Extract the BRK_ENABLE bitfield from a packed word x and return it.

XS1_BRK_ENABLE_SET(x, v)

Pack the value (v) of the BRK_ENABLE bitfield into a packed word x and return the packed field.

ALL_BITS

Value.

XS1_ALL_BITS_SHIFT

XS1_ALL_BITS_SIZE

XS1_ALL_BITS_MASK

XS1_ALL_BITS(x)

Extract the ALL_BITS bitfield from a packed word x and return it.

XS1_ALL_BITS_SET(x, v)

Pack the value (v) of the ALL_BITS bitfield into a packed word x and return the packed field.

KEP_ADDRESS_BITS

KEP Address bits

XS1_KEP_ADDRESS_BITS_SHIFT

XS1_KEP_ADDRESS_BITS_SIZE

XS1_KEP_ADDRESS_BITS_MASK

XS1_KEP_ADDRESS_BITS(x)

Extract the KEP_ADDRESS_BITS bitfield from a packed word x and return it.

XS1_KEP_ADDRESS_BITS_SET(x, v)

Pack the value (v) of the KEP_ADDRESS_BITS bitfield into a packed word x and return the packed field.

WORD_ADDRESS_BITS

Most significant 16 bits of all addresses.

XS1_WORD_ADDRESS_BITS_SHIFT

XS1_WORD_ADDRESS_BITS_SIZE

XS1_WORD_ADDRESS_BITS_MASK

XS1_WORD_ADDRESS_BITS(x)

Extract the WORD_ADDRESS_BITS bitfield from a packed word x and return it.

XS1_WORD_ADDRESS_BITS_SET(x, v)

Pack the value (v) of the WORD_ADDRESS_BITS bitfield into a packed word x and return the packed field.

VECTOR_BASE

The event and interrupt vectors.

XS1_VECTOR_BASE_SHIFT

XS1_VECTOR_BASE_SIZE

XS1_VECTOR_BASE_MASK

XS1_VECTOR_BASE(x)

Extract the VECTOR_BASE bitfield from a packed word x and return it.

XS1_VECTOR_BASE_SET(x, v)

Pack the value (v) of the VECTOR_BASE bitfield into a packed word x and return the packed field.

IBRK_CONDITION

When 0 break when PC == IBREAK_ADDR.

When 1 = break when PC != IBREAK_ADDR.

XS1_IBRK_CONDITION_SHIFT

XS1_IBRK_CONDITION_SIZE

XS1_IBRK_CONDITION_MASK

XS1_IBRK_CONDITION(x)

Extract the IBRK_CONDITION bitfield from a packed word x and return it.

XS1_IBRK_CONDITION_SET(x, v)

Pack the value (v) of the IBRK_CONDITION bitfield into a packed word x and return the packed field.

DBRK_CONDITION

Determines the break condition: 0 = A AND B, 1 = A OR B.

XS1_DBRK_CONDITION_SHIFT

XS1_DBRK_CONDITION_SIZE

XS1_DBRK_CONDITION_MASK

XS1_DBRK_CONDITION(x)

Extract the DBRK_CONDITION bitfield from a packed word x and return it.

XS1_DBRK_CONDITION_SET(x, v)

Pack the value (v) of the DBRK_CONDITION bitfield into a packed word x and return the packed field.

RBRK_CONDITION

When 0 break when condition A is met.

When 1 = break when condition B is met.

XS1_RBRK_CONDITION_SHIFT

XS1_RBRK_CONDITION_SIZE

XS1_RBRK_CONDITION_MASK

XS1_RBRK_CONDITION(x)

Extract the RBRK_CONDITION bitfield from a packed word x and return it.

XS1_RBRK_CONDITION_SET(x, v)

Pack the value (v) of the RBRK_CONDITION bitfield into a packed word x and return the packed field.

BRK_LOAD

When 1 the breakpoints will be be triggered on loads.

XS1_BRK_LOAD_SHIFT

XS1_BRK_LOAD_SIZE

XS1_BRK_LOAD_MASK

XS1_BRK_LOAD(x)

Extract the BRK_LOAD bitfield from a packed word x and return it.

XS1_BRK_LOAD_SET(x, v)

Pack the value (v) of the BRK_LOAD bitfield into a packed word x and return the packed field.

BRK_THREADS

A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_BRK_THREADS_SHIFT

XS1_BRK_THREADS_SIZE

XS1_BRK_THREADS_MASK

XS1_BRK_THREADS(x)

Extract the BRK_THREADS bitfield from a packed word x and return it.

XS1_BRK_THREADS_SET(x, v)

Pack the value (v) of the BRK_THREADS bitfield into a packed word x and return the packed field.

DBG_TYPE_CAUSE

Indicates the cause of the debug interrupt

1: Host initiated a debug interrupt through JTAG

2: Program executed a DCALL instruction

3: Instruction breakpoint

4: Data watch point

5: Resource watch point

XS1_DBG_TYPE_CAUSE_SHIFT

XS1_DBG_TYPE_CAUSE_SIZE

XS1_DBG_TYPE_CAUSE_MASK

XS1_DBG_TYPE_CAUSE(x)

Extract the DBG_TYPE_CAUSE bitfield from a packed word x and return it.

XS1_DBG_TYPE_CAUSE_SET(x, v)

Pack the value (v) of the DBG_TYPE_CAUSE bitfield into a packed word x and return the packed field.

DBG_TYPE_T_NUM

Number of thread which caused the debug interrupt (always 0 in the case of =HOST=).

XS1_DBG_TYPE_T_NUM_SHIFT

XS1_DBG_TYPE_T_NUM_SIZE

XS1_DBG_TYPE_T_NUM_MASK

XS1_DBG_TYPE_T_NUM(x)

Extract the DBG_TYPE_T_NUM bitfield from a packed word x and return it.

XS1_DBG_TYPE_T_NUM_SET(x, v)

Pack the value (v) of the DBG_TYPE_T_NUM bitfield into a packed word x and return the packed field.

DBG_TYPE_HW_NUM

Number of the hardware breakpoint/watchpoint which caused the interrupt (always 0 for =HOST= and =DCALL=).

If multiple breakpoints/watchpoints trigger at once, the lowest number is taken.

XS1_DBG_TYPE_HW_NUM_SHIFT

XS1_DBG_TYPE_HW_NUM_SIZE

XS1_DBG_TYPE_HW_NUM_MASK

XS1_DBG_TYPE_HW_NUM(x)

Extract the DBG_TYPE_HW_NUM bitfield from a packed word x and return it.

XS1_DBG_TYPE_HW_NUM_SET(x, v)

Pack the value (v) of the DBG_TYPE_HW_NUM bitfield into a packed word x and return the packed field.

DBG_RUN_CTRL_STOP

1-hot vector defining which threads are stopped when not in debug mode.

Every bit which is set prevents the respective thread from running.

XS1_DBG_RUN_CTRL_STOP_SHIFT

XS1_DBG_RUN_CTRL_STOP_SIZE

XS1_DBG_RUN_CTRL_STOP_MASK

XS1_DBG_RUN_CTRL_STOP(x)

Extract the DBG_RUN_CTRL_STOP bitfield from a packed word x and return it.

XS1_DBG_RUN_CTRL_STOP_SET(x, v)

Pack the value (v) of the DBG_RUN_CTRL_STOP bitfield into a packed word x and return the packed field.

XCORE_CTRL0_EXTMEM_ENABLE

Enable External memory interface

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SHIFT

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SIZE

XS1_XCORE_CTRL0_EXTMEM_ENABLE_MASK

XS1_XCORE_CTRL0_EXTMEM_ENABLE(x)

Extract the XCORE_CTRL0_EXTMEM_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_EXTMEM_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_USB_ENABLE

Enable the USB hardware support module

XS1_XCORE_CTRL0_USB_ENABLE_SHIFT

XS1_XCORE_CTRL0_USB_ENABLE_SIZE

XS1_XCORE_CTRL0_USB_ENABLE_MASK

XS1_XCORE_CTRL0_USB_ENABLE(x)

Extract the XCORE_CTRL0_USB_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_USB_ENABLE_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_USB_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_CLK_DIVIDER_EN

Enable the clock divider.

This divides the output of the PLL to facilitate one of the low power modes.

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK

XS1_XCORE_CTRL0_CLK_DIVIDER_EN(x)

Extract the XCORE_CTRL0_CLK_DIVIDER_EN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_CLK_DIVIDER_EN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_CLK_DIVIDER_DYN

Select the dynamic mode (1) for the clock divider when the clock divider is enabled.

In dynamic mode the clock divider is only activated when all active threads are paused. In static mode the clock divider is always enabled.

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN(x)

Extract the XCORE_CTRL0_CLK_DIVIDER_DYN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_CLK_DIVIDER_DYN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_MIPI_ENABLE

Enable MIPI interface periph ports

XS1_XCORE_CTRL0_MIPI_ENABLE_SHIFT

XS1_XCORE_CTRL0_MIPI_ENABLE_SIZE

XS1_XCORE_CTRL0_MIPI_ENABLE_MASK

XS1_XCORE_CTRL0_MIPI_ENABLE(x)

Extract the XCORE_CTRL0_MIPI_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_MIPI_ENABLE_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_MIPI_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_MEMSLEEP_ENABLE

Enable memory auto-sleep feature

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SHIFT

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SIZE

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_MASK

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE(x)

Extract the XCORE_CTRL0_MEMSLEEP_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_MEMSLEEP_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_RAMSHUTDOWN

Disable RAMs to save power (contents will be lost)

XS1_XCORE_CTRL0_RAMSHUTDOWN_SHIFT

XS1_XCORE_CTRL0_RAMSHUTDOWN_SIZE

XS1_XCORE_CTRL0_RAMSHUTDOWN_MASK

XS1_XCORE_CTRL0_RAMSHUTDOWN(x)

Extract the XCORE_CTRL0_RAMSHUTDOWN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_RAMSHUTDOWN_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_RAMSHUTDOWN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_EXTMEM_DEVICE_SIZE

Specify size of a connected LPDDR device (options are: 128,256,512Mbits, 1Gbit),

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SHIFT

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SIZE

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_MASK

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE(x)

Extract the XCORE_CTRL0_EXTMEM_DEVICE_SIZE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SET(x, v)

Pack the value (v) of the XCORE_CTRL0_EXTMEM_DEVICE_SIZE bitfield into a packed word x and return the packed field.

BOOT_CONFIG_PLL_MODE_PINS

The boot PLL mode pin value.

XS1_BOOT_CONFIG_PLL_MODE_PINS_SHIFT

XS1_BOOT_CONFIG_PLL_MODE_PINS_SIZE

XS1_BOOT_CONFIG_PLL_MODE_PINS_MASK

XS1_BOOT_CONFIG_PLL_MODE_PINS(x)

Extract the BOOT_CONFIG_PLL_MODE_PINS bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_PLL_MODE_PINS_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_PLL_MODE_PINS bitfield into a packed word x and return the packed field.

BOOT_CONFIG_BOOT_FROM_JTAG

Boot ROM boots from JTAG

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SHIFT

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SIZE

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_MASK

XS1_BOOT_CONFIG_BOOT_FROM_JTAG(x)

Extract the BOOT_CONFIG_BOOT_FROM_JTAG bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_BOOT_FROM_JTAG bitfield into a packed word x and return the packed field.

BOOT_CONFIG_BOOT_FROM_RAM

Boot ROM boots from RAM

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SHIFT

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SIZE

XS1_BOOT_CONFIG_BOOT_FROM_RAM_MASK

XS1_BOOT_CONFIG_BOOT_FROM_RAM(x)

Extract the BOOT_CONFIG_BOOT_FROM_RAM bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_BOOT_FROM_RAM bitfield into a packed word x and return the packed field.

BOOT_CONFIG_DISABLE_OTP_POLL

Cause the ROM to not poll the OTP for correct read levels

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SHIFT

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SIZE

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_MASK

XS1_BOOT_CONFIG_DISABLE_OTP_POLL(x)

Extract the BOOT_CONFIG_DISABLE_OTP_POLL bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_DISABLE_OTP_POLL bitfield into a packed word x and return the packed field.

BOOT_CONFIG_CORE1_POWER_DOWN_N

Indicates if core1 has been powered off

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SHIFT

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SIZE

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_MASK

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N(x)

Extract the BOOT_CONFIG_CORE1_POWER_DOWN_N bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_CORE1_POWER_DOWN_N bitfield into a packed word x and return the packed field.

BOOT_CONFIG_SECURE_BOOT

Overwrite BOOT_MODE.

XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT

XS1_BOOT_CONFIG_SECURE_BOOT_SIZE

XS1_BOOT_CONFIG_SECURE_BOOT_MASK

XS1_BOOT_CONFIG_SECURE_BOOT(x)

Extract the BOOT_CONFIG_SECURE_BOOT bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_SECURE_BOOT_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_SECURE_BOOT bitfield into a packed word x and return the packed field.

BOOT_CONFIG_PROCESSOR

Processor number.

XS1_BOOT_CONFIG_PROCESSOR_SHIFT

XS1_BOOT_CONFIG_PROCESSOR_SIZE

XS1_BOOT_CONFIG_PROCESSOR_MASK

XS1_BOOT_CONFIG_PROCESSOR(x)

Extract the BOOT_CONFIG_PROCESSOR bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_PROCESSOR_SET(x, v)

Pack the value (v) of the BOOT_CONFIG_PROCESSOR bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_XCORE_JTAG

Disable access to XCore’s JTAG debug TAP

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SHIFT

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SIZE

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_MASK

XS1_SECUR_CFG_DISABLE_XCORE_JTAG(x)

Extract the SECUR_CFG_DISABLE_XCORE_JTAG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SET(x, v)

Pack the value (v) of the SECUR_CFG_DISABLE_XCORE_JTAG bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_XCORE_PLINK

Disable PLinks

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SHIFT

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SIZE

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_MASK

XS1_SECUR_CFG_DISABLE_XCORE_PLINK(x)

Extract the SECUR_CFG_DISABLE_XCORE_PLINK bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SET(x, v)

Pack the value (v) of the SECUR_CFG_DISABLE_XCORE_PLINK bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_PLL_JTAG

Disable JTAG access to the PLL/BOOT configuration registers

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SHIFT

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SIZE

XS1_SECUR_CFG_DISABLE_PLL_JTAG_MASK

XS1_SECUR_CFG_DISABLE_PLL_JTAG(x)

Extract the SECUR_CFG_DISABLE_PLL_JTAG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SET(x, v)

Pack the value (v) of the SECUR_CFG_DISABLE_PLL_JTAG bitfield into a packed word x and return the packed field.

SECUR_CFG_SECURE_BOOT

Override boot mode and read boot image from OTP

XS1_SECUR_CFG_SECURE_BOOT_SHIFT

XS1_SECUR_CFG_SECURE_BOOT_SIZE

XS1_SECUR_CFG_SECURE_BOOT_MASK

XS1_SECUR_CFG_SECURE_BOOT(x)

Extract the SECUR_CFG_SECURE_BOOT bitfield from a packed word x and return it.

XS1_SECUR_CFG_SECURE_BOOT_SET(x, v)

Pack the value (v) of the SECUR_CFG_SECURE_BOOT bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_COMBINED

Combine OTP into a single address-space for reading.

XS1_SECUR_CFG_OTP_COMBINED_SHIFT

XS1_SECUR_CFG_OTP_COMBINED_SIZE

XS1_SECUR_CFG_OTP_COMBINED_MASK

XS1_SECUR_CFG_OTP_COMBINED(x)

Extract the SECUR_CFG_OTP_COMBINED bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_COMBINED_SET(x, v)

Pack the value (v) of the SECUR_CFG_OTP_COMBINED bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_PROGRAM_DISABLE

Prevent access to OTP SBPI interface to prevent programming and other functions.

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SHIFT

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SIZE

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_MASK

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE(x)

Extract the SECUR_CFG_OTP_PROGRAM_DISABLE bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SET(x, v)

Pack the value (v) of the SECUR_CFG_OTP_PROGRAM_DISABLE bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_READ_LOCK

Disable read access to OTP.

XS1_SECUR_CFG_OTP_READ_LOCK_SHIFT

XS1_SECUR_CFG_OTP_READ_LOCK_SIZE

XS1_SECUR_CFG_OTP_READ_LOCK_MASK

XS1_SECUR_CFG_OTP_READ_LOCK(x)

Extract the SECUR_CFG_OTP_READ_LOCK bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_READ_LOCK_SET(x, v)

Pack the value (v) of the SECUR_CFG_OTP_READ_LOCK bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_GLOBAL_DEBUG

Disable access to XCore’s global debug

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SHIFT

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SIZE

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_MASK

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG(x)

Extract the SECUR_CFG_DISABLE_GLOBAL_DEBUG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SET(x, v)

Pack the value (v) of the SECUR_CFG_DISABLE_GLOBAL_DEBUG bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_ACCESS

Disables write permission on this register

XS1_SECUR_CFG_DISABLE_ACCESS_SHIFT

XS1_SECUR_CFG_DISABLE_ACCESS_SIZE

XS1_SECUR_CFG_DISABLE_ACCESS_MASK

XS1_SECUR_CFG_DISABLE_ACCESS(x)

Extract the SECUR_CFG_DISABLE_ACCESS bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_ACCESS_SET(x, v)

Pack the value (v) of the SECUR_CFG_DISABLE_ACCESS bitfield into a packed word x and return the packed field.

BOOT_STATUS_LEDS

Boot status LED value.

XS1_BOOT_STATUS_LEDS_SHIFT

XS1_BOOT_STATUS_LEDS_SIZE

XS1_BOOT_STATUS_LEDS_MASK

XS1_BOOT_STATUS_LEDS(x)

Extract the BOOT_STATUS_LEDS bitfield from a packed word x and return it.

XS1_BOOT_STATUS_LEDS_SET(x, v)

Pack the value (v) of the BOOT_STATUS_LEDS bitfield into a packed word x and return the packed field.

BOOT_STATUS_BITS

Other boot status LED bits.

XS1_BOOT_STATUS_BITS_SHIFT

XS1_BOOT_STATUS_BITS_SIZE

XS1_BOOT_STATUS_BITS_MASK

XS1_BOOT_STATUS_BITS(x)

Extract the BOOT_STATUS_BITS bitfield from a packed word x and return it.

XS1_BOOT_STATUS_BITS_SET(x, v)

Pack the value (v) of the BOOT_STATUS_BITS bitfield into a packed word x and return the packed field.

RING_OSC_PERPH_ENABLE

Set to 1 to enable the core peripheral ring oscillator.

XS1_RING_OSC_PERPH_ENABLE_SHIFT

XS1_RING_OSC_PERPH_ENABLE_SIZE

XS1_RING_OSC_PERPH_ENABLE_MASK

XS1_RING_OSC_PERPH_ENABLE(x)

Extract the RING_OSC_PERPH_ENABLE bitfield from a packed word x and return it.

XS1_RING_OSC_PERPH_ENABLE_SET(x, v)

Pack the value (v) of the RING_OSC_PERPH_ENABLE bitfield into a packed word x and return the packed field.

RING_OSC_CORE_ENABLE

Core ring oscillator enable.

XS1_RING_OSC_CORE_ENABLE_SHIFT

XS1_RING_OSC_CORE_ENABLE_SIZE

XS1_RING_OSC_CORE_ENABLE_MASK

XS1_RING_OSC_CORE_ENABLE(x)

Extract the RING_OSC_CORE_ENABLE bitfield from a packed word x and return it.

XS1_RING_OSC_CORE_ENABLE_SET(x, v)

Pack the value (v) of the RING_OSC_CORE_ENABLE bitfield into a packed word x and return the packed field.

RING_OSC_DATA

Ring oscillator Counter data.

XS1_RING_OSC_DATA_SHIFT

XS1_RING_OSC_DATA_SIZE

XS1_RING_OSC_DATA_MASK

XS1_RING_OSC_DATA(x)

Extract the RING_OSC_DATA bitfield from a packed word x and return it.

XS1_RING_OSC_DATA_SET(x, v)

Pack the value (v) of the RING_OSC_DATA bitfield into a packed word x and return the packed field.

PLL_CLK_DIVIDER

Clock divider.

XS1_PLL_CLK_DIVIDER_SHIFT

XS1_PLL_CLK_DIVIDER_SIZE

XS1_PLL_CLK_DIVIDER_MASK

XS1_PLL_CLK_DIVIDER(x)

Extract the PLL_CLK_DIVIDER bitfield from a packed word x and return it.

XS1_PLL_CLK_DIVIDER_SET(x, v)

Pack the value (v) of the PLL_CLK_DIVIDER bitfield into a packed word x and return the packed field.

PLL_CLK_DISABLE

Clock disable.

Writing ‘1’ will remove the clock to the tile.

XS1_PLL_CLK_DISABLE_SHIFT

XS1_PLL_CLK_DISABLE_SIZE

XS1_PLL_CLK_DISABLE_MASK

XS1_PLL_CLK_DISABLE(x)

Extract the PLL_CLK_DISABLE bitfield from a packed word x and return it.

XS1_PLL_CLK_DISABLE_SET(x, v)

Pack the value (v) of the PLL_CLK_DISABLE bitfield into a packed word x and return the packed field.

RTSEL

ROM debug timing adjust.

XS1_RTSEL_SHIFT

XS1_RTSEL_SIZE

XS1_RTSEL_MASK

XS1_RTSEL(x)

Extract the RTSEL bitfield from a packed word x and return it.

XS1_RTSEL_SET(x, v)

Pack the value (v) of the RTSEL bitfield into a packed word x and return the packed field.

PTSEL

ROM debug timing adjust.

XS1_PTSEL_SHIFT

XS1_PTSEL_SIZE

XS1_PTSEL_MASK

XS1_PTSEL(x)

Extract the PTSEL bitfield from a packed word x and return it.

XS1_PTSEL_SET(x, v)

Pack the value (v) of the PTSEL bitfield into a packed word x and return the packed field.

TRB

ROM debug timing adjust.

XS1_TRB_SHIFT

XS1_TRB_SIZE

XS1_TRB_MASK

XS1_TRB(x)

Extract the TRB bitfield from a packed word x and return it.

XS1_TRB_SET(x, v)

Pack the value (v) of the TRB bitfield into a packed word x and return the packed field.

RAM_MASK

Blocks of 64k rams unavailable

XS1_RAM_MASK_SHIFT

XS1_RAM_MASK_SIZE

XS1_RAM_MASK_MASK

XS1_RAM_MASK(x)

Extract the RAM_MASK bitfield from a packed word x and return it.

XS1_RAM_MASK_SET(x, v)

Pack the value (v) of the RAM_MASK bitfield into a packed word x and return the packed field.

CORE1_DISABLE

Core 1’s clock is gated off

XS1_CORE1_DISABLE_SHIFT

XS1_CORE1_DISABLE_SIZE

XS1_CORE1_DISABLE_MASK

XS1_CORE1_DISABLE(x)

Extract the CORE1_DISABLE bitfield from a packed word x and return it.

XS1_CORE1_DISABLE_SET(x, v)

Pack the value (v) of the CORE1_DISABLE bitfield into a packed word x and return the packed field.

THREAD_MASK

Threads unavailable

XS1_THREAD_MASK_SHIFT

XS1_THREAD_MASK_SIZE

XS1_THREAD_MASK_MASK

XS1_THREAD_MASK(x)

Extract the THREAD_MASK bitfield from a packed word x and return it.

XS1_THREAD_MASK_SET(x, v)

Pack the value (v) of the THREAD_MASK bitfield into a packed word x and return the packed field.

THREAD_CTRL0_INUSE

Returns 1 when the thread is in use, 0 otherwise.

XS1_THREAD_CTRL0_INUSE_SHIFT

XS1_THREAD_CTRL0_INUSE_SIZE

XS1_THREAD_CTRL0_INUSE_MASK

XS1_THREAD_CTRL0_INUSE(x)

Extract the THREAD_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the THREAD_CTRL0_INUSE bitfield into a packed word x and return the packed field.

THREAD_CTRL0_MSYNC

1 when the thread is msyncing, 0 otherwise.

XS1_THREAD_CTRL0_MSYNC_SHIFT

XS1_THREAD_CTRL0_MSYNC_SIZE

XS1_THREAD_CTRL0_MSYNC_MASK

XS1_THREAD_CTRL0_MSYNC(x)

Extract the THREAD_CTRL0_MSYNC bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_MSYNC_SET(x, v)

Pack the value (v) of the THREAD_CTRL0_MSYNC bitfield into a packed word x and return the packed field.

THREAD_CTRL0_SSYNC

1 when the thread is ssyncing, 0 otherwise.

XS1_THREAD_CTRL0_SSYNC_SHIFT

XS1_THREAD_CTRL0_SSYNC_SIZE

XS1_THREAD_CTRL0_SSYNC_MASK

XS1_THREAD_CTRL0_SSYNC(x)

Extract the THREAD_CTRL0_SSYNC bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_SSYNC_SET(x, v)

Pack the value (v) of the THREAD_CTRL0_SSYNC bitfield into a packed word x and return the packed field.

THREAD_CTRL0_MASTER

Returns the ID of this thread’s master.

XS1_THREAD_CTRL0_MASTER_SHIFT

XS1_THREAD_CTRL0_MASTER_SIZE

XS1_THREAD_CTRL0_MASTER_MASK

XS1_THREAD_CTRL0_MASTER(x)

Extract the THREAD_CTRL0_MASTER bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_MASTER_SET(x, v)

Pack the value (v) of the THREAD_CTRL0_MASTER bitfield into a packed word x and return the packed field.

PORT_CTRL0_INUSE

Returns 1 when the port is in use, 0 otherwise.

XS1_PORT_CTRL0_INUSE_SHIFT

XS1_PORT_CTRL0_INUSE_SIZE

XS1_PORT_CTRL0_INUSE_MASK

XS1_PORT_CTRL0_INUSE(x)

Extract the PORT_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the PORT_CTRL0_INUSE bitfield into a packed word x and return the packed field.

PORT_CTRL0_IE_MODE

0 when this port will cause events, 1 when it will raise interrupts.

It is controlled using the SETC instruction.

XS1_PORT_CTRL0_IE_MODE_SHIFT

XS1_PORT_CTRL0_IE_MODE_SIZE

XS1_PORT_CTRL0_IE_MODE_MASK

XS1_PORT_CTRL0_IE_MODE(x)

Extract the PORT_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_IE_MODE_SET(x, v)

Pack the value (v) of the PORT_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

PORT_CTRL0_IE_ENABLED

1 when events or interrupts on this port are active.

It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_PORT_CTRL0_IE_ENABLED_SHIFT

XS1_PORT_CTRL0_IE_ENABLED_SIZE

XS1_PORT_CTRL0_IE_ENABLED_MASK

XS1_PORT_CTRL0_IE_ENABLED(x)

Extract the PORT_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_PORT_CTRL0_IE_ENABLED_SET(x, v)

Pack the value (v) of the PORT_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

PORT_CTRL0_DIRECTION

0 when it is in input mode, 1 when this port is in output mode.

XS1_PORT_CTRL0_DIRECTION_SHIFT

XS1_PORT_CTRL0_DIRECTION_SIZE

XS1_PORT_CTRL0_DIRECTION_MASK

XS1_PORT_CTRL0_DIRECTION(x)

Extract the PORT_CTRL0_DIRECTION bitfield from a packed word x and return it.

XS1_PORT_CTRL0_DIRECTION_SET(x, v)

Pack the value (v) of the PORT_CTRL0_DIRECTION bitfield into a packed word x and return the packed field.

PORT_CTRL0_COND

Shows the current condition of the port.

The condition is set using the SETC instruction.

XS1_PORT_CTRL0_COND_SHIFT

XS1_PORT_CTRL0_COND_SIZE

XS1_PORT_CTRL0_COND_MASK

XS1_PORT_CTRL0_COND(x)

Extract the PORT_CTRL0_COND bitfield from a packed word x and return it.

XS1_PORT_CTRL0_COND_SET(x, v)

Pack the value (v) of the PORT_CTRL0_COND bitfield into a packed word x and return the packed field.

PORT_CTRL0_MASTER_SLAVE

0 when the port is a master, 1 when it is a slave.

XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT

XS1_PORT_CTRL0_MASTER_SLAVE_SIZE

XS1_PORT_CTRL0_MASTER_SLAVE_MASK

XS1_PORT_CTRL0_MASTER_SLAVE(x)

Extract the PORT_CTRL0_MASTER_SLAVE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_MASTER_SLAVE_SET(x, v)

Pack the value (v) of the PORT_CTRL0_MASTER_SLAVE bitfield into a packed word x and return the packed field.

PORT_CTRL0_BUFFERS

When 0 there is no buffering between the port and pins.

When 1 there is buffering between the port and instructions.

XS1_PORT_CTRL0_BUFFERS_SHIFT

XS1_PORT_CTRL0_BUFFERS_SIZE

XS1_PORT_CTRL0_BUFFERS_MASK

XS1_PORT_CTRL0_BUFFERS(x)

Extract the PORT_CTRL0_BUFFERS bitfield from a packed word x and return it.

XS1_PORT_CTRL0_BUFFERS_SET(x, v)

Pack the value (v) of the PORT_CTRL0_BUFFERS bitfield into a packed word x and return the packed field.

PORT_CTRL0_READY_MODE

0 - no ready signals used, 1 - strobed port, 2 - handshaken port

XS1_PORT_CTRL0_READY_MODE_SHIFT

XS1_PORT_CTRL0_READY_MODE_SIZE

XS1_PORT_CTRL0_READY_MODE_MASK

XS1_PORT_CTRL0_READY_MODE(x)

Extract the PORT_CTRL0_READY_MODE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_READY_MODE_SET(x, v)

Pack the value (v) of the PORT_CTRL0_READY_MODE bitfield into a packed word x and return the packed field.

PORT_CTRL0_PORT_TYPE

0 - data port, 1 - clock port (1-bit ports only), 2 - ready port (1-bit ports only)

XS1_PORT_CTRL0_PORT_TYPE_SHIFT

XS1_PORT_CTRL0_PORT_TYPE_SIZE

XS1_PORT_CTRL0_PORT_TYPE_MASK

XS1_PORT_CTRL0_PORT_TYPE(x)

Extract the PORT_CTRL0_PORT_TYPE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_PORT_TYPE_SET(x, v)

Pack the value (v) of the PORT_CTRL0_PORT_TYPE bitfield into a packed word x and return the packed field.

PORT_CTRL0_INVERT

When 1 the port is inverted, otherwise it is not inverted.

Only possible on 1-bit ports.

XS1_PORT_CTRL0_INVERT_SHIFT

XS1_PORT_CTRL0_INVERT_SIZE

XS1_PORT_CTRL0_INVERT_MASK

XS1_PORT_CTRL0_INVERT(x)

Extract the PORT_CTRL0_INVERT bitfield from a packed word x and return it.

XS1_PORT_CTRL0_INVERT_SET(x, v)

Pack the value (v) of the PORT_CTRL0_INVERT bitfield into a packed word x and return the packed field.

PORT_CTRL0_SDELAY

0 when the input uses the rising edge, 1 when it uses the falling edge of the clock.

XS1_PORT_CTRL0_SDELAY_SHIFT

XS1_PORT_CTRL0_SDELAY_SIZE

XS1_PORT_CTRL0_SDELAY_MASK

XS1_PORT_CTRL0_SDELAY(x)

Extract the PORT_CTRL0_SDELAY bitfield from a packed word x and return it.

XS1_PORT_CTRL0_SDELAY_SET(x, v)

Pack the value (v) of the PORT_CTRL0_SDELAY bitfield into a packed word x and return the packed field.

PORT_CTRL0_EV_VALID

1 when the Environment Vector is valid.

When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_PORT_CTRL0_EV_VALID_SHIFT

XS1_PORT_CTRL0_EV_VALID_SIZE

XS1_PORT_CTRL0_EV_VALID_MASK

XS1_PORT_CTRL0_EV_VALID(x)

Extract the PORT_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_PORT_CTRL0_EV_VALID_SET(x, v)

Pack the value (v) of the PORT_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

PORT_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this port.

XS1_PORT_CTRL0_T_WAITING_SHIFT

XS1_PORT_CTRL0_T_WAITING_SIZE

XS1_PORT_CTRL0_T_WAITING_MASK

XS1_PORT_CTRL0_T_WAITING(x)

Extract the PORT_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_PORT_CTRL0_T_WAITING_SET(x, v)

Pack the value (v) of the PORT_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

PORT_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this port.

XS1_PORT_CTRL0_T_NUM_SHIFT

XS1_PORT_CTRL0_T_NUM_SIZE

XS1_PORT_CTRL0_T_NUM_MASK

XS1_PORT_CTRL0_T_NUM(x)

Extract the PORT_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_PORT_CTRL0_T_NUM_SET(x, v)

Pack the value (v) of the PORT_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

PORT_CTRL1_DRIVE

Determines whether the output is driving, open drain or pull down.

XS1_PORT_CTRL1_DRIVE_SHIFT

XS1_PORT_CTRL1_DRIVE_SIZE

XS1_PORT_CTRL1_DRIVE_MASK

XS1_PORT_CTRL1_DRIVE(x)

Extract the PORT_CTRL1_DRIVE bitfield from a packed word x and return it.

XS1_PORT_CTRL1_DRIVE_SET(x, v)

Pack the value (v) of the PORT_CTRL1_DRIVE bitfield into a packed word x and return the packed field.

PORT_CTRL1_TWIDTH

The transfer width of the port in bits

XS1_PORT_CTRL1_TWIDTH_SHIFT

XS1_PORT_CTRL1_TWIDTH_SIZE

XS1_PORT_CTRL1_TWIDTH_MASK

XS1_PORT_CTRL1_TWIDTH(x)

Extract the PORT_CTRL1_TWIDTH bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TWIDTH_SET(x, v)

Pack the value (v) of the PORT_CTRL1_TWIDTH bitfield into a packed word x and return the packed field.

PORT_CTRL1_SREG_COUNT

The shift register count in port widths.

XS1_PORT_CTRL1_SREG_COUNT_SHIFT

XS1_PORT_CTRL1_SREG_COUNT_SIZE

XS1_PORT_CTRL1_SREG_COUNT_MASK

XS1_PORT_CTRL1_SREG_COUNT(x)

Extract the PORT_CTRL1_SREG_COUNT bitfield from a packed word x and return it.

XS1_PORT_CTRL1_SREG_COUNT_SET(x, v)

Pack the value (v) of the PORT_CTRL1_SREG_COUNT bitfield into a packed word x and return the packed field.

PORT_CTRL1_TREG_FULL

1 when the transfer register is full.

XS1_PORT_CTRL1_TREG_FULL_SHIFT

XS1_PORT_CTRL1_TREG_FULL_SIZE

XS1_PORT_CTRL1_TREG_FULL_MASK

XS1_PORT_CTRL1_TREG_FULL(x)

Extract the PORT_CTRL1_TREG_FULL bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TREG_FULL_SET(x, v)

Pack the value (v) of the PORT_CTRL1_TREG_FULL bitfield into a packed word x and return the packed field.

PORT_CTRL1_CHANGE_DIR

0 when the direction is fixed, 1 when it is going to change.

XS1_PORT_CTRL1_CHANGE_DIR_SHIFT

XS1_PORT_CTRL1_CHANGE_DIR_SIZE

XS1_PORT_CTRL1_CHANGE_DIR_MASK

XS1_PORT_CTRL1_CHANGE_DIR(x)

Extract the PORT_CTRL1_CHANGE_DIR bitfield from a packed word x and return it.

XS1_PORT_CTRL1_CHANGE_DIR_SET(x, v)

Pack the value (v) of the PORT_CTRL1_CHANGE_DIR bitfield into a packed word x and return the packed field.

PORT_CTRL1_SYNCR

1 when a SYNCR instruction is pending completion.

XS1_PORT_CTRL1_SYNCR_SHIFT

XS1_PORT_CTRL1_SYNCR_SIZE

XS1_PORT_CTRL1_SYNCR_MASK

XS1_PORT_CTRL1_SYNCR(x)

Extract the PORT_CTRL1_SYNCR bitfield from a packed word x and return it.

XS1_PORT_CTRL1_SYNCR_SET(x, v)

Pack the value (v) of the PORT_CTRL1_SYNCR bitfield into a packed word x and return the packed field.

PORT_CTRL1_INST_COMMITTED

1 when an instruction has committed to operating on the port.

XS1_PORT_CTRL1_INST_COMMITTED_SHIFT

XS1_PORT_CTRL1_INST_COMMITTED_SIZE

XS1_PORT_CTRL1_INST_COMMITTED_MASK

XS1_PORT_CTRL1_INST_COMMITTED(x)

Extract the PORT_CTRL1_INST_COMMITTED bitfield from a packed word x and return it.

XS1_PORT_CTRL1_INST_COMMITTED_SET(x, v)

Pack the value (v) of the PORT_CTRL1_INST_COMMITTED bitfield into a packed word x and return the packed field.

PORT_CTRL1_HOLD_DATA

1 data has been captured for a condition and is being held.

XS1_PORT_CTRL1_HOLD_DATA_SHIFT

XS1_PORT_CTRL1_HOLD_DATA_SIZE

XS1_PORT_CTRL1_HOLD_DATA_MASK

XS1_PORT_CTRL1_HOLD_DATA(x)

Extract the PORT_CTRL1_HOLD_DATA bitfield from a packed word x and return it.

XS1_PORT_CTRL1_HOLD_DATA_SET(x, v)

Pack the value (v) of the PORT_CTRL1_HOLD_DATA bitfield into a packed word x and return the packed field.

PORT_CTRL1_WAIT_FOR_TIME

1 when waiting for the port time to be met.

XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT

XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE

XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK

XS1_PORT_CTRL1_WAIT_FOR_TIME(x)

Extract the PORT_CTRL1_WAIT_FOR_TIME bitfield from a packed word x and return it.

XS1_PORT_CTRL1_WAIT_FOR_TIME_SET(x, v)

Pack the value (v) of the PORT_CTRL1_WAIT_FOR_TIME bitfield into a packed word x and return the packed field.

PORT_CTRL1_TIMEMET

1 when a SETPT is used.

XS1_PORT_CTRL1_TIMEMET_SHIFT

XS1_PORT_CTRL1_TIMEMET_SIZE

XS1_PORT_CTRL1_TIMEMET_MASK

XS1_PORT_CTRL1_TIMEMET(x)

Extract the PORT_CTRL1_TIMEMET bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TIMEMET_SET(x, v)

Pack the value (v) of the PORT_CTRL1_TIMEMET bitfield into a packed word x and return the packed field.

PORT_CTRL1_ENDIN

1 when an ENDIN is used on a BUFFERS port and the tReg was full.

XS1_PORT_CTRL1_ENDIN_SHIFT

XS1_PORT_CTRL1_ENDIN_SIZE

XS1_PORT_CTRL1_ENDIN_MASK

XS1_PORT_CTRL1_ENDIN(x)

Extract the PORT_CTRL1_ENDIN bitfield from a packed word x and return it.

XS1_PORT_CTRL1_ENDIN_SET(x, v)

Pack the value (v) of the PORT_CTRL1_ENDIN bitfield into a packed word x and return the packed field.

PORT_CTRL2_TIME

The port time value.

XS1_PORT_CTRL2_TIME_SHIFT

XS1_PORT_CTRL2_TIME_SIZE

XS1_PORT_CTRL2_TIME_MASK

XS1_PORT_CTRL2_TIME(x)

Extract the PORT_CTRL2_TIME bitfield from a packed word x and return it.

XS1_PORT_CTRL2_TIME_SET(x, v)

Pack the value (v) of the PORT_CTRL2_TIME bitfield into a packed word x and return the packed field.

PORT_CTRL2_PIN_DELAY

The port pin delay.

XS1_PORT_CTRL2_PIN_DELAY_SHIFT

XS1_PORT_CTRL2_PIN_DELAY_SIZE

XS1_PORT_CTRL2_PIN_DELAY_MASK

XS1_PORT_CTRL2_PIN_DELAY(x)

Extract the PORT_CTRL2_PIN_DELAY bitfield from a packed word x and return it.

XS1_PORT_CTRL2_PIN_DELAY_SET(x, v)

Pack the value (v) of the PORT_CTRL2_PIN_DELAY bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_OEN

The pad control output enable.

XS1_PORT_PAD_CTRL_OEN_SHIFT

XS1_PORT_PAD_CTRL_OEN_SIZE

XS1_PORT_PAD_CTRL_OEN_MASK

XS1_PORT_PAD_CTRL_OEN(x)

Extract the PORT_PAD_CTRL_OEN bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_OEN_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_OEN bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_REN

The pad control read enable.

XS1_PORT_PAD_CTRL_REN_SHIFT

XS1_PORT_PAD_CTRL_REN_SIZE

XS1_PORT_PAD_CTRL_REN_MASK

XS1_PORT_PAD_CTRL_REN(x)

Extract the PORT_PAD_CTRL_REN bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_REN_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_REN bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_P

The pad control pull.

XS1_PORT_PAD_CTRL_P_SHIFT

XS1_PORT_PAD_CTRL_P_SIZE

XS1_PORT_PAD_CTRL_P_MASK

XS1_PORT_PAD_CTRL_P(x)

Extract the PORT_PAD_CTRL_P bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_P_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_P bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_E

The pad control drive strength.

XS1_PORT_PAD_CTRL_E_SHIFT

XS1_PORT_PAD_CTRL_E_SIZE

XS1_PORT_PAD_CTRL_E_MASK

XS1_PORT_PAD_CTRL_E(x)

Extract the PORT_PAD_CTRL_E bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_E_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_E bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_SR

The pad control slew rate.

XS1_PORT_PAD_CTRL_SR_SHIFT

XS1_PORT_PAD_CTRL_SR_SIZE

XS1_PORT_PAD_CTRL_SR_MASK

XS1_PORT_PAD_CTRL_SR(x)

Extract the PORT_PAD_CTRL_SR bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_SR_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_SR bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_SMT

The pad control Schmitt trigger enable.

XS1_PORT_PAD_CTRL_SMT_SHIFT

XS1_PORT_PAD_CTRL_SMT_SIZE

XS1_PORT_PAD_CTRL_SMT_MASK

XS1_PORT_PAD_CTRL_SMT(x)

Extract the PORT_PAD_CTRL_SMT bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_SMT_SET(x, v)

Pack the value (v) of the PORT_PAD_CTRL_SMT bitfield into a packed word x and return the packed field.

TIMER_CTRL0_INUSE

Returns 1 when it in use, 0 otherwise.

XS1_TIMER_CTRL0_INUSE_SHIFT

XS1_TIMER_CTRL0_INUSE_SIZE

XS1_TIMER_CTRL0_INUSE_MASK

XS1_TIMER_CTRL0_INUSE(x)

Extract the TIMER_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_INUSE bitfield into a packed word x and return the packed field.

TIMER_CTRL0_IE_MODE

0 when this timer will cause events, 1 when it will raise interrupts.

It is controlled using the SETC instruction.

XS1_TIMER_CTRL0_IE_MODE_SHIFT

XS1_TIMER_CTRL0_IE_MODE_SIZE

XS1_TIMER_CTRL0_IE_MODE_MASK

XS1_TIMER_CTRL0_IE_MODE(x)

Extract the TIMER_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_IE_MODE_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

TIMER_CTRL0_IE_ENABLED

1 when events or interrupts on this timer are active.

It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_TIMER_CTRL0_IE_ENABLED_SHIFT

XS1_TIMER_CTRL0_IE_ENABLED_SIZE

XS1_TIMER_CTRL0_IE_ENABLED_MASK

XS1_TIMER_CTRL0_IE_ENABLED(x)

Extract the TIMER_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_IE_ENABLED_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

TIMER_CTRL0_READY

1 when the condition has been met.

It is cleared when a SETC, SETD, SETV, SETC or IN instruction is executed on the timer. 0 when the timer is not in use.

XS1_TIMER_CTRL0_READY_SHIFT

XS1_TIMER_CTRL0_READY_SIZE

XS1_TIMER_CTRL0_READY_MASK

XS1_TIMER_CTRL0_READY(x)

Extract the TIMER_CTRL0_READY bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_READY_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_READY bitfield into a packed word x and return the packed field.

TIMER_CTRL0_COND

Shows the current condition of the timer.

The condition is set using the SETC instruction.

XS1_TIMER_CTRL0_COND_SHIFT

XS1_TIMER_CTRL0_COND_SIZE

XS1_TIMER_CTRL0_COND_MASK

XS1_TIMER_CTRL0_COND(x)

Extract the TIMER_CTRL0_COND bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_COND_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_COND bitfield into a packed word x and return the packed field.

TIMER_CTRL0_EV_VALID

1 when the Environment Vector is valid.

When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_TIMER_CTRL0_EV_VALID_SHIFT

XS1_TIMER_CTRL0_EV_VALID_SIZE

XS1_TIMER_CTRL0_EV_VALID_MASK

XS1_TIMER_CTRL0_EV_VALID(x)

Extract the TIMER_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_EV_VALID_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

TIMER_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this timer.

XS1_TIMER_CTRL0_T_WAITING_SHIFT

XS1_TIMER_CTRL0_T_WAITING_SIZE

XS1_TIMER_CTRL0_T_WAITING_MASK

XS1_TIMER_CTRL0_T_WAITING(x)

Extract the TIMER_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_T_WAITING_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

TIMER_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this timer.

XS1_TIMER_CTRL0_T_NUM_SHIFT

XS1_TIMER_CTRL0_T_NUM_SIZE

XS1_TIMER_CTRL0_T_NUM_MASK

XS1_TIMER_CTRL0_T_NUM(x)

Extract the TIMER_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_T_NUM_SET(x, v)

Pack the value (v) of the TIMER_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_INUSE

Returns 1 when it in use, 0 otherwise.

XS1_SWMEM_CTRL0_INUSE_SHIFT

XS1_SWMEM_CTRL0_INUSE_SIZE

XS1_SWMEM_CTRL0_INUSE_MASK

XS1_SWMEM_CTRL0_INUSE(x)

Extract the SWMEM_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_INUSE bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_IE_MODE

0 when this SWMEM resource will cause events, 1 when it will raise interrupts.

It is controlled using the SETC instruction.

XS1_SWMEM_CTRL0_IE_MODE_SHIFT

XS1_SWMEM_CTRL0_IE_MODE_SIZE

XS1_SWMEM_CTRL0_IE_MODE_MASK

XS1_SWMEM_CTRL0_IE_MODE(x)

Extract the SWMEM_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_IE_MODE_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_IE_ENABLED

1 when events or interrupts on this SWMEM are active.

It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT

XS1_SWMEM_CTRL0_IE_ENABLED_SIZE

XS1_SWMEM_CTRL0_IE_ENABLED_MASK

XS1_SWMEM_CTRL0_IE_ENABLED(x)

Extract the SWMEM_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_IE_ENABLED_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_READY

1 when the condition has been met.

It is cleared when a SETC, SETD, SETV, SETC or IN instruction is executed on the SWMEM. 0 when the SWMEM is not in use.

XS1_SWMEM_CTRL0_READY_SHIFT

XS1_SWMEM_CTRL0_READY_SIZE

XS1_SWMEM_CTRL0_READY_MASK

XS1_SWMEM_CTRL0_READY(x)

Extract the SWMEM_CTRL0_READY bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_READY_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_READY bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_COND

Shows the current condition of the SWMEM.

The condition is set using the SETC instruction.

XS1_SWMEM_CTRL0_COND_SHIFT

XS1_SWMEM_CTRL0_COND_SIZE

XS1_SWMEM_CTRL0_COND_MASK

XS1_SWMEM_CTRL0_COND(x)

Extract the SWMEM_CTRL0_COND bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_COND_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_COND bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_EV_VALID

1 when the Environment Vector is valid.

When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_SWMEM_CTRL0_EV_VALID_SHIFT

XS1_SWMEM_CTRL0_EV_VALID_SIZE

XS1_SWMEM_CTRL0_EV_VALID_MASK

XS1_SWMEM_CTRL0_EV_VALID(x)

Extract the SWMEM_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_EV_VALID_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this SWMEM.

XS1_SWMEM_CTRL0_T_WAITING_SHIFT

XS1_SWMEM_CTRL0_T_WAITING_SIZE

XS1_SWMEM_CTRL0_T_WAITING_MASK

XS1_SWMEM_CTRL0_T_WAITING(x)

Extract the SWMEM_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_T_WAITING_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this SWMEM resource.

XS1_SWMEM_CTRL0_T_NUM_SHIFT

XS1_SWMEM_CTRL0_T_NUM_SIZE

XS1_SWMEM_CTRL0_T_NUM_MASK

XS1_SWMEM_CTRL0_T_NUM(x)

Extract the SWMEM_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_T_NUM_SET(x, v)

Pack the value (v) of the SWMEM_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

OTPA_MOSI_LSB

OTP arbiter MOSI LSB.

XS1_OTPA_MOSI_LSB_SHIFT

XS1_OTPA_MOSI_LSB_SIZE

XS1_OTPA_MOSI_LSB_MASK

XS1_OTPA_MOSI_LSB(x)

Extract the OTPA_MOSI_LSB bitfield from a packed word x and return it.

XS1_OTPA_MOSI_LSB_SET(x, v)

Pack the value (v) of the OTPA_MOSI_LSB bitfield into a packed word x and return the packed field.

OTPA_MOSI_MSB

OTP arbiter MOSI LSB.

XS1_OTPA_MOSI_MSB_SHIFT

XS1_OTPA_MOSI_MSB_SIZE

XS1_OTPA_MOSI_MSB_MASK

XS1_OTPA_MOSI_MSB(x)

Extract the OTPA_MOSI_MSB bitfield from a packed word x and return it.

XS1_OTPA_MOSI_MSB_SET(x, v)

Pack the value (v) of the OTPA_MOSI_MSB bitfield into a packed word x and return the packed field.

OTPA_CLK_IDX

OTP SBPI CLK input.

XS1_OTPA_CLK_IDX_SHIFT

XS1_OTPA_CLK_IDX_SIZE

XS1_OTPA_CLK_IDX_MASK

XS1_OTPA_CLK_IDX(x)

Extract the OTPA_CLK_IDX bitfield from a packed word x and return it.

XS1_OTPA_CLK_IDX_SET(x, v)

Pack the value (v) of the OTPA_CLK_IDX bitfield into a packed word x and return the packed field.

OTPA_SP_IDX

OTP SBPI SP input.

XS1_OTPA_SP_IDX_SHIFT

XS1_OTPA_SP_IDX_SIZE

XS1_OTPA_SP_IDX_MASK

XS1_OTPA_SP_IDX(x)

Extract the OTPA_SP_IDX bitfield from a packed word x and return it.

XS1_OTPA_SP_IDX_SET(x, v)

Pack the value (v) of the OTPA_SP_IDX bitfield into a packed word x and return the packed field.

OTPA_CS_IDX

OTP SBPI CS (chip select) input.

XS1_OTPA_CS_IDX_SHIFT

XS1_OTPA_CS_IDX_SIZE

XS1_OTPA_CS_IDX_MASK

XS1_OTPA_CS_IDX(x)

Extract the OTPA_CS_IDX bitfield from a packed word x and return it.

XS1_OTPA_CS_IDX_SET(x, v)

Pack the value (v) of the OTPA_CS_IDX bitfield into a packed word x and return the packed field.

OTPA_CKE_IDX

OTP SBPI CKE (clock enable) input.

XS1_OTPA_CKE_IDX_SHIFT

XS1_OTPA_CKE_IDX_SIZE

XS1_OTPA_CKE_IDX_MASK

XS1_OTPA_CKE_IDX(x)

Extract the OTPA_CKE_IDX bitfield from a packed word x and return it.

XS1_OTPA_CKE_IDX_SET(x, v)

Pack the value (v) of the OTPA_CKE_IDX bitfield into a packed word x and return the packed field.

OTPA_DCTRL_IDX

OTP USER DCTRL input.

XS1_OTPA_DCTRL_IDX_SHIFT

XS1_OTPA_DCTRL_IDX_SIZE

XS1_OTPA_DCTRL_IDX_MASK

XS1_OTPA_DCTRL_IDX(x)

Extract the OTPA_DCTRL_IDX bitfield from a packed word x and return it.

XS1_OTPA_DCTRL_IDX_SET(x, v)

Pack the value (v) of the OTPA_DCTRL_IDX bitfield into a packed word x and return the packed field.

OTPA_PD_IDX

OTP USER PD input.

XS1_OTPA_PD_IDX_SHIFT

XS1_OTPA_PD_IDX_SIZE

XS1_OTPA_PD_IDX_MASK

XS1_OTPA_PD_IDX(x)

Extract the OTPA_PD_IDX bitfield from a packed word x and return it.

XS1_OTPA_PD_IDX_SET(x, v)

Pack the value (v) of the OTPA_PD_IDX bitfield into a packed word x and return the packed field.

OTPA_SEL_IDX

OTP USER SEL input.

XS1_OTPA_SEL_IDX_SHIFT

XS1_OTPA_SEL_IDX_SIZE

XS1_OTPA_SEL_IDX_MASK

XS1_OTPA_SEL_IDX(x)

Extract the OTPA_SEL_IDX bitfield from a packed word x and return it.

XS1_OTPA_SEL_IDX_SET(x, v)

Pack the value (v) of the OTPA_SEL_IDX bitfield into a packed word x and return the packed field.

OTPA_CK_IDX

OTP USER CK input.

XS1_OTPA_CK_IDX_SHIFT

XS1_OTPA_CK_IDX_SIZE

XS1_OTPA_CK_IDX_MASK

XS1_OTPA_CK_IDX(x)

Extract the OTPA_CK_IDX bitfield from a packed word x and return it.

XS1_OTPA_CK_IDX_SET(x, v)

Pack the value (v) of the OTPA_CK_IDX bitfield into a packed word x and return the packed field.

OTPA_A_LSB

OTP USER A (address) LSB (bit 0).

XS1_OTPA_A_LSB_SHIFT

XS1_OTPA_A_LSB_SIZE

XS1_OTPA_A_LSB_MASK

XS1_OTPA_A_LSB(x)

Extract the OTPA_A_LSB bitfield from a packed word x and return it.

XS1_OTPA_A_LSB_SET(x, v)

Pack the value (v) of the OTPA_A_LSB bitfield into a packed word x and return the packed field.

OTPA_A_MSB

OTP USER A (address) MSB (bit 10).

XS1_OTPA_A_MSB_SHIFT

XS1_OTPA_A_MSB_SIZE

XS1_OTPA_A_MSB_MASK

XS1_OTPA_A_MSB(x)

Extract the OTPA_A_MSB bitfield from a packed word x and return it.

XS1_OTPA_A_MSB_SET(x, v)

Pack the value (v) of the OTPA_A_MSB bitfield into a packed word x and return the packed field.

OTPA_RST_IDX

OTP reset input (active high)

XS1_OTPA_RST_IDX_SHIFT

XS1_OTPA_RST_IDX_SIZE

XS1_OTPA_RST_IDX_MASK

XS1_OTPA_RST_IDX(x)

Extract the OTPA_RST_IDX bitfield from a packed word x and return it.

XS1_OTPA_RST_IDX_SET(x, v)

Pack the value (v) of the OTPA_RST_IDX bitfield into a packed word x and return the packed field.

OTPA_ARB_REQ_IDX

OTP arbiter request

XS1_OTPA_ARB_REQ_IDX_SHIFT

XS1_OTPA_ARB_REQ_IDX_SIZE

XS1_OTPA_ARB_REQ_IDX_MASK

XS1_OTPA_ARB_REQ_IDX(x)

Extract the OTPA_ARB_REQ_IDX bitfield from a packed word x and return it.

XS1_OTPA_ARB_REQ_IDX_SET(x, v)

Pack the value (v) of the OTPA_ARB_REQ_IDX bitfield into a packed word x and return the packed field.

OTPA_MUXSEL_LSB

OTP mux select LSB

XS1_OTPA_MUXSEL_LSB_SHIFT

XS1_OTPA_MUXSEL_LSB_SIZE

XS1_OTPA_MUXSEL_LSB_MASK

XS1_OTPA_MUXSEL_LSB(x)

Extract the OTPA_MUXSEL_LSB bitfield from a packed word x and return it.

XS1_OTPA_MUXSEL_LSB_SET(x, v)

Pack the value (v) of the OTPA_MUXSEL_LSB bitfield into a packed word x and return the packed field.

OTPA_MUXSEL_MSB

OTP mux select MSB

XS1_OTPA_MUXSEL_MSB_SHIFT

XS1_OTPA_MUXSEL_MSB_SIZE

XS1_OTPA_MUXSEL_MSB_MASK

XS1_OTPA_MUXSEL_MSB(x)

Extract the OTPA_MUXSEL_MSB bitfield from a packed word x and return it.

XS1_OTPA_MUXSEL_MSB_SET(x, v)

Pack the value (v) of the OTPA_MUXSEL_MSB bitfield into a packed word x and return the packed field.

OTPA_MISO_LSB

OTP arbiter MISO LSB.

XS1_OTPA_MISO_LSB_SHIFT

XS1_OTPA_MISO_LSB_SIZE

XS1_OTPA_MISO_LSB_MASK

XS1_OTPA_MISO_LSB(x)

Extract the OTPA_MISO_LSB bitfield from a packed word x and return it.

XS1_OTPA_MISO_LSB_SET(x, v)

Pack the value (v) of the OTPA_MISO_LSB bitfield into a packed word x and return the packed field.

OTPA_MISO_MSB

OTP arbiter MISO LSB.

XS1_OTPA_MISO_MSB_SHIFT

XS1_OTPA_MISO_MSB_SIZE

XS1_OTPA_MISO_MSB_MASK

XS1_OTPA_MISO_MSB(x)

Extract the OTPA_MISO_MSB bitfield from a packed word x and return it.

XS1_OTPA_MISO_MSB_SET(x, v)

Pack the value (v) of the OTPA_MISO_MSB bitfield into a packed word x and return the packed field.

OTPA_FLAG_IDX

OTP SBPI flag status.

XS1_OTPA_FLAG_IDX_SHIFT

XS1_OTPA_FLAG_IDX_SIZE

XS1_OTPA_FLAG_IDX_MASK

XS1_OTPA_FLAG_IDX(x)

Extract the OTPA_FLAG_IDX bitfield from a packed word x and return it.

XS1_OTPA_FLAG_IDX_SET(x, v)

Pack the value (v) of the OTPA_FLAG_IDX bitfield into a packed word x and return the packed field.

OTPA_ARB_GNT_IDX

OTP arbiter granted.

XS1_OTPA_ARB_GNT_IDX_SHIFT

XS1_OTPA_ARB_GNT_IDX_SIZE

XS1_OTPA_ARB_GNT_IDX_MASK

XS1_OTPA_ARB_GNT_IDX(x)

Extract the OTPA_ARB_GNT_IDX bitfield from a packed word x and return it.

XS1_OTPA_ARB_GNT_IDX_SET(x, v)

Pack the value (v) of the OTPA_ARB_GNT_IDX bitfield into a packed word x and return the packed field.

OTP_DAP_RFMR_MR_4

OTP DAP RFMR register MR_4 control.

XS1_OTP_DAP_RFMR_MR_4_SHIFT

XS1_OTP_DAP_RFMR_MR_4_SIZE

XS1_OTP_DAP_RFMR_MR_4_MASK

XS1_OTP_DAP_RFMR_MR_4(x)

Extract the OTP_DAP_RFMR_MR_4 bitfield from a packed word x and return it.

XS1_OTP_DAP_RFMR_MR_4_SET(x, v)

Pack the value (v) of the OTP_DAP_RFMR_MR_4 bitfield into a packed word x and return the packed field.

OTP_DAP_RFMR_MR_5

OTP DAP RFMR register MR_5 control.

XS1_OTP_DAP_RFMR_MR_5_SHIFT

XS1_OTP_DAP_RFMR_MR_5_SIZE

XS1_OTP_DAP_RFMR_MR_5_MASK

XS1_OTP_DAP_RFMR_MR_5(x)

Extract the OTP_DAP_RFMR_MR_5 bitfield from a packed word x and return it.

XS1_OTP_DAP_RFMR_MR_5_SET(x, v)

Pack the value (v) of the OTP_DAP_RFMR_MR_5 bitfield into a packed word x and return the packed field.

SYNC_CTRL0_INUSE

1 when the synchroniser is in use.

XS1_SYNC_CTRL0_INUSE_SHIFT

XS1_SYNC_CTRL0_INUSE_SIZE

XS1_SYNC_CTRL0_INUSE_MASK

XS1_SYNC_CTRL0_INUSE(x)

Extract the SYNC_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the SYNC_CTRL0_INUSE bitfield into a packed word x and return the packed field.

SYNC_CTRL0_MSYNCED

1 when the master of this synchroniser has msynced on it.

XS1_SYNC_CTRL0_MSYNCED_SHIFT

XS1_SYNC_CTRL0_MSYNCED_SIZE

XS1_SYNC_CTRL0_MSYNCED_MASK

XS1_SYNC_CTRL0_MSYNCED(x)

Extract the SYNC_CTRL0_MSYNCED bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_MSYNCED_SET(x, v)

Pack the value (v) of the SYNC_CTRL0_MSYNCED bitfield into a packed word x and return the packed field.

SYNC_CTRL0_JOIN

1 when the synchroniser will free the threads after synchronisation.

0 otherwise.

XS1_SYNC_CTRL0_JOIN_SHIFT

XS1_SYNC_CTRL0_JOIN_SIZE

XS1_SYNC_CTRL0_JOIN_MASK

XS1_SYNC_CTRL0_JOIN(x)

Extract the SYNC_CTRL0_JOIN bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_JOIN_SET(x, v)

Pack the value (v) of the SYNC_CTRL0_JOIN bitfield into a packed word x and return the packed field.

SYNC_CTRL0_MASTER

When synchroniser is in use it is the ID of the master thread.

0 when not in use.

XS1_SYNC_CTRL0_MASTER_SHIFT

XS1_SYNC_CTRL0_MASTER_SIZE

XS1_SYNC_CTRL0_MASTER_MASK

XS1_SYNC_CTRL0_MASTER(x)

Extract the SYNC_CTRL0_MASTER bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_MASTER_SET(x, v)

Pack the value (v) of the SYNC_CTRL0_MASTER bitfield into a packed word x and return the packed field.

SYNC_TBV0_SLAVES

1 bit for each of the threads.

When 1 indicates that the corresponding thread is attached to the synchroniser.

XS1_SYNC_TBV0_SLAVES_SHIFT

XS1_SYNC_TBV0_SLAVES_SIZE

XS1_SYNC_TBV0_SLAVES_MASK

XS1_SYNC_TBV0_SLAVES(x)

Extract the SYNC_TBV0_SLAVES bitfield from a packed word x and return it.

XS1_SYNC_TBV0_SLAVES_SET(x, v)

Pack the value (v) of the SYNC_TBV0_SLAVES bitfield into a packed word x and return the packed field.

LOCK_CTRL0_INUSE

1 when the lock is in use.

XS1_LOCK_CTRL0_INUSE_SHIFT

XS1_LOCK_CTRL0_INUSE_SIZE

XS1_LOCK_CTRL0_INUSE_MASK

XS1_LOCK_CTRL0_INUSE(x)

Extract the LOCK_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_LOCK_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the LOCK_CTRL0_INUSE bitfield into a packed word x and return the packed field.

LOCK_CTRL0_OWNT_V

Indicates that the lock’s owner is known.

XS1_LOCK_CTRL0_OWNT_V_SHIFT

XS1_LOCK_CTRL0_OWNT_V_SIZE

XS1_LOCK_CTRL0_OWNT_V_MASK

XS1_LOCK_CTRL0_OWNT_V(x)

Extract the LOCK_CTRL0_OWNT_V bitfield from a packed word x and return it.

XS1_LOCK_CTRL0_OWNT_V_SET(x, v)

Pack the value (v) of the LOCK_CTRL0_OWNT_V bitfield into a packed word x and return the packed field.

LOCK_CTRL0_OWNT

When OWNT_V is true then this is the ID of the thread currently holding the lock.

XS1_LOCK_CTRL0_OWNT_SHIFT

XS1_LOCK_CTRL0_OWNT_SIZE

XS1_LOCK_CTRL0_OWNT_MASK

XS1_LOCK_CTRL0_OWNT(x)

Extract the LOCK_CTRL0_OWNT bitfield from a packed word x and return it.

XS1_LOCK_CTRL0_OWNT_SET(x, v)

Pack the value (v) of the LOCK_CTRL0_OWNT bitfield into a packed word x and return the packed field.

LOCK_TBV0_WAITING

1 bit for each of the threads.

When 1 indicates that the corresponding thread is waiting for the lock.

XS1_LOCK_TBV0_WAITING_SHIFT

XS1_LOCK_TBV0_WAITING_SIZE

XS1_LOCK_TBV0_WAITING_MASK

XS1_LOCK_TBV0_WAITING(x)

Extract the LOCK_TBV0_WAITING bitfield from a packed word x and return it.

XS1_LOCK_TBV0_WAITING_SET(x, v)

Pack the value (v) of the LOCK_TBV0_WAITING bitfield into a packed word x and return the packed field.

MMAP_CTRL0_INUSE

XS1_MMAP_CTRL0_INUSE_SHIFT

XS1_MMAP_CTRL0_INUSE_SIZE

XS1_MMAP_CTRL0_INUSE_MASK

XS1_MMAP_CTRL0_INUSE(x)

Extract the MMAP_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_INUSE bitfield into a packed word x and return the packed field.

MMAP_CTRL0_RO

XS1_MMAP_CTRL0_RO_SHIFT

XS1_MMAP_CTRL0_RO_SIZE

XS1_MMAP_CTRL0_RO_MASK

XS1_MMAP_CTRL0_RO(x)

Extract the MMAP_CTRL0_RO bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_RO_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_RO bitfield into a packed word x and return the packed field.

MMAP_CTRL0_LOCK

XS1_MMAP_CTRL0_LOCK_SHIFT

XS1_MMAP_CTRL0_LOCK_SIZE

XS1_MMAP_CTRL0_LOCK_MASK

XS1_MMAP_CTRL0_LOCK(x)

Extract the MMAP_CTRL0_LOCK bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_LOCK_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_LOCK bitfield into a packed word x and return the packed field.

MMAP_CTRL0_GLOBAL

XS1_MMAP_CTRL0_GLOBAL_SHIFT

XS1_MMAP_CTRL0_GLOBAL_SIZE

XS1_MMAP_CTRL0_GLOBAL_MASK

XS1_MMAP_CTRL0_GLOBAL(x)

Extract the MMAP_CTRL0_GLOBAL bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_GLOBAL_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_GLOBAL bitfield into a packed word x and return the packed field.

MMAP_CTRL0_ASID

XS1_MMAP_CTRL0_ASID_SHIFT

XS1_MMAP_CTRL0_ASID_SIZE

XS1_MMAP_CTRL0_ASID_MASK

XS1_MMAP_CTRL0_ASID(x)

Extract the MMAP_CTRL0_ASID bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_ASID_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_ASID bitfield into a packed word x and return the packed field.

MMAP_CTRL0_LENGTH

XS1_MMAP_CTRL0_LENGTH_SHIFT

XS1_MMAP_CTRL0_LENGTH_SIZE

XS1_MMAP_CTRL0_LENGTH_MASK

XS1_MMAP_CTRL0_LENGTH(x)

Extract the MMAP_CTRL0_LENGTH bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_LENGTH_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_LENGTH bitfield into a packed word x and return the packed field.

MMAP_CTRL0_PHY_ADDR

XS1_MMAP_CTRL0_PHY_ADDR_SHIFT

XS1_MMAP_CTRL0_PHY_ADDR_SIZE

XS1_MMAP_CTRL0_PHY_ADDR_MASK

XS1_MMAP_CTRL0_PHY_ADDR(x)

Extract the MMAP_CTRL0_PHY_ADDR bitfield from a packed word x and return it.

XS1_MMAP_CTRL0_PHY_ADDR_SET(x, v)

Pack the value (v) of the MMAP_CTRL0_PHY_ADDR bitfield into a packed word x and return the packed field.

MMAP_CTRL1_THREADS_EN

XS1_MMAP_CTRL1_THREADS_EN_SHIFT

XS1_MMAP_CTRL1_THREADS_EN_SIZE

XS1_MMAP_CTRL1_THREADS_EN_MASK

XS1_MMAP_CTRL1_THREADS_EN(x)

Extract the MMAP_CTRL1_THREADS_EN bitfield from a packed word x and return it.

XS1_MMAP_CTRL1_THREADS_EN_SET(x, v)

Pack the value (v) of the MMAP_CTRL1_THREADS_EN bitfield into a packed word x and return the packed field.

MMAP_CTRL1_VIRT_ADDR

XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT

XS1_MMAP_CTRL1_VIRT_ADDR_SIZE

XS1_MMAP_CTRL1_VIRT_ADDR_MASK

XS1_MMAP_CTRL1_VIRT_ADDR(x)

Extract the MMAP_CTRL1_VIRT_ADDR bitfield from a packed word x and return it.

XS1_MMAP_CTRL1_VIRT_ADDR_SET(x, v)

Pack the value (v) of the MMAP_CTRL1_VIRT_ADDR bitfield into a packed word x and return the packed field.

MMAP_CTRL2_AGE

XS1_MMAP_CTRL2_AGE_SHIFT

XS1_MMAP_CTRL2_AGE_SIZE

XS1_MMAP_CTRL2_AGE_MASK

XS1_MMAP_CTRL2_AGE(x)

Extract the MMAP_CTRL2_AGE bitfield from a packed word x and return it.

XS1_MMAP_CTRL2_AGE_SET(x, v)

Pack the value (v) of the MMAP_CTRL2_AGE bitfield into a packed word x and return the packed field.

MMAP_CTRL2_OWNER

XS1_MMAP_CTRL2_OWNER_SHIFT

XS1_MMAP_CTRL2_OWNER_SIZE

XS1_MMAP_CTRL2_OWNER_MASK

XS1_MMAP_CTRL2_OWNER(x)

Extract the MMAP_CTRL2_OWNER bitfield from a packed word x and return it.

XS1_MMAP_CTRL2_OWNER_SET(x, v)

Pack the value (v) of the MMAP_CTRL2_OWNER bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_INUSE

1 when the channel end is in use.

XS1_CHANEND_CTRL0_INUSE_SHIFT

XS1_CHANEND_CTRL0_INUSE_SIZE

XS1_CHANEND_CTRL0_INUSE_MASK

XS1_CHANEND_CTRL0_INUSE(x)

Extract the CHANEND_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_INUSE bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_IE_MODE

0 when the channel end will cause events, 1 when in use and it will raise interrupts.

XS1_CHANEND_CTRL0_IE_MODE_SHIFT

XS1_CHANEND_CTRL0_IE_MODE_SIZE

XS1_CHANEND_CTRL0_IE_MODE_MASK

XS1_CHANEND_CTRL0_IE_MODE(x)

Extract the CHANEND_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_IE_MODE_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_IE_ENABLED

1 when events or interrupts are enabled on the channel end.

XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT

XS1_CHANEND_CTRL0_IE_ENABLED_SIZE

XS1_CHANEND_CTRL0_IE_ENABLED_MASK

XS1_CHANEND_CTRL0_IE_ENABLED(x)

Extract the CHANEND_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_IE_ENABLED_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_IN_READY

1 when in use and there is sufficient data in the channel end for a token to be input by a thread.

XS1_CHANEND_CTRL0_IN_READY_SHIFT

XS1_CHANEND_CTRL0_IN_READY_SIZE

XS1_CHANEND_CTRL0_IN_READY_MASK

XS1_CHANEND_CTRL0_IN_READY(x)

Extract the CHANEND_CTRL0_IN_READY bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_IN_READY_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_IN_READY bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_IN_WAITING

1 when the input thread is waiting either for data or for an event.

XS1_CHANEND_CTRL0_IN_WAITING_SHIFT

XS1_CHANEND_CTRL0_IN_WAITING_SIZE

XS1_CHANEND_CTRL0_IN_WAITING_MASK

XS1_CHANEND_CTRL0_IN_WAITING(x)

Extract the CHANEND_CTRL0_IN_WAITING bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_IN_WAITING_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_IN_WAITING bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_OUT_READY

1 when in use and either not connected or there is sufficient room in the target channel end for a token to be ouptut by a thread.

Will be 0 when requesting a link but not yet connected.

XS1_CHANEND_CTRL0_OUT_READY_SHIFT

XS1_CHANEND_CTRL0_OUT_READY_SIZE

XS1_CHANEND_CTRL0_OUT_READY_MASK

XS1_CHANEND_CTRL0_OUT_READY(x)

Extract the CHANEND_CTRL0_OUT_READY bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_OUT_READY_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_OUT_READY bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_OUT_WAITING

1 when there is a thread waiting to write data to the channel end.

XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT

XS1_CHANEND_CTRL0_OUT_WAITING_SIZE

XS1_CHANEND_CTRL0_OUT_WAITING_MASK

XS1_CHANEND_CTRL0_OUT_WAITING(x)

Extract the CHANEND_CTRL0_OUT_WAITING bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_OUT_WAITING_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_OUT_WAITING bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_EV_VALID

1 when the Environment Vector is valid.

When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_CHANEND_CTRL0_EV_VALID_SHIFT

XS1_CHANEND_CTRL0_EV_VALID_SIZE

XS1_CHANEND_CTRL0_EV_VALID_MASK

XS1_CHANEND_CTRL0_EV_VALID(x)

Extract the CHANEND_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_EV_VALID_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_IN_T_NUM

Number of the input thread waiting for data or an event on this channel end.

XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT

XS1_CHANEND_CTRL0_IN_T_NUM_SIZE

XS1_CHANEND_CTRL0_IN_T_NUM_MASK

XS1_CHANEND_CTRL0_IN_T_NUM(x)

Extract the CHANEND_CTRL0_IN_T_NUM bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_IN_T_NUM_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_IN_T_NUM bitfield into a packed word x and return the packed field.

CHANEND_CTRL0_OUT_T_NUM

Number of the last thread to attempt to write data to this channel end.

XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT

XS1_CHANEND_CTRL0_OUT_T_NUM_SIZE

XS1_CHANEND_CTRL0_OUT_T_NUM_MASK

XS1_CHANEND_CTRL0_OUT_T_NUM(x)

Extract the CHANEND_CTRL0_OUT_T_NUM bitfield from a packed word x and return it.

XS1_CHANEND_CTRL0_OUT_T_NUM_SET(x, v)

Pack the value (v) of the CHANEND_CTRL0_OUT_T_NUM bitfield into a packed word x and return the packed field.

CLKBLK_CTRL0_INUSE

1 when the clock source is in use.

XS1_CLKBLK_CTRL0_INUSE_SHIFT

XS1_CLKBLK_CTRL0_INUSE_SIZE

XS1_CLKBLK_CTRL0_INUSE_MASK

XS1_CLKBLK_CTRL0_INUSE(x)

Extract the CLKBLK_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL0_INUSE bitfield into a packed word x and return the packed field.

CLKBLK_CTRL0_STARTED

1 when the clock source has been started.

XS1_CLKBLK_CTRL0_STARTED_SHIFT

XS1_CLKBLK_CTRL0_STARTED_SIZE

XS1_CLKBLK_CTRL0_STARTED_MASK

XS1_CLKBLK_CTRL0_STARTED(x)

Extract the CLKBLK_CTRL0_STARTED bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL0_STARTED_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL0_STARTED bitfield into a packed word x and return the packed field.

CLKBLK_CTRL0_STOPPING

1 when the clock source is in the process of stopping.

XS1_CLKBLK_CTRL0_STOPPING_SHIFT

XS1_CLKBLK_CTRL0_STOPPING_SIZE

XS1_CLKBLK_CTRL0_STOPPING_MASK

XS1_CLKBLK_CTRL0_STOPPING(x)

Extract the CLKBLK_CTRL0_STOPPING bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL0_STOPPING_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL0_STOPPING bitfield into a packed word x and return the packed field.

CLKBLK_CTRL0_T_WAITING

1 when there is a thread waiting for synchronisation with the clock block.

XS1_CLKBLK_CTRL0_T_WAITING_SHIFT

XS1_CLKBLK_CTRL0_T_WAITING_SIZE

XS1_CLKBLK_CTRL0_T_WAITING_MASK

XS1_CLKBLK_CTRL0_T_WAITING(x)

Extract the CLKBLK_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL0_T_WAITING_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

CLKBLK_CTRL0_T_NUM

Number of the thread waiting for the clock block.

XS1_CLKBLK_CTRL0_T_NUM_SHIFT

XS1_CLKBLK_CTRL0_T_NUM_SIZE

XS1_CLKBLK_CTRL0_T_NUM_MASK

XS1_CLKBLK_CTRL0_T_NUM(x)

Extract the CLKBLK_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL0_T_NUM_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

CLKBLK_CTRL1_FALL_DELAY

Falling edge delay counter.

XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT

XS1_CLKBLK_CTRL1_FALL_DELAY_SIZE

XS1_CLKBLK_CTRL1_FALL_DELAY_MASK

XS1_CLKBLK_CTRL1_FALL_DELAY(x)

Extract the CLKBLK_CTRL1_FALL_DELAY bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL1_FALL_DELAY_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL1_FALL_DELAY bitfield into a packed word x and return the packed field.

CLKBLK_CTRL1_RISE_DELAY

Rising edge delay counter.

XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT

XS1_CLKBLK_CTRL1_RISE_DELAY_SIZE

XS1_CLKBLK_CTRL1_RISE_DELAY_MASK

XS1_CLKBLK_CTRL1_RISE_DELAY(x)

Extract the CLKBLK_CTRL1_RISE_DELAY bitfield from a packed word x and return it.

XS1_CLKBLK_CTRL1_RISE_DELAY_SET(x, v)

Pack the value (v) of the CLKBLK_CTRL1_RISE_DELAY bitfield into a packed word x and return the packed field.

COPROC_CTRL0_INUSE

1 when the coprocessor is in use.

XS1_COPROC_CTRL0_INUSE_SHIFT

XS1_COPROC_CTRL0_INUSE_SIZE

XS1_COPROC_CTRL0_INUSE_MASK

XS1_COPROC_CTRL0_INUSE(x)

Extract the COPROC_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_COPROC_CTRL0_INUSE_SET(x, v)

Pack the value (v) of the COPROC_CTRL0_INUSE bitfield into a packed word x and return the packed field.

COPROC_CTRL0_OWNT_V

Indicates that the coprocessor’s owner is known.

XS1_COPROC_CTRL0_OWNT_V_SHIFT

XS1_COPROC_CTRL0_OWNT_V_SIZE

XS1_COPROC_CTRL0_OWNT_V_MASK

XS1_COPROC_CTRL0_OWNT_V(x)

Extract the COPROC_CTRL0_OWNT_V bitfield from a packed word x and return it.

XS1_COPROC_CTRL0_OWNT_V_SET(x, v)

Pack the value (v) of the COPROC_CTRL0_OWNT_V bitfield into a packed word x and return the packed field.

COPROC_CTRL0_OWNT

When OWNT_V is true then this is the ID of the thread currently using the coprocessor.

XS1_COPROC_CTRL0_OWNT_SHIFT

XS1_COPROC_CTRL0_OWNT_SIZE

XS1_COPROC_CTRL0_OWNT_MASK

XS1_COPROC_CTRL0_OWNT(x)

Extract the COPROC_CTRL0_OWNT bitfield from a packed word x and return it.

XS1_COPROC_CTRL0_OWNT_SET(x, v)

Pack the value (v) of the COPROC_CTRL0_OWNT bitfield into a packed word x and return the packed field.

COPROC_TBV0_WAITING

1 bit for each of the threads.

When 1 indicates that the corresponding thread is waiting for the coprocessor.

XS1_COPROC_TBV0_WAITING_SHIFT

XS1_COPROC_TBV0_WAITING_SIZE

XS1_COPROC_TBV0_WAITING_MASK

XS1_COPROC_TBV0_WAITING(x)

Extract the COPROC_TBV0_WAITING bitfield from a packed word x and return it.

XS1_COPROC_TBV0_WAITING_SET(x, v)

Pack the value (v) of the COPROC_TBV0_WAITING bitfield into a packed word x and return the packed field.

RES_ID_TYPE

The type of a resource.

XS1_RES_ID_TYPE_SHIFT

XS1_RES_ID_TYPE_SIZE

XS1_RES_ID_TYPE_MASK

XS1_RES_ID_TYPE(x)

Extract the RES_ID_TYPE bitfield from a packed word x and return it.

XS1_RES_ID_TYPE_SET(x, v)

Pack the value (v) of the RES_ID_TYPE bitfield into a packed word x and return the packed field.

RES_ID_REGID

The register ID for resource GETPS / SETPS accesses.

Must be 0 otherwise.

XS1_RES_ID_REGID_SHIFT

XS1_RES_ID_REGID_SIZE

XS1_RES_ID_REGID_MASK

XS1_RES_ID_REGID(x)

Extract the RES_ID_REGID bitfield from a packed word x and return it.

XS1_RES_ID_REGID_SET(x, v)

Pack the value (v) of the RES_ID_REGID bitfield into a packed word x and return the packed field.

RES_ID_RESNUM

The resource number of a resource.

XS1_RES_ID_RESNUM_SHIFT

XS1_RES_ID_RESNUM_SIZE

XS1_RES_ID_RESNUM_MASK

XS1_RES_ID_RESNUM(x)

Extract the RES_ID_RESNUM bitfield from a packed word x and return it.

XS1_RES_ID_RESNUM_SET(x, v)

Pack the value (v) of the RES_ID_RESNUM bitfield into a packed word x and return the packed field.

RES_ID_PORTWIDTH

The size of a port - zero for all resources which are not ports.

XS1_RES_ID_PORTWIDTH_SHIFT

XS1_RES_ID_PORTWIDTH_SIZE

XS1_RES_ID_PORTWIDTH_MASK

XS1_RES_ID_PORTWIDTH(x)

Extract the RES_ID_PORTWIDTH bitfield from a packed word x and return it.

XS1_RES_ID_PORTWIDTH_SET(x, v)

Pack the value (v) of the RES_ID_PORTWIDTH bitfield into a packed word x and return the packed field.

CHAN_ID_CHANNUM

The channel end number.

XS1_CHAN_ID_CHANNUM_SHIFT

XS1_CHAN_ID_CHANNUM_SIZE

XS1_CHAN_ID_CHANNUM_MASK

XS1_CHAN_ID_CHANNUM(x)

Extract the CHAN_ID_CHANNUM bitfield from a packed word x and return it.

XS1_CHAN_ID_CHANNUM_SET(x, v)

Pack the value (v) of the CHAN_ID_CHANNUM bitfield into a packed word x and return the packed field.

CHAN_ID_PROCESSOR

The processor to which this resource belongs.

XS1_CHAN_ID_PROCESSOR_SHIFT

XS1_CHAN_ID_PROCESSOR_SIZE

XS1_CHAN_ID_PROCESSOR_MASK

XS1_CHAN_ID_PROCESSOR(x)

Extract the CHAN_ID_PROCESSOR bitfield from a packed word x and return it.

XS1_CHAN_ID_PROCESSOR_SET(x, v)

Pack the value (v) of the CHAN_ID_PROCESSOR bitfield into a packed word x and return the packed field.

CHAN_ID_NODE

The node in which this resource is found.

XS1_CHAN_ID_NODE_SHIFT

XS1_CHAN_ID_NODE_SIZE

XS1_CHAN_ID_NODE_MASK

XS1_CHAN_ID_NODE(x)

Extract the CHAN_ID_NODE bitfield from a packed word x and return it.

XS1_CHAN_ID_NODE_SET(x, v)

Pack the value (v) of the CHAN_ID_NODE bitfield into a packed word x and return the packed field.

HEADER_1BYTE_CHANNUM

The channel end number.

XS1_HEADER_1BYTE_CHANNUM_SHIFT

XS1_HEADER_1BYTE_CHANNUM_SIZE

XS1_HEADER_1BYTE_CHANNUM_MASK

XS1_HEADER_1BYTE_CHANNUM(x)

Extract the HEADER_1BYTE_CHANNUM bitfield from a packed word x and return it.

XS1_HEADER_1BYTE_CHANNUM_SET(x, v)

Pack the value (v) of the HEADER_1BYTE_CHANNUM bitfield into a packed word x and return the packed field.

HEADER_1BYTE_PROCESSOR

The processor to which this resource belongs.

XS1_HEADER_1BYTE_PROCESSOR_SHIFT

XS1_HEADER_1BYTE_PROCESSOR_SIZE

XS1_HEADER_1BYTE_PROCESSOR_MASK

XS1_HEADER_1BYTE_PROCESSOR(x)

Extract the HEADER_1BYTE_PROCESSOR bitfield from a packed word x and return it.

XS1_HEADER_1BYTE_PROCESSOR_SET(x, v)

Pack the value (v) of the HEADER_1BYTE_PROCESSOR bitfield into a packed word x and return the packed field.

HEADER_1BYTE_NODE

The node in which this resource is found.

XS1_HEADER_1BYTE_NODE_SHIFT

XS1_HEADER_1BYTE_NODE_SIZE

XS1_HEADER_1BYTE_NODE_MASK

XS1_HEADER_1BYTE_NODE(x)

Extract the HEADER_1BYTE_NODE bitfield from a packed word x and return it.

XS1_HEADER_1BYTE_NODE_SET(x, v)

Pack the value (v) of the HEADER_1BYTE_NODE bitfield into a packed word x and return the packed field.

HEADER_3BYTE_CHANNUM

The channel end number.

XS1_HEADER_3BYTE_CHANNUM_SHIFT

XS1_HEADER_3BYTE_CHANNUM_SIZE

XS1_HEADER_3BYTE_CHANNUM_MASK

XS1_HEADER_3BYTE_CHANNUM(x)

Extract the HEADER_3BYTE_CHANNUM bitfield from a packed word x and return it.

XS1_HEADER_3BYTE_CHANNUM_SET(x, v)

Pack the value (v) of the HEADER_3BYTE_CHANNUM bitfield into a packed word x and return the packed field.

HEADER_3BYTE_PROCESSOR

The processor to which this resource belongs.

XS1_HEADER_3BYTE_PROCESSOR_SHIFT

XS1_HEADER_3BYTE_PROCESSOR_SIZE

XS1_HEADER_3BYTE_PROCESSOR_MASK

XS1_HEADER_3BYTE_PROCESSOR(x)

Extract the HEADER_3BYTE_PROCESSOR bitfield from a packed word x and return it.

XS1_HEADER_3BYTE_PROCESSOR_SET(x, v)

Pack the value (v) of the HEADER_3BYTE_PROCESSOR bitfield into a packed word x and return the packed field.

HEADER_3BYTE_NODE

The node in which this resource is found.

XS1_HEADER_3BYTE_NODE_SHIFT

XS1_HEADER_3BYTE_NODE_SIZE

XS1_HEADER_3BYTE_NODE_MASK

XS1_HEADER_3BYTE_NODE(x)

Extract the HEADER_3BYTE_NODE bitfield from a packed word x and return it.

XS1_HEADER_3BYTE_NODE_SET(x, v)

Pack the value (v) of the HEADER_3BYTE_NODE bitfield into a packed word x and return the packed field.

SETCTRL_MODE

Select mode to change.

XS1_SETC_MODE_SHIFT

XS1_SETC_MODE_SIZE

XS1_SETC_MODE_MASK

XS1_SETC_MODE(x)

Extract the SETCTRL_MODE bitfield from a packed word x and return it.

XS1_SETC_MODE_SET(x, v)

Pack the value (v) of the SETCTRL_MODE bitfield into a packed word x and return the packed field.

SETCTRL_VALUE

Value for mode change.

XS1_SETC_VALUE_SHIFT

XS1_SETC_VALUE_SIZE

XS1_SETC_VALUE_MASK

XS1_SETC_VALUE(x)

Extract the SETCTRL_VALUE bitfield from a packed word x and return it.

XS1_SETC_VALUE_SET(x, v)

Pack the value (v) of the SETCTRL_VALUE bitfield into a packed word x and return the packed field.

SETCTRL_LMODE

Long mode bits.

XS1_SETC_LMODE_SHIFT

XS1_SETC_LMODE_SIZE

XS1_SETC_LMODE_MASK

XS1_SETC_LMODE(x)

Extract the SETCTRL_LMODE bitfield from a packed word x and return it.

XS1_SETC_LMODE_SET(x, v)

Pack the value (v) of the SETCTRL_LMODE bitfield into a packed word x and return the packed field.

MMAPCTRL_MODE

Select mode to change.

XS1_SETC_MMAP_MODE_SHIFT

XS1_SETC_MMAP_MODE_SIZE

XS1_SETC_MMAP_MODE_MASK

XS1_SETC_MMAP_MODE(x)

Extract the MMAPCTRL_MODE bitfield from a packed word x and return it.

XS1_SETC_MMAP_MODE_SET(x, v)

Pack the value (v) of the MMAPCTRL_MODE bitfield into a packed word x and return the packed field.

MMAPCTRL_VALUE

Value for mode change.

XS1_SETC_MMAP_VALUE_SHIFT

XS1_SETC_MMAP_VALUE_SIZE

XS1_SETC_MMAP_VALUE_MASK

XS1_SETC_MMAP_VALUE(x)

Extract the MMAPCTRL_VALUE bitfield from a packed word x and return it.

XS1_SETC_MMAP_VALUE_SET(x, v)

Pack the value (v) of the MMAPCTRL_VALUE bitfield into a packed word x and return the packed field.

DBG_INT_REQ_DBG

Request a debug interrupt on the processor.

XS1_DBG_INT_REQ_DBG_SHIFT

XS1_DBG_INT_REQ_DBG_SIZE

XS1_DBG_INT_REQ_DBG_MASK

XS1_DBG_INT_REQ_DBG(x)

Extract the DBG_INT_REQ_DBG bitfield from a packed word x and return it.

XS1_DBG_INT_REQ_DBG_SET(x, v)

Pack the value (v) of the DBG_INT_REQ_DBG bitfield into a packed word x and return the packed field.

DBG_INT_IN_DBG

1 when the processor is in debug mode.

XS1_DBG_INT_IN_DBG_SHIFT

XS1_DBG_INT_IN_DBG_SIZE

XS1_DBG_INT_IN_DBG_MASK

XS1_DBG_INT_IN_DBG(x)

Extract the DBG_INT_IN_DBG bitfield from a packed word x and return it.

XS1_DBG_INT_IN_DBG_SET(x, v)

Pack the value (v) of the DBG_INT_IN_DBG bitfield into a packed word x and return the packed field.

DBG_CTRL_PSWITCH_RO_EXT

When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch

XS1_DBG_CTRL_PSWITCH_RO_EXT_SHIFT

XS1_DBG_CTRL_PSWITCH_RO_EXT_SIZE

XS1_DBG_CTRL_PSWITCH_RO_EXT_MASK

XS1_DBG_CTRL_PSWITCH_RO_EXT(x)

Extract the DBG_CTRL_PSWITCH_RO_EXT bitfield from a packed word x and return it.

XS1_DBG_CTRL_PSWITCH_RO_EXT_SET(x, v)

Pack the value (v) of the DBG_CTRL_PSWITCH_RO_EXT bitfield into a packed word x and return the packed field.

DBG_CTRL_PSWITCH_RO

When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch, XCore(PS_DBG_Scratch) and JTAG

XS1_DBG_CTRL_PSWITCH_RO_SHIFT

XS1_DBG_CTRL_PSWITCH_RO_SIZE

XS1_DBG_CTRL_PSWITCH_RO_MASK

XS1_DBG_CTRL_PSWITCH_RO(x)

Extract the DBG_CTRL_PSWITCH_RO bitfield from a packed word x and return it.

XS1_DBG_CTRL_PSWITCH_RO_SET(x, v)

Pack the value (v) of the DBG_CTRL_PSWITCH_RO bitfield into a packed word x and return the packed field.

DEVICE_ID0_VERSION

XCore version.

XS1_DEVICE_ID0_VERSION_SHIFT

XS1_DEVICE_ID0_VERSION_SIZE

XS1_DEVICE_ID0_VERSION_MASK

XS1_DEVICE_ID0_VERSION(x)

Extract the DEVICE_ID0_VERSION bitfield from a packed word x and return it.

XS1_DEVICE_ID0_VERSION_SET(x, v)

Pack the value (v) of the DEVICE_ID0_VERSION bitfield into a packed word x and return the packed field.

DEVICE_ID0_REVISION

XCore revision.

XS1_DEVICE_ID0_REVISION_SHIFT

XS1_DEVICE_ID0_REVISION_SIZE

XS1_DEVICE_ID0_REVISION_MASK

XS1_DEVICE_ID0_REVISION(x)

Extract the DEVICE_ID0_REVISION bitfield from a packed word x and return it.

XS1_DEVICE_ID0_REVISION_SET(x, v)

Pack the value (v) of the DEVICE_ID0_REVISION bitfield into a packed word x and return the packed field.

DEVICE_ID0_NODE

Number of the node in which this XCore is located.

XS1_DEVICE_ID0_NODE_SHIFT

XS1_DEVICE_ID0_NODE_SIZE

XS1_DEVICE_ID0_NODE_MASK

XS1_DEVICE_ID0_NODE(x)

Extract the DEVICE_ID0_NODE bitfield from a packed word x and return it.

XS1_DEVICE_ID0_NODE_SET(x, v)

Pack the value (v) of the DEVICE_ID0_NODE bitfield into a packed word x and return the packed field.

DEVICE_ID0_PID

Processor ID of this XCore.

XS1_DEVICE_ID0_PID_SHIFT

XS1_DEVICE_ID0_PID_SIZE

XS1_DEVICE_ID0_PID_MASK

XS1_DEVICE_ID0_PID(x)

Extract the DEVICE_ID0_PID bitfield from a packed word x and return it.

XS1_DEVICE_ID0_PID_SET(x, v)

Pack the value (v) of the DEVICE_ID0_PID bitfield into a packed word x and return the packed field.

DEVICE_ID1_NUM_THREADS

Number of threads.

XS1_DEVICE_ID1_NUM_THREADS_SHIFT

XS1_DEVICE_ID1_NUM_THREADS_SIZE

XS1_DEVICE_ID1_NUM_THREADS_MASK

XS1_DEVICE_ID1_NUM_THREADS(x)

Extract the DEVICE_ID1_NUM_THREADS bitfield from a packed word x and return it.

XS1_DEVICE_ID1_NUM_THREADS_SET(x, v)

Pack the value (v) of the DEVICE_ID1_NUM_THREADS bitfield into a packed word x and return the packed field.

DEVICE_ID1_NUM_SYNCS

Number of synchronisers.

XS1_DEVICE_ID1_NUM_SYNCS_SHIFT

XS1_DEVICE_ID1_NUM_SYNCS_SIZE

XS1_DEVICE_ID1_NUM_SYNCS_MASK

XS1_DEVICE_ID1_NUM_SYNCS(x)

Extract the DEVICE_ID1_NUM_SYNCS bitfield from a packed word x and return it.

XS1_DEVICE_ID1_NUM_SYNCS_SET(x, v)

Pack the value (v) of the DEVICE_ID1_NUM_SYNCS bitfield into a packed word x and return the packed field.

DEVICE_ID1_NUM_LOCKS

Number of the locks.

XS1_DEVICE_ID1_NUM_LOCKS_SHIFT

XS1_DEVICE_ID1_NUM_LOCKS_SIZE

XS1_DEVICE_ID1_NUM_LOCKS_MASK

XS1_DEVICE_ID1_NUM_LOCKS(x)

Extract the DEVICE_ID1_NUM_LOCKS bitfield from a packed word x and return it.

XS1_DEVICE_ID1_NUM_LOCKS_SET(x, v)

Pack the value (v) of the DEVICE_ID1_NUM_LOCKS bitfield into a packed word x and return the packed field.

DEVICE_ID1_NUM_CHANENDS

Number of channel ends.

XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT

XS1_DEVICE_ID1_NUM_CHANENDS_SIZE

XS1_DEVICE_ID1_NUM_CHANENDS_MASK

XS1_DEVICE_ID1_NUM_CHANENDS(x)

Extract the DEVICE_ID1_NUM_CHANENDS bitfield from a packed word x and return it.

XS1_DEVICE_ID1_NUM_CHANENDS_SET(x, v)

Pack the value (v) of the DEVICE_ID1_NUM_CHANENDS bitfield into a packed word x and return the packed field.

DEVICE_ID2_NUM_TIMERS

Number of timers.

XS1_DEVICE_ID2_NUM_TIMERS_SHIFT

XS1_DEVICE_ID2_NUM_TIMERS_SIZE

XS1_DEVICE_ID2_NUM_TIMERS_MASK

XS1_DEVICE_ID2_NUM_TIMERS(x)

Extract the DEVICE_ID2_NUM_TIMERS bitfield from a packed word x and return it.

XS1_DEVICE_ID2_NUM_TIMERS_SET(x, v)

Pack the value (v) of the DEVICE_ID2_NUM_TIMERS bitfield into a packed word x and return the packed field.

DEVICE_ID2_NUM_CLKBLKS

Number of clock blocks.

XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT

XS1_DEVICE_ID2_NUM_CLKBLKS_SIZE

XS1_DEVICE_ID2_NUM_CLKBLKS_MASK

XS1_DEVICE_ID2_NUM_CLKBLKS(x)

Extract the DEVICE_ID2_NUM_CLKBLKS bitfield from a packed word x and return it.

XS1_DEVICE_ID2_NUM_CLKBLKS_SET(x, v)

Pack the value (v) of the DEVICE_ID2_NUM_CLKBLKS bitfield into a packed word x and return the packed field.

JUNK

1 when the current packet is considered junk and will be thrown away.

XS1_JUNK_SHIFT

XS1_JUNK_SIZE

XS1_JUNK_MASK

XS1_JUNK(x)

Extract the JUNK bitfield from a packed word x and return it.

XS1_JUNK_SET(x, v)

Pack the value (v) of the JUNK bitfield into a packed word x and return the packed field.

NETWORK

Network ID for the PLink.

XS1_NETWORK_SHIFT

XS1_NETWORK_SIZE

XS1_NETWORK_MASK

XS1_NETWORK(x)

Extract the NETWORK bitfield from a packed word x and return it.

XS1_NETWORK_SET(x, v)

Pack the value (v) of the NETWORK bitfield into a packed word x and return the packed field.

SRC_TARGET_ID

Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status.

XS1_SRC_TARGET_ID_SHIFT

XS1_SRC_TARGET_ID_SIZE

XS1_SRC_TARGET_ID_MASK

XS1_SRC_TARGET_ID(x)

Extract the SRC_TARGET_ID bitfield from a packed word x and return it.

XS1_SRC_TARGET_ID_SET(x, v)

Pack the value (v) of the SRC_TARGET_ID bitfield into a packed word x and return the packed field.

SRC_TARGET_TYPE

00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle.

XS1_SRC_TARGET_TYPE_SHIFT

XS1_SRC_TARGET_TYPE_SIZE

XS1_SRC_TARGET_TYPE_MASK

XS1_SRC_TARGET_TYPE(x)

Extract the SRC_TARGET_TYPE bitfield from a packed word x and return it.

XS1_SRC_TARGET_TYPE_SET(x, v)

Pack the value (v) of the SRC_TARGET_TYPE bitfield into a packed word x and return the packed field.

SS_DEVICE_ID0_VERSION

SSwitch version.

XS1_SS_DEVICE_ID0_VERSION_SHIFT

XS1_SS_DEVICE_ID0_VERSION_SIZE

XS1_SS_DEVICE_ID0_VERSION_MASK

XS1_SS_DEVICE_ID0_VERSION(x)

Extract the SS_DEVICE_ID0_VERSION bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID0_VERSION_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID0_VERSION bitfield into a packed word x and return the packed field.

SS_DEVICE_ID0_REVISION

SSwitch revision.

XS1_SS_DEVICE_ID0_REVISION_SHIFT

XS1_SS_DEVICE_ID0_REVISION_SIZE

XS1_SS_DEVICE_ID0_REVISION_MASK

XS1_SS_DEVICE_ID0_REVISION(x)

Extract the SS_DEVICE_ID0_REVISION bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID0_REVISION_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID0_REVISION bitfield into a packed word x and return the packed field.

SS_DEVICE_ID0_BOOT_CTRL

Sampled values of BootCtl pins on Power On Reset.

XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT

XS1_SS_DEVICE_ID0_BOOT_CTRL_SIZE

XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK

XS1_SS_DEVICE_ID0_BOOT_CTRL(x)

Extract the SS_DEVICE_ID0_BOOT_CTRL bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID0_BOOT_CTRL_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID0_BOOT_CTRL bitfield into a packed word x and return the packed field.

SS_DEVICE_ID1_NUM_PLINKS_PER_PROC

Number of processors on the device.

XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT

XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SIZE

XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK

XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC(x)

Extract the SS_DEVICE_ID1_NUM_PLINKS_PER_PROC bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID1_NUM_PLINKS_PER_PROC bitfield into a packed word x and return the packed field.

SS_DEVICE_ID1_NUM_PROCESSORS

Number of processors on the SSwitch.

XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT

XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SIZE

XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK

XS1_SS_DEVICE_ID1_NUM_PROCESSORS(x)

Extract the SS_DEVICE_ID1_NUM_PROCESSORS bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID1_NUM_PROCESSORS bitfield into a packed word x and return the packed field.

SS_DEVICE_ID1_NUM_SLINKS

Number of SLinks on the SSwitch.

XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT

XS1_SS_DEVICE_ID1_NUM_SLINKS_SIZE

XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK

XS1_SS_DEVICE_ID1_NUM_SLINKS(x)

Extract the SS_DEVICE_ID1_NUM_SLINKS bitfield from a packed word x and return it.

XS1_SS_DEVICE_ID1_NUM_SLINKS_SET(x, v)

Pack the value (v) of the SS_DEVICE_ID1_NUM_SLINKS bitfield into a packed word x and return the packed field.

SS_NODE_CONFIG_HEADERS

0 = 2-byte headers, 1 = 1-byte headers (reset as 0).

XS1_SS_NODE_CONFIG_HEADERS_SHIFT

XS1_SS_NODE_CONFIG_HEADERS_SIZE

XS1_SS_NODE_CONFIG_HEADERS_MASK

XS1_SS_NODE_CONFIG_HEADERS(x)

Extract the SS_NODE_CONFIG_HEADERS bitfield from a packed word x and return it.

XS1_SS_NODE_CONFIG_HEADERS_SET(x, v)

Pack the value (v) of the SS_NODE_CONFIG_HEADERS bitfield into a packed word x and return the packed field.

SS_NODE_CONFIG_DISABLE_PLL_CTL_REG

0 = PLL_CTL_REG has write access.

1 = PLL_CTL_REG can not be written to.

XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT

XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SIZE

XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK

XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG(x)

Extract the SS_NODE_CONFIG_DISABLE_PLL_CTL_REG bitfield from a packed word x and return it.

XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SET(x, v)

Pack the value (v) of the SS_NODE_CONFIG_DISABLE_PLL_CTL_REG bitfield into a packed word x and return the packed field.

SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE

0 = SSCTL registers have write access.

1 = SSCTL registers can not be written to.

XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT

XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SIZE

XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK

XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE(x)

Extract the SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE bitfield from a packed word x and return it.

XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SET(x, v)

Pack the value (v) of the SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE bitfield into a packed word x and return the packed field.

SS_NODE_ID_ID

The unique ID of this node.

XS1_SS_NODE_ID_ID_SHIFT

XS1_SS_NODE_ID_ID_SIZE

XS1_SS_NODE_ID_ID_MASK

XS1_SS_NODE_ID_ID(x)

Extract the SS_NODE_ID_ID bitfield from a packed word x and return it.

XS1_SS_NODE_ID_ID_SET(x, v)

Pack the value (v) of the SS_NODE_ID_ID bitfield into a packed word x and return the packed field.

SS_PLL_CTL_INPUT_DIVISOR

Oscilator input divider value range from 0 (0x00) to 63 (0x3F).

R value.

XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT

XS1_SS_PLL_CTL_INPUT_DIVISOR_SIZE

XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK

XS1_SS_PLL_CTL_INPUT_DIVISOR(x)

Extract the SS_PLL_CTL_INPUT_DIVISOR bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_INPUT_DIVISOR_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_INPUT_DIVISOR bitfield into a packed word x and return the packed field.

SS_PLL_CTL_FEEDBACK_MUL

Feedback multiplication ratio, range from 1 (0x0001) to 8191 (0x1FFF).

F value.

XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT

XS1_SS_PLL_CTL_FEEDBACK_MUL_SIZE

XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK

XS1_SS_PLL_CTL_FEEDBACK_MUL(x)

Extract the SS_PLL_CTL_FEEDBACK_MUL bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_FEEDBACK_MUL_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_FEEDBACK_MUL bitfield into a packed word x and return the packed field.

SS_PLL_CTL_POST_DIVISOR

Output divider value range from 0 to 7.

OD value.

XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT

XS1_SS_PLL_CTL_POST_DIVISOR_SIZE

XS1_SS_PLL_CTL_POST_DIVISOR_MASK

XS1_SS_PLL_CTL_POST_DIVISOR(x)

Extract the SS_PLL_CTL_POST_DIVISOR bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_POST_DIVISOR_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_POST_DIVISOR bitfield into a packed word x and return the packed field.

SS_TEST_MODE_BOOT_RAM

If set to 1, set the boot mode to jump to RAM

XS1_SS_TEST_MODE_BOOT_RAM_SHIFT

XS1_SS_TEST_MODE_BOOT_RAM_SIZE

XS1_SS_TEST_MODE_BOOT_RAM_MASK

XS1_SS_TEST_MODE_BOOT_RAM(x)

Extract the SS_TEST_MODE_BOOT_RAM bitfield from a packed word x and return it.

XS1_SS_TEST_MODE_BOOT_RAM_SET(x, v)

Pack the value (v) of the SS_TEST_MODE_BOOT_RAM bitfield into a packed word x and return the packed field.

SS_APP_PLL_ENABLE

If set to 1, enable the secondary PLL

XS1_SS_APP_PLL_ENABLE_SHIFT

XS1_SS_APP_PLL_ENABLE_SIZE

XS1_SS_APP_PLL_ENABLE_MASK

XS1_SS_APP_PLL_ENABLE(x)

Extract the SS_APP_PLL_ENABLE bitfield from a packed word x and return it.

XS1_SS_APP_PLL_ENABLE_SET(x, v)

Pack the value (v) of the SS_APP_PLL_ENABLE bitfield into a packed word x and return the packed field.

SS_FRAC_N_PERIOD_CYC_CNT

The p value for the fractional divider.

The period over which the fractional N divider oscillates between F and F+1 is p+1

XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT

XS1_SS_FRAC_N_PERIOD_CYC_CNT_SIZE

XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK

XS1_SS_FRAC_N_PERIOD_CYC_CNT(x)

Extract the SS_FRAC_N_PERIOD_CYC_CNT bitfield from a packed word x and return it.

XS1_SS_FRAC_N_PERIOD_CYC_CNT_SET(x, v)

Pack the value (v) of the SS_FRAC_N_PERIOD_CYC_CNT bitfield into a packed word x and return the packed field.

SS_FRAC_N_F_HIGH_CYC_CNT

The f value for the fractional divider.

The number of clock cycles in the period that a divider F+1 is used is f+1.

XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT

XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SIZE

XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK

XS1_SS_FRAC_N_F_HIGH_CYC_CNT(x)

Extract the SS_FRAC_N_F_HIGH_CYC_CNT bitfield from a packed word x and return it.

XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SET(x, v)

Pack the value (v) of the SS_FRAC_N_F_HIGH_CYC_CNT bitfield into a packed word x and return the packed field.

SS_FRAC_N_ENABLE

When set to 1, the secondary PLL will be a fractional N divided PLL

XS1_SS_FRAC_N_ENABLE_SHIFT

XS1_SS_FRAC_N_ENABLE_SIZE

XS1_SS_FRAC_N_ENABLE_MASK

XS1_SS_FRAC_N_ENABLE(x)

Extract the SS_FRAC_N_ENABLE bitfield from a packed word x and return it.

XS1_SS_FRAC_N_ENABLE_SET(x, v)

Pack the value (v) of the SS_FRAC_N_ENABLE bitfield into a packed word x and return the packed field.

SS_LPDDR_ENABLE

When set to 1 this will allow the LPDDR controller to access the pads

XS1_SS_LPDDR_ENABLE_SHIFT

XS1_SS_LPDDR_ENABLE_SIZE

XS1_SS_LPDDR_ENABLE_MASK

XS1_SS_LPDDR_ENABLE(x)

Extract the SS_LPDDR_ENABLE bitfield from a packed word x and return it.

XS1_SS_LPDDR_ENABLE_SET(x, v)

Pack the value (v) of the SS_LPDDR_ENABLE bitfield into a packed word x and return the packed field.

SS_LPDDR_MUXTO_CORE1

Defines which xCORE has access to the LPDDR controller via the mux

XS1_SS_LPDDR_MUXTO_CORE1_SHIFT

XS1_SS_LPDDR_MUXTO_CORE1_SIZE

XS1_SS_LPDDR_MUXTO_CORE1_MASK

XS1_SS_LPDDR_MUXTO_CORE1(x)

Extract the SS_LPDDR_MUXTO_CORE1 bitfield from a packed word x and return it.

XS1_SS_LPDDR_MUXTO_CORE1_SET(x, v)

Pack the value (v) of the SS_LPDDR_MUXTO_CORE1 bitfield into a packed word x and return the packed field.

SS_TEST_MODE_BOOT_JTAG

If set to 1, set the boot mode to boot from JTAG

XS1_SS_TEST_MODE_BOOT_JTAG_SHIFT

XS1_SS_TEST_MODE_BOOT_JTAG_SIZE

XS1_SS_TEST_MODE_BOOT_JTAG_MASK

XS1_SS_TEST_MODE_BOOT_JTAG(x)

Extract the SS_TEST_MODE_BOOT_JTAG bitfield from a packed word x and return it.

XS1_SS_TEST_MODE_BOOT_JTAG_SET(x, v)

Pack the value (v) of the SS_TEST_MODE_BOOT_JTAG bitfield into a packed word x and return the packed field.

SS_APP_PLL_INPUT_FROM_SYS_PLL

If set to 1, use the output of the core PLL as input, otherwise use the crystal oscillator as input.

XS1_SS_APP_PLL_INPUT_FROM_SYS_PLL_SHIFT

XS1_SS_APP_PLL_INPUT_FROM_SYS_PLL_SIZE

XS1_SS_APP_PLL_INPUT_FROM_SYS_PLL_MASK

XS1_SS_APP_PLL_INPUT_FROM_SYS_PLL(x)

Extract the SS_APP_PLL_INPUT_FROM_SYS_PLL bitfield from a packed word x and return it.

XS1_SS_APP_PLL_INPUT_FROM_SYS_PLL_SET(x, v)

Pack the value (v) of the SS_APP_PLL_INPUT_FROM_SYS_PLL bitfield into a packed word x and return the packed field.

SS_APP_PLL_TO_DDR

If set to 1, route the output clock for the Application PLL to the DDR divider and DDR clock, else route it to the APP divider and APP clock

XS1_SS_APP_PLL_TO_DDR_SHIFT

XS1_SS_APP_PLL_TO_DDR_SIZE

XS1_SS_APP_PLL_TO_DDR_MASK

XS1_SS_APP_PLL_TO_DDR(x)

Extract the SS_APP_PLL_TO_DDR bitfield from a packed word x and return it.

XS1_SS_APP_PLL_TO_DDR_SET(x, v)

Pack the value (v) of the SS_APP_PLL_TO_DDR bitfield into a packed word x and return the packed field.

SS_TEST_MODE_PLL_BYPASS

If set to 1, set the PLL to be bypassed

XS1_SS_TEST_MODE_PLL_BYPASS_SHIFT

XS1_SS_TEST_MODE_PLL_BYPASS_SIZE

XS1_SS_TEST_MODE_PLL_BYPASS_MASK

XS1_SS_TEST_MODE_PLL_BYPASS(x)

Extract the SS_TEST_MODE_PLL_BYPASS bitfield from a packed word x and return it.

XS1_SS_TEST_MODE_PLL_BYPASS_SET(x, v)

Pack the value (v) of the SS_TEST_MODE_PLL_BYPASS bitfield into a packed word x and return the packed field.

SS_PLL_CTL_DISABLE

If set to 1, the PLL is disabled.

XS1_SS_PLL_CTL_DISABLE_SHIFT

XS1_SS_PLL_CTL_DISABLE_SIZE

XS1_SS_PLL_CTL_DISABLE_MASK

XS1_SS_PLL_CTL_DISABLE(x)

Extract the SS_PLL_CTL_DISABLE bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_DISABLE_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_DISABLE bitfield into a packed word x and return the packed field.

SS_APP_PLL_BYPASS

If set to 1, set the APP PLL to be bypassed

XS1_SS_APP_PLL_BYPASS_SHIFT

XS1_SS_APP_PLL_BYPASS_SIZE

XS1_SS_APP_PLL_BYPASS_MASK

XS1_SS_APP_PLL_BYPASS(x)

Extract the SS_APP_PLL_BYPASS bitfield from a packed word x and return it.

XS1_SS_APP_PLL_BYPASS_SET(x, v)

Pack the value (v) of the SS_APP_PLL_BYPASS bitfield into a packed word x and return the packed field.

SS_PLL_CTL_NLOCK

If set to 1, the chip will not wait for the PLL to re-lock.

Only use this if a gradual change is made to the PLL

XS1_SS_PLL_CTL_NLOCK_SHIFT

XS1_SS_PLL_CTL_NLOCK_SIZE

XS1_SS_PLL_CTL_NLOCK_MASK

XS1_SS_PLL_CTL_NLOCK(x)

Extract the SS_PLL_CTL_NLOCK bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_NLOCK_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_NLOCK bitfield into a packed word x and return the packed field.

SS_PLL_CTL_NRESET

If set to 1, the chip will not be reset

XS1_SS_PLL_CTL_NRESET_SHIFT

XS1_SS_PLL_CTL_NRESET_SIZE

XS1_SS_PLL_CTL_NRESET_MASK

XS1_SS_PLL_CTL_NRESET(x)

Extract the SS_PLL_CTL_NRESET bitfield from a packed word x and return it.

XS1_SS_PLL_CTL_NRESET_SET(x, v)

Pack the value (v) of the SS_PLL_CTL_NRESET bitfield into a packed word x and return the packed field.

SS_APP_PLL_SEL_OUT_DDR

If set to 1, the Application PLL output will be sent to the DDR rather than the IO

XS1_SS_APP_PLL_SEL_OUT_DDR_SHIFT

XS1_SS_APP_PLL_SEL_OUT_DDR_SIZE

XS1_SS_APP_PLL_SEL_OUT_DDR_MASK

XS1_SS_APP_PLL_SEL_OUT_DDR(x)

Extract the SS_APP_PLL_SEL_OUT_DDR bitfield from a packed word x and return it.

XS1_SS_APP_PLL_SEL_OUT_DDR_SET(x, v)

Pack the value (v) of the SS_APP_PLL_SEL_OUT_DDR bitfield into a packed word x and return the packed field.

SS_CLK_DIVIDER_CLK_DIV

SSwitch clock divider

XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT

XS1_SS_CLK_DIVIDER_CLK_DIV_SIZE

XS1_SS_CLK_DIVIDER_CLK_DIV_MASK

XS1_SS_CLK_DIVIDER_CLK_DIV(x)

Extract the SS_CLK_DIVIDER_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_CLK_DIVIDER_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_CLK_DIVIDER_CLK_DIV bitfield into a packed word x and return the packed field.

SS_SSWITCH_REF_CLK_DIV

Software reference clock divider

XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT

XS1_SS_SSWITCH_REF_CLK_DIV_SIZE

XS1_SS_SSWITCH_REF_CLK_DIV_MASK

XS1_SS_SSWITCH_REF_CLK_DIV(x)

Extract the SS_SSWITCH_REF_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_SSWITCH_REF_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_SSWITCH_REF_CLK_DIV bitfield into a packed word x and return the packed field.

SS_SSWITCH_MIPI_CLK_DIV

MIPI shim clock divider.

When set to X the input clock is divided by 2(X+1).

XS1_SS_SSWITCH_MIPI_CLK_DIV_SHIFT

XS1_SS_SSWITCH_MIPI_CLK_DIV_SIZE

XS1_SS_SSWITCH_MIPI_CLK_DIV_MASK

XS1_SS_SSWITCH_MIPI_CLK_DIV(x)

Extract the SS_SSWITCH_MIPI_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_SSWITCH_MIPI_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_SSWITCH_MIPI_CLK_DIV bitfield into a packed word x and return the packed field.

SS_SSWITCH_MIPI_CLK_DIV_DISABLE

MIPI clock divider disable.

When set to 0, the divider is enabled.

XS1_SS_SSWITCH_MIPI_CLK_DIV_DISABLE_SHIFT

XS1_SS_SSWITCH_MIPI_CLK_DIV_DISABLE_SIZE

XS1_SS_SSWITCH_MIPI_CLK_DIV_DISABLE_MASK

XS1_SS_SSWITCH_MIPI_CLK_DIV_DISABLE(x)

Extract the SS_SSWITCH_MIPI_CLK_DIV_DISABLE bitfield from a packed word x and return it.

XS1_SS_SSWITCH_MIPI_CLK_DIV_DISABLE_SET(x, v)

Pack the value (v) of the SS_SSWITCH_MIPI_CLK_DIV_DISABLE bitfield into a packed word x and return the packed field.

SS_DDR_CLK_DIV

LPDDR clock divider.

When set to X the input clock is divided by 2(X+1).

XS1_SS_DDR_CLK_DIV_SHIFT

XS1_SS_DDR_CLK_DIV_SIZE

XS1_SS_DDR_CLK_DIV_MASK

XS1_SS_DDR_CLK_DIV(x)

Extract the SS_DDR_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_DDR_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_DDR_CLK_DIV bitfield into a packed word x and return the packed field.

SS_DDR_CLK_DIV_DISABLE

LPDDR clock divider disable.

When set to 0, the divider is enabled.

XS1_SS_DDR_CLK_DIV_DISABLE_SHIFT

XS1_SS_DDR_CLK_DIV_DISABLE_SIZE

XS1_SS_DDR_CLK_DIV_DISABLE_MASK

XS1_SS_DDR_CLK_DIV_DISABLE(x)

Extract the SS_DDR_CLK_DIV_DISABLE bitfield from a packed word x and return it.

XS1_SS_DDR_CLK_DIV_DISABLE_SET(x, v)

Pack the value (v) of the SS_DDR_CLK_DIV_DISABLE bitfield into a packed word x and return the packed field.

SS_DDR_CLK_FROM_APP_PLL

If set to 1, the secondary PLL is used as a source for the LPDDR clock divider.

By default, the output of the core PLL is used.

XS1_SS_DDR_CLK_FROM_APP_PLL_SHIFT

XS1_SS_DDR_CLK_FROM_APP_PLL_SIZE

XS1_SS_DDR_CLK_FROM_APP_PLL_MASK

XS1_SS_DDR_CLK_FROM_APP_PLL(x)

Extract the SS_DDR_CLK_FROM_APP_PLL bitfield from a packed word x and return it.

XS1_SS_DDR_CLK_FROM_APP_PLL_SET(x, v)

Pack the value (v) of the SS_DDR_CLK_FROM_APP_PLL bitfield into a packed word x and return the packed field.

SS_MIPI_CLK_FROM_APP_PLL

If set to 1, the secondary PLL is used as a source for the MIPI shim clock divider.

By default, the output of the core PLL is used.

XS1_SS_MIPI_CLK_FROM_APP_PLL_SHIFT

XS1_SS_MIPI_CLK_FROM_APP_PLL_SIZE

XS1_SS_MIPI_CLK_FROM_APP_PLL_MASK

XS1_SS_MIPI_CLK_FROM_APP_PLL(x)

Extract the SS_MIPI_CLK_FROM_APP_PLL bitfield from a packed word x and return it.

XS1_SS_MIPI_CLK_FROM_APP_PLL_SET(x, v)

Pack the value (v) of the SS_MIPI_CLK_FROM_APP_PLL bitfield into a packed word x and return the packed field.

SS_APP_CLK_DIV

Application clock divider.

When set to X, the output of the secondary PLL will be divided by 2(X+1) in order to form the output on the output pin

XS1_SS_APP_CLK_DIV_SHIFT

XS1_SS_APP_CLK_DIV_SIZE

XS1_SS_APP_CLK_DIV_MASK

XS1_SS_APP_CLK_DIV(x)

Extract the SS_APP_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_APP_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_APP_CLK_DIV bitfield into a packed word x and return the packed field.

SS_APP_CLK_DIV_DISABLE

Application clock divider disable.

When set to 0, the divider is enabled, and pin X1D11 will be connected to the application clock rather than to port 1D.

XS1_SS_APP_CLK_DIV_DISABLE_SHIFT

XS1_SS_APP_CLK_DIV_DISABLE_SIZE

XS1_SS_APP_CLK_DIV_DISABLE_MASK

XS1_SS_APP_CLK_DIV_DISABLE(x)

Extract the SS_APP_CLK_DIV_DISABLE bitfield from a packed word x and return it.

XS1_SS_APP_CLK_DIV_DISABLE_SET(x, v)

Pack the value (v) of the SS_APP_CLK_DIV_DISABLE bitfield into a packed word x and return the packed field.

SS_APP_CLK_FROM_APP_PLL

If set to 1, the secondary PLL is used as a source for the application clock divider.

By default, the output of the core PLL is used.

XS1_SS_APP_CLK_FROM_APP_PLL_SHIFT

XS1_SS_APP_CLK_FROM_APP_PLL_SIZE

XS1_SS_APP_CLK_FROM_APP_PLL_MASK

XS1_SS_APP_CLK_FROM_APP_PLL(x)

Extract the SS_APP_CLK_FROM_APP_PLL bitfield from a packed word x and return it.

XS1_SS_APP_CLK_FROM_APP_PLL_SET(x, v)

Pack the value (v) of the SS_APP_CLK_FROM_APP_PLL bitfield into a packed word x and return the packed field.

SS_MIPI_CFG_CLK_DIV

MIPI PHY clock divider.

When set to X, the input clock will be divided by 2(X+1).

XS1_SS_MIPI_CFG_CLK_DIV_SHIFT

XS1_SS_MIPI_CFG_CLK_DIV_SIZE

XS1_SS_MIPI_CFG_CLK_DIV_MASK

XS1_SS_MIPI_CFG_CLK_DIV(x)

Extract the SS_MIPI_CFG_CLK_DIV bitfield from a packed word x and return it.

XS1_SS_MIPI_CFG_CLK_DIV_SET(x, v)

Pack the value (v) of the SS_MIPI_CFG_CLK_DIV bitfield into a packed word x and return the packed field.

SS_MIPI_CFG_CLK_DIV_DISABLE

MIPI PHY clock divider disable.

When set to 0, the divider is enabled.

XS1_SS_MIPI_CFG_CLK_DIV_DISABLE_SHIFT

XS1_SS_MIPI_CFG_CLK_DIV_DISABLE_SIZE

XS1_SS_MIPI_CFG_CLK_DIV_DISABLE_MASK

XS1_SS_MIPI_CFG_CLK_DIV_DISABLE(x)

Extract the SS_MIPI_CFG_CLK_DIV_DISABLE bitfield from a packed word x and return it.

XS1_SS_MIPI_CFG_CLK_DIV_DISABLE_SET(x, v)

Pack the value (v) of the SS_MIPI_CFG_CLK_DIV_DISABLE bitfield into a packed word x and return the packed field.

SS_MIPI_CFG_CLK_FROM_APP_PLL

If set to 1, the secondary PLL is used as a source for the MIPI PHY clock divider.

By default, the output of the core PLL is used.

XS1_SS_MIPI_CFG_CLK_FROM_APP_PLL_SHIFT

XS1_SS_MIPI_CFG_CLK_FROM_APP_PLL_SIZE

XS1_SS_MIPI_CFG_CLK_FROM_APP_PLL_MASK

XS1_SS_MIPI_CFG_CLK_FROM_APP_PLL(x)

Extract the SS_MIPI_CFG_CLK_FROM_APP_PLL bitfield from a packed word x and return it.

XS1_SS_MIPI_CFG_CLK_FROM_APP_PLL_SET(x, v)

Pack the value (v) of the SS_MIPI_CFG_CLK_FROM_APP_PLL bitfield into a packed word x and return the packed field.

SS_JTAG_DEVICE_ID_CONST_VAL

XS1_SS_JTAG_DEVICE_ID_CONST_VAL_SHIFT

XS1_SS_JTAG_DEVICE_ID_CONST_VAL_SIZE

XS1_SS_JTAG_DEVICE_ID_CONST_VAL_MASK

XS1_SS_JTAG_DEVICE_ID_CONST_VAL(x)

Extract the SS_JTAG_DEVICE_ID_CONST_VAL bitfield from a packed word x and return it.

XS1_SS_JTAG_DEVICE_ID_CONST_VAL_SET(x, v)

Pack the value (v) of the SS_JTAG_DEVICE_ID_CONST_VAL bitfield into a packed word x and return the packed field.

SS_JTAG_DEVICE_ID_MANU_ID

XS1_SS_JTAG_DEVICE_ID_MANU_ID_SHIFT

XS1_SS_JTAG_DEVICE_ID_MANU_ID_SIZE

XS1_SS_JTAG_DEVICE_ID_MANU_ID_MASK

XS1_SS_JTAG_DEVICE_ID_MANU_ID(x)

Extract the SS_JTAG_DEVICE_ID_MANU_ID bitfield from a packed word x and return it.

XS1_SS_JTAG_DEVICE_ID_MANU_ID_SET(x, v)

Pack the value (v) of the SS_JTAG_DEVICE_ID_MANU_ID bitfield into a packed word x and return the packed field.

SS_JTAG_DEVICE_ID_PART_NUM

XS1_SS_JTAG_DEVICE_ID_PART_NUM_SHIFT

XS1_SS_JTAG_DEVICE_ID_PART_NUM_SIZE

XS1_SS_JTAG_DEVICE_ID_PART_NUM_MASK

XS1_SS_JTAG_DEVICE_ID_PART_NUM(x)

Extract the SS_JTAG_DEVICE_ID_PART_NUM bitfield from a packed word x and return it.

XS1_SS_JTAG_DEVICE_ID_PART_NUM_SET(x, v)

Pack the value (v) of the SS_JTAG_DEVICE_ID_PART_NUM bitfield into a packed word x and return the packed field.

SS_JTAG_DEVICE_ID_VERSION

XS1_SS_JTAG_DEVICE_ID_VERSION_SHIFT

XS1_SS_JTAG_DEVICE_ID_VERSION_SIZE

XS1_SS_JTAG_DEVICE_ID_VERSION_MASK

XS1_SS_JTAG_DEVICE_ID_VERSION(x)

Extract the SS_JTAG_DEVICE_ID_VERSION bitfield from a packed word x and return it.

XS1_SS_JTAG_DEVICE_ID_VERSION_SET(x, v)

Pack the value (v) of the SS_JTAG_DEVICE_ID_VERSION bitfield into a packed word x and return the packed field.

SS_JTAG_USERCODE_MASKID

metal fixable ID code

XS1_SS_JTAG_USERCODE_MASKID_SHIFT

XS1_SS_JTAG_USERCODE_MASKID_SIZE

XS1_SS_JTAG_USERCODE_MASKID_MASK

XS1_SS_JTAG_USERCODE_MASKID(x)

Extract the SS_JTAG_USERCODE_MASKID bitfield from a packed word x and return it.

XS1_SS_JTAG_USERCODE_MASKID_SET(x, v)

Pack the value (v) of the SS_JTAG_USERCODE_MASKID bitfield into a packed word x and return the packed field.

SS_JTAG_USERCODE_OTP

JTAG USERCODE value programmed into OTP SR

XS1_SS_JTAG_USERCODE_OTP_SHIFT

XS1_SS_JTAG_USERCODE_OTP_SIZE

XS1_SS_JTAG_USERCODE_OTP_MASK

XS1_SS_JTAG_USERCODE_OTP(x)

Extract the SS_JTAG_USERCODE_OTP bitfield from a packed word x and return it.

XS1_SS_JTAG_USERCODE_OTP_SET(x, v)

Pack the value (v) of the SS_JTAG_USERCODE_OTP bitfield into a packed word x and return the packed field.

DIM0_DIR

The direction for packets whose dimension is 0.

XS1_DIM0_DIR_SHIFT

XS1_DIM0_DIR_SIZE

XS1_DIM0_DIR_MASK

XS1_DIM0_DIR(x)

Extract the DIM0_DIR bitfield from a packed word x and return it.

XS1_DIM0_DIR_SET(x, v)

Pack the value (v) of the DIM0_DIR bitfield into a packed word x and return the packed field.

DIM1_DIR

The direction for packets whose dimension is 1.

XS1_DIM1_DIR_SHIFT

XS1_DIM1_DIR_SIZE

XS1_DIM1_DIR_MASK

XS1_DIM1_DIR(x)

Extract the DIM1_DIR bitfield from a packed word x and return it.

XS1_DIM1_DIR_SET(x, v)

Pack the value (v) of the DIM1_DIR bitfield into a packed word x and return the packed field.

DIM2_DIR

The direction for packets whose dimension is 2.

XS1_DIM2_DIR_SHIFT

XS1_DIM2_DIR_SIZE

XS1_DIM2_DIR_MASK

XS1_DIM2_DIR(x)

Extract the DIM2_DIR bitfield from a packed word x and return it.

XS1_DIM2_DIR_SET(x, v)

Pack the value (v) of the DIM2_DIR bitfield into a packed word x and return the packed field.

DIM3_DIR

The direction for packets whose dimension is 3.

XS1_DIM3_DIR_SHIFT

XS1_DIM3_DIR_SIZE

XS1_DIM3_DIR_MASK

XS1_DIM3_DIR(x)

Extract the DIM3_DIR bitfield from a packed word x and return it.

XS1_DIM3_DIR_SET(x, v)

Pack the value (v) of the DIM3_DIR bitfield into a packed word x and return the packed field.

DIM4_DIR

The direction for packets whose dimension is 4.

XS1_DIM4_DIR_SHIFT

XS1_DIM4_DIR_SIZE

XS1_DIM4_DIR_MASK

XS1_DIM4_DIR(x)

Extract the DIM4_DIR bitfield from a packed word x and return it.

XS1_DIM4_DIR_SET(x, v)

Pack the value (v) of the DIM4_DIR bitfield into a packed word x and return the packed field.

DIM5_DIR

The direction for packets whose dimension is 5.

XS1_DIM5_DIR_SHIFT

XS1_DIM5_DIR_SIZE

XS1_DIM5_DIR_MASK

XS1_DIM5_DIR(x)

Extract the DIM5_DIR bitfield from a packed word x and return it.

XS1_DIM5_DIR_SET(x, v)

Pack the value (v) of the DIM5_DIR bitfield into a packed word x and return the packed field.

DIM6_DIR

The direction for packets whose dimension is 6.

XS1_DIM6_DIR_SHIFT

XS1_DIM6_DIR_SIZE

XS1_DIM6_DIR_MASK

XS1_DIM6_DIR(x)

Extract the DIM6_DIR bitfield from a packed word x and return it.

XS1_DIM6_DIR_SET(x, v)

Pack the value (v) of the DIM6_DIR bitfield into a packed word x and return the packed field.

DIM7_DIR

The direction for packets whose dimension is 7.

XS1_DIM7_DIR_SHIFT

XS1_DIM7_DIR_SIZE

XS1_DIM7_DIR_MASK

XS1_DIM7_DIR(x)

Extract the DIM7_DIR bitfield from a packed word x and return it.

XS1_DIM7_DIR_SET(x, v)

Pack the value (v) of the DIM7_DIR bitfield into a packed word x and return the packed field.

DIM8_DIR

The direction for packets whose dimension is 8.

XS1_DIM8_DIR_SHIFT

XS1_DIM8_DIR_SIZE

XS1_DIM8_DIR_MASK

XS1_DIM8_DIR(x)

Extract the DIM8_DIR bitfield from a packed word x and return it.

XS1_DIM8_DIR_SET(x, v)

Pack the value (v) of the DIM8_DIR bitfield into a packed word x and return the packed field.

DIM9_DIR

The direction for packets whose dimension is 9.

XS1_DIM9_DIR_SHIFT

XS1_DIM9_DIR_SIZE

XS1_DIM9_DIR_MASK

XS1_DIM9_DIR(x)

Extract the DIM9_DIR bitfield from a packed word x and return it.

XS1_DIM9_DIR_SET(x, v)

Pack the value (v) of the DIM9_DIR bitfield into a packed word x and return the packed field.

DIMA_DIR

The direction for packets whose dimension is A.

XS1_DIMA_DIR_SHIFT

XS1_DIMA_DIR_SIZE

XS1_DIMA_DIR_MASK

XS1_DIMA_DIR(x)

Extract the DIMA_DIR bitfield from a packed word x and return it.

XS1_DIMA_DIR_SET(x, v)

Pack the value (v) of the DIMA_DIR bitfield into a packed word x and return the packed field.

DIMB_DIR

The direction for packets whose dimension is B.

XS1_DIMB_DIR_SHIFT

XS1_DIMB_DIR_SIZE

XS1_DIMB_DIR_MASK

XS1_DIMB_DIR(x)

Extract the DIMB_DIR bitfield from a packed word x and return it.

XS1_DIMB_DIR_SET(x, v)

Pack the value (v) of the DIMB_DIR bitfield into a packed word x and return the packed field.

DIMC_DIR

The direction for packets whose dimension is C.

XS1_DIMC_DIR_SHIFT

XS1_DIMC_DIR_SIZE

XS1_DIMC_DIR_MASK

XS1_DIMC_DIR(x)

Extract the DIMC_DIR bitfield from a packed word x and return it.

XS1_DIMC_DIR_SET(x, v)

Pack the value (v) of the DIMC_DIR bitfield into a packed word x and return the packed field.

DIMD_DIR

The direction for packets whose dimension is D.

XS1_DIMD_DIR_SHIFT

XS1_DIMD_DIR_SIZE

XS1_DIMD_DIR_MASK

XS1_DIMD_DIR(x)

Extract the DIMD_DIR bitfield from a packed word x and return it.

XS1_DIMD_DIR_SET(x, v)

Pack the value (v) of the DIMD_DIR bitfield into a packed word x and return the packed field.

DIME_DIR

The direction for packets whose dimension is E.

XS1_DIME_DIR_SHIFT

XS1_DIME_DIR_SIZE

XS1_DIME_DIR_MASK

XS1_DIME_DIR(x)

Extract the DIME_DIR bitfield from a packed word x and return it.

XS1_DIME_DIR_SET(x, v)

Pack the value (v) of the DIME_DIR bitfield into a packed word x and return the packed field.

DIMF_DIR

The direction for packets whose dimension is F.

XS1_DIMF_DIR_SHIFT

XS1_DIMF_DIR_SIZE

XS1_DIMF_DIR_MASK

XS1_DIMF_DIR(x)

Extract the DIMF_DIR bitfield from a packed word x and return it.

XS1_DIMF_DIR_SET(x, v)

Pack the value (v) of the DIMF_DIR bitfield into a packed word x and return the packed field.

GLOBAL_DEBUG_ENABLE_INDEBUG

if DEBUGN Set 1 to enable inDebug bit to drive GlobalDebug.else Reserved.

XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT

XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SIZE

XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK

XS1_GLOBAL_DEBUG_ENABLE_INDEBUG(x)

Extract the GLOBAL_DEBUG_ENABLE_INDEBUG bitfield from a packed word x and return it.

XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SET(x, v)

Pack the value (v) of the GLOBAL_DEBUG_ENABLE_INDEBUG bitfield into a packed word x and return the packed field.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ

if DEBUGN Set 1 to enable GlobalDebug to generate debug request to XCore.else Reserved.

XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT

XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SIZE

XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK

XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ(x)

Extract the GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ bitfield from a packed word x and return it.

XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SET(x, v)

Pack the value (v) of the GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ bitfield into a packed word x and return the packed field.

GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG

If set, XCore0 is the source of last GlobalDebug event.

XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT

XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SIZE

XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK

XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG(x)

Extract the GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG bitfield from a packed word x and return it.

XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SET(x, v)

Pack the value (v) of the GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG bitfield into a packed word x and return the packed field.

GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG

If set, XCore1 is the source of last GlobalDebug event.

XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT

XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SIZE

XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK

XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG(x)

Extract the GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG bitfield from a packed word x and return it.

XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SET(x, v)

Pack the value (v) of the GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG bitfield into a packed word x and return the packed field.

GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG

if DEBUGN If set, external pin, is the source of last GlobalDebug event.else Reserved.

XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT

XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SIZE

XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK

XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG(x)

Extract the GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG bitfield from a packed word x and return it.

XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SET(x, v)

Pack the value (v) of the GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG bitfield into a packed word x and return the packed field.

LINK_SRC_INUSE

1 when the source side of the link is in use.

XS1_LINK_SRC_INUSE_SHIFT

XS1_LINK_SRC_INUSE_SIZE

XS1_LINK_SRC_INUSE_MASK

XS1_LINK_SRC_INUSE(x)

Extract the LINK_SRC_INUSE bitfield from a packed word x and return it.

XS1_LINK_SRC_INUSE_SET(x, v)

Pack the value (v) of the LINK_SRC_INUSE bitfield into a packed word x and return the packed field.

LINK_DST_INUSE

1 when the dest side of the link is in use.

XS1_LINK_DST_INUSE_SHIFT

XS1_LINK_DST_INUSE_SIZE

XS1_LINK_DST_INUSE_MASK

XS1_LINK_DST_INUSE(x)

Extract the LINK_DST_INUSE bitfield from a packed word x and return it.

XS1_LINK_DST_INUSE_SET(x, v)

Pack the value (v) of the LINK_DST_INUSE bitfield into a packed word x and return the packed field.

LINK_JUNK

1 when the current packet is considered junk and will be thrown away.

XS1_LINK_JUNK_SHIFT

XS1_LINK_JUNK_SIZE

XS1_LINK_JUNK_MASK

XS1_LINK_JUNK(x)

Extract the LINK_JUNK bitfield from a packed word x and return it.

XS1_LINK_JUNK_SET(x, v)

Pack the value (v) of the LINK_JUNK bitfield into a packed word x and return the packed field.

LINK_NETWORK

Determines the network to which this link belongs, reset as 0.

XS1_LINK_NETWORK_SHIFT

XS1_LINK_NETWORK_SIZE

XS1_LINK_NETWORK_MASK

XS1_LINK_NETWORK(x)

Extract the LINK_NETWORK bitfield from a packed word x and return it.

XS1_LINK_NETWORK_SET(x, v)

Pack the value (v) of the LINK_NETWORK bitfield into a packed word x and return the packed field.

LINK_DIRECTION

The direction that this link operates in.

XS1_LINK_DIRECTION_SHIFT

XS1_LINK_DIRECTION_SIZE

XS1_LINK_DIRECTION_MASK

XS1_LINK_DIRECTION(x)

Extract the LINK_DIRECTION bitfield from a packed word x and return it.

XS1_LINK_DIRECTION_SET(x, v)

Pack the value (v) of the LINK_DIRECTION bitfield into a packed word x and return the packed field.

SLINK_SRC_TARGET_ID

When the link is in use, this is the destination link number to which all packets are sent.

XS1_SLINK_SRC_TARGET_ID_SHIFT

XS1_SLINK_SRC_TARGET_ID_SIZE

XS1_SLINK_SRC_TARGET_ID_MASK

XS1_SLINK_SRC_TARGET_ID(x)

Extract the SLINK_SRC_TARGET_ID bitfield from a packed word x and return it.

XS1_SLINK_SRC_TARGET_ID_SET(x, v)

Pack the value (v) of the SLINK_SRC_TARGET_ID bitfield into a packed word x and return the packed field.

SLINK_SRC_TARGET_TYPE

Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_SLINK_SRC_TARGET_TYPE_SHIFT

XS1_SLINK_SRC_TARGET_TYPE_SIZE

XS1_SLINK_SRC_TARGET_TYPE_MASK

XS1_SLINK_SRC_TARGET_TYPE(x)

Extract the SLINK_SRC_TARGET_TYPE bitfield from a packed word x and return it.

XS1_SLINK_SRC_TARGET_TYPE_SET(x, v)

Pack the value (v) of the SLINK_SRC_TARGET_TYPE bitfield into a packed word x and return the packed field.

PLINK_SRC_TARGET_ID

When the link is in use, this is the destination link number to which all packets are sent.

XS1_PLINK_SRC_TARGET_ID_SHIFT

XS1_PLINK_SRC_TARGET_ID_SIZE

XS1_PLINK_SRC_TARGET_ID_MASK

XS1_PLINK_SRC_TARGET_ID(x)

Extract the PLINK_SRC_TARGET_ID bitfield from a packed word x and return it.

XS1_PLINK_SRC_TARGET_ID_SET(x, v)

Pack the value (v) of the PLINK_SRC_TARGET_ID bitfield into a packed word x and return the packed field.

PLINK_SRC_TARGET_TYPE

Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_PLINK_SRC_TARGET_TYPE_SHIFT

XS1_PLINK_SRC_TARGET_TYPE_SIZE

XS1_PLINK_SRC_TARGET_TYPE_MASK

XS1_PLINK_SRC_TARGET_TYPE(x)

Extract the PLINK_SRC_TARGET_TYPE bitfield from a packed word x and return it.

XS1_PLINK_SRC_TARGET_TYPE_SET(x, v)

Pack the value (v) of the PLINK_SRC_TARGET_TYPE bitfield into a packed word x and return the packed field.

XLINK_INTER_TOKEN_DELAY

Specify min.

number of idle system clocks between two continuous transmit tokens -1.

XS1_XLINK_INTER_TOKEN_DELAY_SHIFT

XS1_XLINK_INTER_TOKEN_DELAY_SIZE

XS1_XLINK_INTER_TOKEN_DELAY_MASK

XS1_XLINK_INTER_TOKEN_DELAY(x)

Extract the XLINK_INTER_TOKEN_DELAY bitfield from a packed word x and return it.

XS1_XLINK_INTER_TOKEN_DELAY_SET(x, v)

Pack the value (v) of the XLINK_INTER_TOKEN_DELAY bitfield into a packed word x and return the packed field.

XLINK_INTRA_TOKEN_DELAY

Specify min.

number of idle system clocks between two continuous symbols witin a transmit token -1.

XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT

XS1_XLINK_INTRA_TOKEN_DELAY_SIZE

XS1_XLINK_INTRA_TOKEN_DELAY_MASK

XS1_XLINK_INTRA_TOKEN_DELAY(x)

Extract the XLINK_INTRA_TOKEN_DELAY bitfield from a packed word x and return it.

XS1_XLINK_INTRA_TOKEN_DELAY_SET(x, v)

Pack the value (v) of the XLINK_INTRA_TOKEN_DELAY bitfield into a packed word x and return the packed field.

XLINK_RX_RESET

Reset the receiver.

The next symbol that is detected will be the first symbol in a token.

XS1_XLINK_RX_RESET_SHIFT

XS1_XLINK_RX_RESET_SIZE

XS1_XLINK_RX_RESET_MASK

XS1_XLINK_RX_RESET(x)

Extract the XLINK_RX_RESET bitfield from a packed word x and return it.

XS1_XLINK_RX_RESET_SET(x, v)

Pack the value (v) of the XLINK_RX_RESET bitfield into a packed word x and return the packed field.

XLINK_HELLO

Clear this end of the xlink’s credit and issue a HELLO token.

XS1_XLINK_HELLO_SHIFT

XS1_XLINK_HELLO_SIZE

XS1_XLINK_HELLO_MASK

XS1_XLINK_HELLO(x)

Extract the XLINK_HELLO bitfield from a packed word x and return it.

XS1_XLINK_HELLO_SET(x, v)

Pack the value (v) of the XLINK_HELLO bitfield into a packed word x and return the packed field.

TX_CREDIT

This end of the xlink has credit to allow it to transmit.

XS1_TX_CREDIT_SHIFT

XS1_TX_CREDIT_SIZE

XS1_TX_CREDIT_MASK

XS1_TX_CREDIT(x)

Extract the TX_CREDIT bitfield from a packed word x and return it.

XS1_TX_CREDIT_SET(x, v)

Pack the value (v) of the TX_CREDIT bitfield into a packed word x and return the packed field.

RX_CREDIT

This end of the xlink has issued credit to allow the remote end to transmit

XS1_RX_CREDIT_SHIFT

XS1_RX_CREDIT_SIZE

XS1_RX_CREDIT_MASK

XS1_RX_CREDIT(x)

Extract the RX_CREDIT bitfield from a packed word x and return it.

XS1_RX_CREDIT_SET(x, v)

Pack the value (v) of the RX_CREDIT bitfield into a packed word x and return the packed field.

XLINK_RX_ERROR

Rx buffer overflow or illegal token encoding received.

XS1_XLINK_RX_ERROR_SHIFT

XS1_XLINK_RX_ERROR_SIZE

XS1_XLINK_RX_ERROR_MASK

XS1_XLINK_RX_ERROR(x)

Extract the XLINK_RX_ERROR bitfield from a packed word x and return it.

XS1_XLINK_RX_ERROR_SET(x, v)

Pack the value (v) of the XLINK_RX_ERROR bitfield into a packed word x and return the packed field.

XLINK_WIDE

0: operate in 2 wire mode; 1: operate in 5 wire mode

XS1_XLINK_WIDE_SHIFT

XS1_XLINK_WIDE_SIZE

XS1_XLINK_WIDE_MASK

XS1_XLINK_WIDE(x)

Extract the XLINK_WIDE bitfield from a packed word x and return it.

XS1_XLINK_WIDE_SET(x, v)

Pack the value (v) of the XLINK_WIDE bitfield into a packed word x and return the packed field.

XLINK_ENABLE

Write to this bit with ‘1’ will enable the XLink, writing ‘0’ will disable it.

This bit controls the muxing of ports with overlapping xlinks.

XS1_XLINK_ENABLE_SHIFT

XS1_XLINK_ENABLE_SIZE

XS1_XLINK_ENABLE_MASK

XS1_XLINK_ENABLE(x)

Extract the XLINK_ENABLE bitfield from a packed word x and return it.

XS1_XLINK_ENABLE_SET(x, v)

Pack the value (v) of the XLINK_ENABLE bitfield into a packed word x and return the packed field.

XSTATIC_DEST_CHAN_END

The destination channel end on this node that packets received in static mode are forwarded to.

XS1_XSTATIC_DEST_CHAN_END_SHIFT

XS1_XSTATIC_DEST_CHAN_END_SIZE

XS1_XSTATIC_DEST_CHAN_END_MASK

XS1_XSTATIC_DEST_CHAN_END(x)

Extract the XSTATIC_DEST_CHAN_END bitfield from a packed word x and return it.

XS1_XSTATIC_DEST_CHAN_END_SET(x, v)

Pack the value (v) of the XSTATIC_DEST_CHAN_END bitfield into a packed word x and return the packed field.

XSTATIC_DEST_PROC

The destination processor on this node that packets received in static mode are forwarded to.

XS1_XSTATIC_DEST_PROC_SHIFT

XS1_XSTATIC_DEST_PROC_SIZE

XS1_XSTATIC_DEST_PROC_MASK

XS1_XSTATIC_DEST_PROC(x)

Extract the XSTATIC_DEST_PROC bitfield from a packed word x and return it.

XS1_XSTATIC_DEST_PROC_SET(x, v)

Pack the value (v) of the XSTATIC_DEST_PROC bitfield into a packed word x and return the packed field.

XSTATIC_ENABLE

Enable static forwarding.

XS1_XSTATIC_ENABLE_SHIFT

XS1_XSTATIC_ENABLE_SIZE

XS1_XSTATIC_ENABLE_MASK

XS1_XSTATIC_ENABLE(x)

Extract the XSTATIC_ENABLE bitfield from a packed word x and return it.

XS1_XSTATIC_ENABLE_SET(x, v)

Pack the value (v) of the XSTATIC_ENABLE bitfield into a packed word x and return the packed field.

SSCTRL_PSCTRL_CORE_NUM

Core Number for the PSCTRL register address through the SSwitch

XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT

XS1_SSCTRL_PSCTRL_CORE_NUM_SIZE

XS1_SSCTRL_PSCTRL_CORE_NUM_MASK

XS1_SSCTRL_PSCTRL_CORE_NUM(x)

Extract the SSCTRL_PSCTRL_CORE_NUM bitfield from a packed word x and return it.

XS1_SSCTRL_PSCTRL_CORE_NUM_SET(x, v)

Pack the value (v) of the SSCTRL_PSCTRL_CORE_NUM bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_UTMI_XCVRSELECT

Value of the UTMI XCVRSelect signals to the USB Phy

XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT

XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SIZE

XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK

XS1_USB_PHY_CFG0_UTMI_XCVRSELECT(x)

Extract the USB_PHY_CFG0_UTMI_XCVRSELECT bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_UTMI_XCVRSELECT bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_UTMI_TERMSELECT

Value of the UTMI Terminal Select signal to the USB Phy

XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT

XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SIZE

XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK

XS1_USB_PHY_CFG0_UTMI_TERMSELECT(x)

Extract the USB_PHY_CFG0_UTMI_TERMSELECT bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_UTMI_TERMSELECT bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_UTMI_OPMODE

Value of the UTMI OpMode signals to the USB Phy

XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT

XS1_USB_PHY_CFG0_UTMI_OPMODE_SIZE

XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK

XS1_USB_PHY_CFG0_UTMI_OPMODE(x)

Extract the USB_PHY_CFG0_UTMI_OPMODE bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_UTMI_OPMODE_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_UTMI_OPMODE bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_UTMI_SUSPENDM

Value of the UTMI SuspendM signal to the USB Phy

XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT

XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SIZE

XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK

XS1_USB_PHY_CFG0_UTMI_SUSPENDM(x)

Extract the USB_PHY_CFG0_UTMI_SUSPENDM bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_UTMI_SUSPENDM bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_DPPULLDOWN

Set to 1 to enable the DP Pulldown

XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT

XS1_USB_PHY_CFG0_DPPULLDOWN_SIZE

XS1_USB_PHY_CFG0_DPPULLDOWN_MASK

XS1_USB_PHY_CFG0_DPPULLDOWN(x)

Extract the USB_PHY_CFG0_DPPULLDOWN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_DPPULLDOWN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_DPPULLDOWN bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_DMPULLDOWN

Set to 1 to enable the DM Pulldown

XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT

XS1_USB_PHY_CFG0_DMPULLDOWN_SIZE

XS1_USB_PHY_CFG0_DMPULLDOWN_MASK

XS1_USB_PHY_CFG0_DMPULLDOWN(x)

Extract the USB_PHY_CFG0_DMPULLDOWN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_DMPULLDOWN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_DMPULLDOWN bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_TXBITSTUFF_EN

Set to 1 to enable USB Tx BitStuffing

XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT

XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SIZE

XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK

XS1_USB_PHY_CFG0_TXBITSTUFF_EN(x)

Extract the USB_PHY_CFG0_TXBITSTUFF_EN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_TXBITSTUFF_EN bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_PLL_EN

Set to 1 to enable the USB PLL

XS1_USB_PHY_CFG0_PLL_EN_SHIFT

XS1_USB_PHY_CFG0_PLL_EN_SIZE

XS1_USB_PHY_CFG0_PLL_EN_MASK

XS1_USB_PHY_CFG0_PLL_EN(x)

Extract the USB_PHY_CFG0_PLL_EN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_PLL_EN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_PLL_EN bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_LPM_ALIVE

Set to 1 to enable USB LPM

XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT

XS1_USB_PHY_CFG0_LPM_ALIVE_SIZE

XS1_USB_PHY_CFG0_LPM_ALIVE_MASK

XS1_USB_PHY_CFG0_LPM_ALIVE(x)

Extract the USB_PHY_CFG0_LPM_ALIVE bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_LPM_ALIVE_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_LPM_ALIVE bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_IDPAD_EN

Set to 1 to enable the ID PAD

XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT

XS1_USB_PHY_CFG0_IDPAD_EN_SIZE

XS1_USB_PHY_CFG0_IDPAD_EN_MASK

XS1_USB_PHY_CFG0_IDPAD_EN(x)

Extract the USB_PHY_CFG0_IDPAD_EN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_IDPAD_EN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_IDPAD_EN bitfield into a packed word x and return the packed field.

USB_PHY_CFG0_XTLSEL

Oscillator freqeuncy.

Set to: 0 (10MHz), 1 (12MHz), 2 (25MHz), 3~(30MHz), 4 (19.2MHz), 5 (24MHz), 6 (27MHz), or 7 (40MHz).

XS1_USB_PHY_CFG0_XTLSEL_SHIFT

XS1_USB_PHY_CFG0_XTLSEL_SIZE

XS1_USB_PHY_CFG0_XTLSEL_MASK

XS1_USB_PHY_CFG0_XTLSEL(x)

Extract the USB_PHY_CFG0_XTLSEL bitfield from a packed word x and return it.

XS1_USB_PHY_CFG0_XTLSEL_SET(x, v)

Pack the value (v) of the USB_PHY_CFG0_XTLSEL bitfield into a packed word x and return the packed field.

USB_PHY_CFG2_PONRST

USB PHY reset, set to 1 to take the PHY out of reset

XS1_USB_PHY_CFG2_PONRST_SHIFT

XS1_USB_PHY_CFG2_PONRST_SIZE

XS1_USB_PHY_CFG2_PONRST_MASK

XS1_USB_PHY_CFG2_PONRST(x)

Extract the USB_PHY_CFG2_PONRST bitfield from a packed word x and return it.

XS1_USB_PHY_CFG2_PONRST_SET(x, v)

Pack the value (v) of the USB_PHY_CFG2_PONRST bitfield into a packed word x and return the packed field.

USB_PHY_CFG2_UTMI_RESET

UTMI reset, set to 0 to take UTMI out of reset

XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT

XS1_USB_PHY_CFG2_UTMI_RESET_SIZE

XS1_USB_PHY_CFG2_UTMI_RESET_MASK

XS1_USB_PHY_CFG2_UTMI_RESET(x)

Extract the USB_PHY_CFG2_UTMI_RESET bitfield from a packed word x and return it.

XS1_USB_PHY_CFG2_UTMI_RESET_SET(x, v)

Pack the value (v) of the USB_PHY_CFG2_UTMI_RESET bitfield into a packed word x and return the packed field.

USB_PHY_CFG3_VCONTROL

USB VCONTROL

XS1_USB_PHY_CFG3_VCONTROL_SHIFT

XS1_USB_PHY_CFG3_VCONTROL_SIZE

XS1_USB_PHY_CFG3_VCONTROL_MASK

XS1_USB_PHY_CFG3_VCONTROL(x)

Extract the USB_PHY_CFG3_VCONTROL bitfield from a packed word x and return it.

XS1_USB_PHY_CFG3_VCONTROL_SET(x, v)

Pack the value (v) of the USB_PHY_CFG3_VCONTROL bitfield into a packed word x and return the packed field.

USB_PHY_CFG3_EXTERNAL_TEST_MODE

USB EXTERNAL TEST MODE

XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT

XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SIZE

XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK

XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE(x)

Extract the USB_PHY_CFG3_EXTERNAL_TEST_MODE bitfield from a packed word x and return it.

XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SET(x, v)

Pack the value (v) of the USB_PHY_CFG3_EXTERNAL_TEST_MODE bitfield into a packed word x and return the packed field.

USB_PHY_CFG3_LS_EN

USB LS Enable

XS1_USB_PHY_CFG3_LS_EN_SHIFT

XS1_USB_PHY_CFG3_LS_EN_SIZE

XS1_USB_PHY_CFG3_LS_EN_MASK

XS1_USB_PHY_CFG3_LS_EN(x)

Extract the USB_PHY_CFG3_LS_EN bitfield from a packed word x and return it.

XS1_USB_PHY_CFG3_LS_EN_SET(x, v)

Pack the value (v) of the USB_PHY_CFG3_LS_EN bitfield into a packed word x and return the packed field.

USB_PHY_CFG3_UTMI_VCONTROLLOADM

USB UTMI VCONTROLLOADM

XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT

XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SIZE

XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK

XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM(x)

Extract the USB_PHY_CFG3_UTMI_VCONTROLLOADM bitfield from a packed word x and return it.

XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SET(x, v)

Pack the value (v) of the USB_PHY_CFG3_UTMI_VCONTROLLOADM bitfield into a packed word x and return the packed field.

USB_PHY_CFG3_HS_BIST_MODE

USB HS BIST Mode

XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT

XS1_USB_PHY_CFG3_HS_BIST_MODE_SIZE

XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK

XS1_USB_PHY_CFG3_HS_BIST_MODE(x)

Extract the USB_PHY_CFG3_HS_BIST_MODE bitfield from a packed word x and return it.

XS1_USB_PHY_CFG3_HS_BIST_MODE_SET(x, v)

Pack the value (v) of the USB_PHY_CFG3_HS_BIST_MODE bitfield into a packed word x and return the packed field.

USB_SHIM_CFG_AND_RXV_RXA

When enabled RxValid output to xCore is AND’d with RxActive

XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT

XS1_USB_SHIM_CFG_AND_RXV_RXA_SIZE

XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK

XS1_USB_SHIM_CFG_AND_RXV_RXA(x)

Extract the USB_SHIM_CFG_AND_RXV_RXA bitfield from a packed word x and return it.

XS1_USB_SHIM_CFG_AND_RXV_RXA_SET(x, v)

Pack the value (v) of the USB_SHIM_CFG_AND_RXV_RXA bitfield into a packed word x and return the packed field.

USB_SHIM_CFG_FLAG_MODE

USB flag mode selection: 1 selects linestate; 0 selects RxActive and RxValid

XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT

XS1_USB_SHIM_CFG_FLAG_MODE_SIZE

XS1_USB_SHIM_CFG_FLAG_MODE_MASK

XS1_USB_SHIM_CFG_FLAG_MODE(x)

Extract the USB_SHIM_CFG_FLAG_MODE bitfield from a packed word x and return it.

XS1_USB_SHIM_CFG_FLAG_MODE_SET(x, v)

Pack the value (v) of the USB_SHIM_CFG_FLAG_MODE bitfield into a packed word x and return the packed field.

USB_PHY_STATUS_UTMI_LINESTATE

The UTMI line state; 0: SE0, 1: J, 2: K, 3: SE1

XS1_USB_PHY_STATUS_UTMI_LINESTATE_SHIFT

XS1_USB_PHY_STATUS_UTMI_LINESTATE_SIZE

XS1_USB_PHY_STATUS_UTMI_LINESTATE_MASK

XS1_USB_PHY_STATUS_UTMI_LINESTATE(x)

Extract the USB_PHY_STATUS_UTMI_LINESTATE bitfield from a packed word x and return it.

XS1_USB_PHY_STATUS_UTMI_LINESTATE_SET(x, v)

Pack the value (v) of the USB_PHY_STATUS_UTMI_LINESTATE bitfield into a packed word x and return the packed field.

USB_PHY_STATUS_HOSTDISCONNECT

Set to 1 if no peripheral is connected

XS1_USB_PHY_STATUS_HOSTDISCONNECT_SHIFT

XS1_USB_PHY_STATUS_HOSTDISCONNECT_SIZE

XS1_USB_PHY_STATUS_HOSTDISCONNECT_MASK

XS1_USB_PHY_STATUS_HOSTDISCONNECT(x)

Extract the USB_PHY_STATUS_HOSTDISCONNECT bitfield from a packed word x and return it.

XS1_USB_PHY_STATUS_HOSTDISCONNECT_SET(x, v)

Pack the value (v) of the USB_PHY_STATUS_HOSTDISCONNECT bitfield into a packed word x and return the packed field.

USB_PHY_STATUS_IDPAD

1 if resistance of IDPAD to ground is > 100 kOhm (mini B plug)

XS1_USB_PHY_STATUS_IDPAD_SHIFT

XS1_USB_PHY_STATUS_IDPAD_SIZE

XS1_USB_PHY_STATUS_IDPAD_MASK

XS1_USB_PHY_STATUS_IDPAD(x)

Extract the USB_PHY_STATUS_IDPAD bitfield from a packed word x and return it.

XS1_USB_PHY_STATUS_IDPAD_SET(x, v)

Pack the value (v) of the USB_PHY_STATUS_IDPAD bitfield into a packed word x and return the packed field.

USB_PHY_STATUS_BIST_OK

1 if BIST succeeded

XS1_USB_PHY_STATUS_BIST_OK_SHIFT

XS1_USB_PHY_STATUS_BIST_OK_SIZE

XS1_USB_PHY_STATUS_BIST_OK_MASK

XS1_USB_PHY_STATUS_BIST_OK(x)

Extract the USB_PHY_STATUS_BIST_OK bitfield from a packed word x and return it.

XS1_USB_PHY_STATUS_BIST_OK_SET(x, v)

Pack the value (v) of the USB_PHY_STATUS_BIST_OK bitfield into a packed word x and return the packed field.

USB_PHY_STATUS_DEBUG_OUT

Debug output signals

XS1_USB_PHY_STATUS_DEBUG_OUT_SHIFT

XS1_USB_PHY_STATUS_DEBUG_OUT_SIZE

XS1_USB_PHY_STATUS_DEBUG_OUT_MASK

XS1_USB_PHY_STATUS_DEBUG_OUT(x)

Extract the USB_PHY_STATUS_DEBUG_OUT bitfield from a packed word x and return it.

XS1_USB_PHY_STATUS_DEBUG_OUT_SET(x, v)

Pack the value (v) of the USB_PHY_STATUS_DEBUG_OUT bitfield into a packed word x and return the packed field.

WATCHDOG_COUNT_ENABLE

Set this bit to 1 to enable the watchdog counter.

XS1_WATCHDOG_COUNT_ENABLE_SHIFT

XS1_WATCHDOG_COUNT_ENABLE_SIZE

XS1_WATCHDOG_COUNT_ENABLE_MASK

XS1_WATCHDOG_COUNT_ENABLE(x)

Extract the WATCHDOG_COUNT_ENABLE bitfield from a packed word x and return it.

XS1_WATCHDOG_COUNT_ENABLE_SET(x, v)

Pack the value (v) of the WATCHDOG_COUNT_ENABLE bitfield into a packed word x and return the packed field.

WATCHDOG_TRIGGER_ENABLE

Set this bit to 1 to enable the watchdog to actually reset the chip.

XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT

XS1_WATCHDOG_TRIGGER_ENABLE_SIZE

XS1_WATCHDOG_TRIGGER_ENABLE_MASK

XS1_WATCHDOG_TRIGGER_ENABLE(x)

Extract the WATCHDOG_TRIGGER_ENABLE bitfield from a packed word x and return it.

XS1_WATCHDOG_TRIGGER_ENABLE_SET(x, v)

Pack the value (v) of the WATCHDOG_TRIGGER_ENABLE bitfield into a packed word x and return the packed field.

WATCHDOG_PRESCALER_VALUE

This is the current count of the prescaler.

One is added one every input clock edge on the oscillator (XIN). When it reaches the prescaler wrap value (see below), it resets to zero and one is subtracted from the watchdog count (see below).

XS1_WATCHDOG_PRESCALER_VALUE_SHIFT

XS1_WATCHDOG_PRESCALER_VALUE_SIZE

XS1_WATCHDOG_PRESCALER_VALUE_MASK

XS1_WATCHDOG_PRESCALER_VALUE(x)

Extract the WATCHDOG_PRESCALER_VALUE bitfield from a packed word x and return it.

XS1_WATCHDOG_PRESCALER_VALUE_SET(x, v)

Pack the value (v) of the WATCHDOG_PRESCALER_VALUE bitfield into a packed word x and return the packed field.

WATCHDOG_PRESCALER_WRAP_VALUE

This is the prescaler divider.

The input clock on XIN is divided by this value plus one, before being used to adjust the watchdog count (see below).

XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT

XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SIZE

XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK

XS1_WATCHDOG_PRESCALER_WRAP_VALUE(x)

Extract the WATCHDOG_PRESCALER_WRAP_VALUE bitfield from a packed word x and return it.

XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SET(x, v)

Pack the value (v) of the WATCHDOG_PRESCALER_WRAP_VALUE bitfield into a packed word x and return the packed field.

WATCHDOG_COUNT_VALUE

This is the watchdog counter.

It counts down every PRESCALER_WRAP_VALUE input clock edges. When it reaches zero the chip is reset. The maximum time for the watchdog is 2^{12} \times 2^{16} = 2^{28} = 268,435,456 input clocks.

XS1_WATCHDOG_COUNT_VALUE_SHIFT

XS1_WATCHDOG_COUNT_VALUE_SIZE

XS1_WATCHDOG_COUNT_VALUE_MASK

XS1_WATCHDOG_COUNT_VALUE(x)

Extract the WATCHDOG_COUNT_VALUE bitfield from a packed word x and return it.

XS1_WATCHDOG_COUNT_VALUE_SET(x, v)

Pack the value (v) of the WATCHDOG_COUNT_VALUE bitfield into a packed word x and return the packed field.

WATCHDOG_HAS_TRIGGERED

When 1, the watchdog has been triggered.

This bit is only reset to 0 on a power-on-reset.

XS1_WATCHDOG_HAS_TRIGGERED_SHIFT

XS1_WATCHDOG_HAS_TRIGGERED_SIZE

XS1_WATCHDOG_HAS_TRIGGERED_MASK

XS1_WATCHDOG_HAS_TRIGGERED(x)

Extract the WATCHDOG_HAS_TRIGGERED bitfield from a packed word x and return it.

XS1_WATCHDOG_HAS_TRIGGERED_SET(x, v)

Pack the value (v) of the WATCHDOG_HAS_TRIGGERED bitfield into a packed word x and return the packed field.

MIPI_STATUS0_OSC_CLK_ACT

Test mode osc clock act

XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT

XS1_MIPI_STATUS0_OSC_CLK_ACT_SIZE

XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK

XS1_MIPI_STATUS0_OSC_CLK_ACT(x)

Extract the MIPI_STATUS0_OSC_CLK_ACT bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_OSC_CLK_ACT_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_OSC_CLK_ACT bitfield into a packed word x and return the packed field.

MIPI_STATUS0_OSC_CLK_READY

Test mode osc clock ready

XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT

XS1_MIPI_STATUS0_OSC_CLK_READY_SIZE

XS1_MIPI_STATUS0_OSC_CLK_READY_MASK

XS1_MIPI_STATUS0_OSC_CLK_READY(x)

Extract the MIPI_STATUS0_OSC_CLK_READY bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_OSC_CLK_READY_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_OSC_CLK_READY bitfield into a packed word x and return the packed field.

MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G

Test mode bit clk greater than 2400G

XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT

XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SIZE

XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK

XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G(x)

Extract the MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G bitfield into a packed word x and return the packed field.

MIPI_STATUS0_DATA_CORRECT_LAN0

Test mode data correct lan0

XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT

XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SIZE

XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK

XS1_MIPI_STATUS0_DATA_CORRECT_LAN0(x)

Extract the MIPI_STATUS0_DATA_CORRECT_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_DATA_CORRECT_LAN0 bitfield into a packed word x and return the packed field.

MIPI_STATUS0_DATA_CORRECT_LAN1

Test mode data correct lan1

XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT

XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SIZE

XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK

XS1_MIPI_STATUS0_DATA_CORRECT_LAN1(x)

Extract the MIPI_STATUS0_DATA_CORRECT_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_DATA_CORRECT_LAN1 bitfield into a packed word x and return the packed field.

MIPI_STATUS0_DATA_CORRECT_LAN2

Test mode data correct lan2

XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT

XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SIZE

XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK

XS1_MIPI_STATUS0_DATA_CORRECT_LAN2(x)

Extract the MIPI_STATUS0_DATA_CORRECT_LAN2 bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_DATA_CORRECT_LAN2 bitfield into a packed word x and return the packed field.

MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C

Test mode da cdphy r100 control0 2d1c

XS1_MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C_SHIFT

XS1_MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C_SIZE

XS1_MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C_MASK

XS1_MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C(x)

Extract the MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C bitfield into a packed word x and return the packed field.

MIPI_STATUS0_STOPSTATE_CLK

Clock lane is in the stop state

XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT

XS1_MIPI_STATUS0_STOPSTATE_CLK_SIZE

XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK

XS1_MIPI_STATUS0_STOPSTATE_CLK(x)

Extract the MIPI_STATUS0_STOPSTATE_CLK bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_STOPSTATE_CLK_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_STOPSTATE_CLK bitfield into a packed word x and return the packed field.

MIPI_STATUS0_STOPSTATE_LAN0

Lane 0 is in the stop state

XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT

XS1_MIPI_STATUS0_STOPSTATE_LAN0_SIZE

XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK

XS1_MIPI_STATUS0_STOPSTATE_LAN0(x)

Extract the MIPI_STATUS0_STOPSTATE_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_STOPSTATE_LAN0_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_STOPSTATE_LAN0 bitfield into a packed word x and return the packed field.

MIPI_STATUS0_STOPSTATE_LAN1

Lane 1 is in the stop state

XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT

XS1_MIPI_STATUS0_STOPSTATE_LAN1_SIZE

XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK

XS1_MIPI_STATUS0_STOPSTATE_LAN1(x)

Extract the MIPI_STATUS0_STOPSTATE_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_STATUS0_STOPSTATE_LAN1_SET(x, v)

Pack the value (v) of the MIPI_STATUS0_STOPSTATE_LAN1 bitfield into a packed word x and return the packed field.

MIPI_SHIM_STATUS_REG

Set to 1 if an overflow has been detected in the DEMUXER.

This is not recoverable, and indicates that the MIPI_CLK is too slow for the rate at which data is received.

XS1_MIPI_SHIM_STATUS_REG_SHIFT

XS1_MIPI_SHIM_STATUS_REG_SIZE

XS1_MIPI_SHIM_STATUS_REG_MASK

XS1_MIPI_SHIM_STATUS_REG(x)

Extract the MIPI_SHIM_STATUS_REG bitfield from a packed word x and return it.

XS1_MIPI_SHIM_STATUS_REG_SET(x, v)

Pack the value (v) of the MIPI_SHIM_STATUS_REG bitfield into a packed word x and return the packed field.

MIPI_SHIM_CFG0_PIXEL_DEMUX_EN

Set to 1 to enable the MIPI shim to demultiplex data according to the demux mode and stuff fields.

Demuxing is only applied to packets that have the correct datatype.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SIZE

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN(x)

Extract the MIPI_SHIM_CFG0_PIXEL_DEMUX_EN bitfield from a packed word x and return it.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SET(x, v)

Pack the value (v) of the MIPI_SHIM_CFG0_PIXEL_DEMUX_EN bitfield into a packed word x and return the packed field.

MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE

This field needs to be set to the CSI-2 packet type that needs to be demuxed.

Only packets with a matching type are demultiplexed.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SIZE

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE(x)

Extract the MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE bitfield from a packed word x and return it.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SET(x, v)

Pack the value (v) of the MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE bitfield into a packed word x and return the packed field.

MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE

Specifies how the demultiplexer operates.

The modes supported are 10to16, 12to16, 14to16, rgb565to888, rgb888to888.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SIZE

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE(x)

Extract the MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE bitfield from a packed word x and return it.

XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SET(x, v)

Pack the value (v) of the MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE bitfield into a packed word x and return the packed field.

MIPI_SHIM_DEMUX_STUFF

Set to 1 to add an extra data byte after every RGB565 or RGB888 pixel.

This will align pixels to a 32-bit word.

XS1_MIPI_SHIM_DEMUX_STUFF_SHIFT

XS1_MIPI_SHIM_DEMUX_STUFF_SIZE

XS1_MIPI_SHIM_DEMUX_STUFF_MASK

XS1_MIPI_SHIM_DEMUX_STUFF(x)

Extract the MIPI_SHIM_DEMUX_STUFF bitfield from a packed word x and return it.

XS1_MIPI_SHIM_DEMUX_STUFF_SET(x, v)

Pack the value (v) of the MIPI_SHIM_DEMUX_STUFF bitfield into a packed word x and return the packed field.

MIPI_SHIM_BIAS

Set to 1 to offset the output pixels with -0x80 (for 8-bit outputs) or -0x8000 (for 16-bit outputs).

This can be used to make unsigned data signed around zero.

XS1_MIPI_SHIM_BIAS_SHIFT

XS1_MIPI_SHIM_BIAS_SIZE

XS1_MIPI_SHIM_BIAS_MASK

XS1_MIPI_SHIM_BIAS(x)

Extract the MIPI_SHIM_BIAS bitfield from a packed word x and return it.

XS1_MIPI_SHIM_BIAS_SET(x, v)

Pack the value (v) of the MIPI_SHIM_BIAS bitfield into a packed word x and return the packed field.

MIPI_SHIM_CFG0_SEL_DEBUG_OUT

MIPI shim config0 sel debug out

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SIZE

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT(x)

Extract the MIPI_SHIM_CFG0_SEL_DEBUG_OUT bitfield from a packed word x and return it.

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SET(x, v)

Pack the value (v) of the MIPI_SHIM_CFG0_SEL_DEBUG_OUT bitfield into a packed word x and return the packed field.

MIPI_SHIM_CFG0_SEL_DEBUG

MIPI shim config0 sel debug

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SIZE

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK

XS1_MIPI_SHIM_CFG0_SEL_DEBUG(x)

Extract the MIPI_SHIM_CFG0_SEL_DEBUG bitfield from a packed word x and return it.

XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SET(x, v)

Pack the value (v) of the MIPI_SHIM_CFG0_SEL_DEBUG bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG0_HW_RSTN

Reset, set to 1 to take the MIPI PHY out of reset

XS1_MIPI_DPHY_CFG0_HW_RSTN_SHIFT

XS1_MIPI_DPHY_CFG0_HW_RSTN_SIZE

XS1_MIPI_DPHY_CFG0_HW_RSTN_MASK

XS1_MIPI_DPHY_CFG0_HW_RSTN(x)

Extract the MIPI_DPHY_CFG0_HW_RSTN bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG0_HW_RSTN_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG0_HW_RSTN bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON

Set to 1

XS1_MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON_SHIFT

XS1_MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON_SIZE

XS1_MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON_MASK

XS1_MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON(x)

Extract the MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG1_MP_TEST_EN

MIPI dphy config1 mp test mode enable

XS1_MIPI_DPHY_CFG1_MP_TEST_EN_SHIFT

XS1_MIPI_DPHY_CFG1_MP_TEST_EN_SIZE

XS1_MIPI_DPHY_CFG1_MP_TEST_EN_MASK

XS1_MIPI_DPHY_CFG1_MP_TEST_EN(x)

Extract the MIPI_DPHY_CFG1_MP_TEST_EN bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG1_MP_TEST_EN_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG1_MP_TEST_EN bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG1_MP_TEST_MODE_SEL

MIPI dphy config1 mp test mode select

XS1_MIPI_DPHY_CFG1_MP_TEST_MODE_SEL_SHIFT

XS1_MIPI_DPHY_CFG1_MP_TEST_MODE_SEL_SIZE

XS1_MIPI_DPHY_CFG1_MP_TEST_MODE_SEL_MASK

XS1_MIPI_DPHY_CFG1_MP_TEST_MODE_SEL(x)

Extract the MIPI_DPHY_CFG1_MP_TEST_MODE_SEL bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG1_MP_TEST_MODE_SEL_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG1_MP_TEST_MODE_SEL bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN

MIPI dphy config1 cdphy r100 control 0 2d1c efuse enable

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN_SHIFT

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN_SIZE

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN_MASK

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN(x)

Extract the MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN

MIPI dphy config1 cdphy r100 control 0 2d1c efuse in

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN_SHIFT

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN_SIZE

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN_MASK

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN(x)

Extract the MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG2_PLL_CLK_SEL

MIPI dphy config2 pll clock select

XS1_MIPI_DPHY_CFG2_PLL_CLK_SEL_SHIFT

XS1_MIPI_DPHY_CFG2_PLL_CLK_SEL_SIZE

XS1_MIPI_DPHY_CFG2_PLL_CLK_SEL_MASK

XS1_MIPI_DPHY_CFG2_PLL_CLK_SEL(x)

Extract the MIPI_DPHY_CFG2_PLL_CLK_SEL bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG2_PLL_CLK_SEL_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG2_PLL_CLK_SEL bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_LANE_SWAP_CLK

The DP/DN pair over which to input the clock

XS1_MIPI_DPHY_CFG3_LANE_SWAP_CLK_SHIFT

XS1_MIPI_DPHY_CFG3_LANE_SWAP_CLK_SIZE

XS1_MIPI_DPHY_CFG3_LANE_SWAP_CLK_MASK

XS1_MIPI_DPHY_CFG3_LANE_SWAP_CLK(x)

Extract the MIPI_DPHY_CFG3_LANE_SWAP_CLK bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_LANE_SWAP_CLK_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_LANE_SWAP_CLK bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_LANE_SWAP_LAN0

The DP/DN pair over which to input lane 0

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN0_SHIFT

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN0_SIZE

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN0_MASK

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN0(x)

Extract the MIPI_DPHY_CFG3_LANE_SWAP_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN0_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_LANE_SWAP_LAN0 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_LANE_SWAP_LAN1

The DP/DN pair over which to input lane 1 (if two lanes are needed)

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN1_SHIFT

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN1_SIZE

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN1_MASK

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN1(x)

Extract the MIPI_DPHY_CFG3_LANE_SWAP_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_LANE_SWAP_LAN1_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_LANE_SWAP_LAN1 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_DPDN_SWAP_CLK

Set to 1 to swap the DN/DP pair on the clock lane

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_CLK_SHIFT

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_CLK_SIZE

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_CLK_MASK

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_CLK(x)

Extract the MIPI_DPHY_CFG3_DPDN_SWAP_CLK bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_CLK_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_DPDN_SWAP_CLK bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_DPDN_SWAP_LAN0

Set to 1 to swap the DN/DP pair on the lane 0

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN0_SHIFT

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN0_SIZE

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN0_MASK

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN0(x)

Extract the MIPI_DPHY_CFG3_DPDN_SWAP_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN0_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_DPDN_SWAP_LAN0 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_DPDN_SWAP_LAN1

Set to 1 to swap the DN/DP pair on the lane 1

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN1_SHIFT

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN1_SIZE

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN1_MASK

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN1(x)

Extract the MIPI_DPHY_CFG3_DPDN_SWAP_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_DPDN_SWAP_LAN1_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_DPDN_SWAP_LAN1 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_ENABLE_CLK

Set to 0 to disable the clock lane receiver

XS1_MIPI_DPHY_CFG3_ENABLE_CLK_SHIFT

XS1_MIPI_DPHY_CFG3_ENABLE_CLK_SIZE

XS1_MIPI_DPHY_CFG3_ENABLE_CLK_MASK

XS1_MIPI_DPHY_CFG3_ENABLE_CLK(x)

Extract the MIPI_DPHY_CFG3_ENABLE_CLK bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_ENABLE_CLK_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_ENABLE_CLK bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_ENABLE_LAN0

Set to 0 to disable lane 0 receiver

XS1_MIPI_DPHY_CFG3_ENABLE_LAN0_SHIFT

XS1_MIPI_DPHY_CFG3_ENABLE_LAN0_SIZE

XS1_MIPI_DPHY_CFG3_ENABLE_LAN0_MASK

XS1_MIPI_DPHY_CFG3_ENABLE_LAN0(x)

Extract the MIPI_DPHY_CFG3_ENABLE_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_ENABLE_LAN0_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_ENABLE_LAN0 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG3_ENABLE_LAN1

Set to 0 to disable lane 1 receiver

XS1_MIPI_DPHY_CFG3_ENABLE_LAN1_SHIFT

XS1_MIPI_DPHY_CFG3_ENABLE_LAN1_SIZE

XS1_MIPI_DPHY_CFG3_ENABLE_LAN1_MASK

XS1_MIPI_DPHY_CFG3_ENABLE_LAN1(x)

Extract the MIPI_DPHY_CFG3_ENABLE_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG3_ENABLE_LAN1_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG3_ENABLE_LAN1 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK

MIPI dphy Tclk-settle for clock

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK_SHIFT

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK_SIZE

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK_MASK

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK(x)

Extract the MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0

MIPI dphy Tclk-settle in lane 0

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0_SHIFT

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0_SIZE

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0_MASK

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0(x)

Extract the MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1

MIPI dphy Tclk-settle in lane 1

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1_SHIFT

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1_SIZE

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1_MASK

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1(x)

Extract the MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1 bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1 bitfield into a packed word x and return the packed field.

MIPI_DPHY_CFG5_DEBUG_MODE_SEL

MIPI dphy debug mode select

XS1_MIPI_DPHY_CFG5_DEBUG_MODE_SEL_SHIFT

XS1_MIPI_DPHY_CFG5_DEBUG_MODE_SEL_SIZE

XS1_MIPI_DPHY_CFG5_DEBUG_MODE_SEL_MASK

XS1_MIPI_DPHY_CFG5_DEBUG_MODE_SEL(x)

Extract the MIPI_DPHY_CFG5_DEBUG_MODE_SEL bitfield from a packed word x and return it.

XS1_MIPI_DPHY_CFG5_DEBUG_MODE_SEL_SET(x, v)

Pack the value (v) of the MIPI_DPHY_CFG5_DEBUG_MODE_SEL bitfield into a packed word x and return the packed field.

LPDDR_IID_ENABLE

Two 8-bit masks, one bit per thread.

Top eight bits enable instructions to be routed through a specified queue, bottom eight bits enable data to be routed through a specified queue.

XS1_LPDDR_IID_ENABLE_SHIFT

XS1_LPDDR_IID_ENABLE_SIZE

XS1_LPDDR_IID_ENABLE_MASK

XS1_LPDDR_IID_ENABLE(x)

Extract the LPDDR_IID_ENABLE bitfield from a packed word x and return it.

XS1_LPDDR_IID_ENABLE_SET(x, v)

Pack the value (v) of the LPDDR_IID_ENABLE bitfield into a packed word x and return the packed field.

LPDDR_IID_0_7

Four bits per thread.

Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_LPDDR_IID_0_7_SHIFT

XS1_LPDDR_IID_0_7_SIZE

XS1_LPDDR_IID_0_7_MASK

XS1_LPDDR_IID_0_7(x)

Extract the LPDDR_IID_0_7 bitfield from a packed word x and return it.

XS1_LPDDR_IID_0_7_SET(x, v)

Pack the value (v) of the LPDDR_IID_0_7 bitfield into a packed word x and return the packed field.

LPDDR_IID_8_15

Four bits per thread.

Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_LPDDR_IID_8_15_SHIFT

XS1_LPDDR_IID_8_15_SIZE

XS1_LPDDR_IID_8_15_MASK

XS1_LPDDR_IID_8_15(x)

Extract the LPDDR_IID_8_15 bitfield from a packed word x and return it.

XS1_LPDDR_IID_8_15_SET(x, v)

Pack the value (v) of the LPDDR_IID_8_15 bitfield into a packed word x and return the packed field.

LPDDR_QUEUE_CONT

Slow sys clock.

Set this bit if the tile clock is less than the LPDDR clock.

XS1_LPDDR_QUEUE_CONT_SHIFT

XS1_LPDDR_QUEUE_CONT_SIZE

XS1_LPDDR_QUEUE_CONT_MASK

XS1_LPDDR_QUEUE_CONT(x)

Extract the LPDDR_QUEUE_CONT bitfield from a packed word x and return it.

XS1_LPDDR_QUEUE_CONT_SET(x, v)

Pack the value (v) of the LPDDR_QUEUE_CONT bitfield into a packed word x and return the packed field.

LPDDR_RO_PRI

Priority for RO queue.

Zero is lowest priority.

XS1_LPDDR_RO_PRI_SHIFT

XS1_LPDDR_RO_PRI_SIZE

XS1_LPDDR_RO_PRI_MASK

XS1_LPDDR_RO_PRI(x)

Extract the LPDDR_RO_PRI bitfield from a packed word x and return it.

XS1_LPDDR_RO_PRI_SET(x, v)

Pack the value (v) of the LPDDR_RO_PRI bitfield into a packed word x and return the packed field.

LPDDR_RW0_PRI

Priority for RW queue 0.

Zero is lowest priority.

XS1_LPDDR_RW0_PRI_SHIFT

XS1_LPDDR_RW0_PRI_SIZE

XS1_LPDDR_RW0_PRI_MASK

XS1_LPDDR_RW0_PRI(x)

Extract the LPDDR_RW0_PRI bitfield from a packed word x and return it.

XS1_LPDDR_RW0_PRI_SET(x, v)

Pack the value (v) of the LPDDR_RW0_PRI bitfield into a packed word x and return the packed field.

LPDDR_RW1_PRI

Priority for RW queue 1.

Zero is lowest priority.

XS1_LPDDR_RW1_PRI_SHIFT

XS1_LPDDR_RW1_PRI_SIZE

XS1_LPDDR_RW1_PRI_MASK

XS1_LPDDR_RW1_PRI(x)

Extract the LPDDR_RW1_PRI bitfield from a packed word x and return it.

XS1_LPDDR_RW1_PRI_SET(x, v)

Pack the value (v) of the LPDDR_RW1_PRI bitfield into a packed word x and return the packed field.

LPDDR_TOUT

Maximum number of transactions until a queue is served.

Set to 0 to disable a timeout

XS1_LPDDR_TOUT_SHIFT

XS1_LPDDR_TOUT_SIZE

XS1_LPDDR_TOUT_MASK

XS1_LPDDR_TOUT(x)

Extract the LPDDR_TOUT bitfield from a packed word x and return it.

XS1_LPDDR_TOUT_SET(x, v)

Pack the value (v) of the LPDDR_TOUT bitfield into a packed word x and return the packed field.

LPDDR_MTG_CMD

MTG Commands status for CSR Read

XS1_LPDDR_MTG_CMD_SHIFT

XS1_LPDDR_MTG_CMD_SIZE

XS1_LPDDR_MTG_CMD_MASK

XS1_LPDDR_MTG_CMD(x)

Extract the LPDDR_MTG_CMD bitfield from a packed word x and return it.

XS1_LPDDR_MTG_CMD_SET(x, v)

Pack the value (v) of the LPDDR_MTG_CMD bitfield into a packed word x and return the packed field.

LPDDR_DLL_CONTROL

DLL Control

XS1_LPDDR_DLL_CONTROL_SHIFT

XS1_LPDDR_DLL_CONTROL_SIZE

XS1_LPDDR_DLL_CONTROL_MASK

XS1_LPDDR_DLL_CONTROL(x)

Extract the LPDDR_DLL_CONTROL bitfield from a packed word x and return it.

XS1_LPDDR_DLL_CONTROL_SET(x, v)

Pack the value (v) of the LPDDR_DLL_CONTROL bitfield into a packed word x and return the packed field.

LPDDR_DLL_MEASUREMENT_STATUS

Measurement status of the DLL

XS1_LPDDR_DLL_MEASUREMENT_STATUS_SHIFT

XS1_LPDDR_DLL_MEASUREMENT_STATUS_SIZE

XS1_LPDDR_DLL_MEASUREMENT_STATUS_MASK

XS1_LPDDR_DLL_MEASUREMENT_STATUS(x)

Extract the LPDDR_DLL_MEASUREMENT_STATUS bitfield from a packed word x and return it.

XS1_LPDDR_DLL_MEASUREMENT_STATUS_SET(x, v)

Pack the value (v) of the LPDDR_DLL_MEASUREMENT_STATUS bitfield into a packed word x and return the packed field.

LPDDR_DLL_MANUAL_CONTROL

DLL Manual Control

XS1_LPDDR_DLL_MANUAL_CONTROL_SHIFT

XS1_LPDDR_DLL_MANUAL_CONTROL_SIZE

XS1_LPDDR_DLL_MANUAL_CONTROL_MASK

XS1_LPDDR_DLL_MANUAL_CONTROL(x)

Extract the LPDDR_DLL_MANUAL_CONTROL bitfield from a packed word x and return it.

XS1_LPDDR_DLL_MANUAL_CONTROL_SET(x, v)

Pack the value (v) of the LPDDR_DLL_MANUAL_CONTROL bitfield into a packed word x and return the packed field.

LPDDR_DLL_PHY_CALIBRATION_DATA

DLL Calibration Data

XS1_LPDDR_DLL_PHY_CALIBRATION_DATA_SHIFT

XS1_LPDDR_DLL_PHY_CALIBRATION_DATA_SIZE

XS1_LPDDR_DLL_PHY_CALIBRATION_DATA_MASK

XS1_LPDDR_DLL_PHY_CALIBRATION_DATA(x)

Extract the LPDDR_DLL_PHY_CALIBRATION_DATA bitfield from a packed word x and return it.

XS1_LPDDR_DLL_PHY_CALIBRATION_DATA_SET(x, v)

Pack the value (v) of the LPDDR_DLL_PHY_CALIBRATION_DATA bitfield into a packed word x and return the packed field.

LPDDR_PHY_CONTROL

PHY Control

XS1_LPDDR_PHY_CONTROL_SHIFT

XS1_LPDDR_PHY_CONTROL_SIZE

XS1_LPDDR_PHY_CONTROL_MASK

XS1_LPDDR_PHY_CONTROL(x)

Extract the LPDDR_PHY_CONTROL bitfield from a packed word x and return it.

XS1_LPDDR_PHY_CONTROL_SET(x, v)

Pack the value (v) of the LPDDR_PHY_CONTROL bitfield into a packed word x and return the packed field.

LPDDR_LMR_OPCODE

LMR opcode

XS1_LPDDR_LMR_OPCODE_SHIFT

XS1_LPDDR_LMR_OPCODE_SIZE

XS1_LPDDR_LMR_OPCODE_MASK

XS1_LPDDR_LMR_OPCODE(x)

Extract the LPDDR_LMR_OPCODE bitfield from a packed word x and return it.

XS1_LPDDR_LMR_OPCODE_SET(x, v)

Pack the value (v) of the LPDDR_LMR_OPCODE bitfield into a packed word x and return the packed field.

LPDDR_EMR_OPCODE

EMR opcode

XS1_LPDDR_EMR_OPCODE_SHIFT

XS1_LPDDR_EMR_OPCODE_SIZE

XS1_LPDDR_EMR_OPCODE_MASK

XS1_LPDDR_EMR_OPCODE(x)

Extract the LPDDR_EMR_OPCODE bitfield from a packed word x and return it.

XS1_LPDDR_EMR_OPCODE_SET(x, v)

Pack the value (v) of the LPDDR_EMR_OPCODE bitfield into a packed word x and return the packed field.

LPDDR_PE_TREFI_CNT

LPDDR tREFI clock count

XS1_LPDDR_PE_TREFI_CNT_SHIFT

XS1_LPDDR_PE_TREFI_CNT_SIZE

XS1_LPDDR_PE_TREFI_CNT_MASK

XS1_LPDDR_PE_TREFI_CNT(x)

Extract the LPDDR_PE_TREFI_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TREFI_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TREFI_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRAS_CNT

LPDDR tRAS clock count

XS1_LPDDR_PE_TRAS_CNT_SHIFT

XS1_LPDDR_PE_TRAS_CNT_SIZE

XS1_LPDDR_PE_TRAS_CNT_MASK

XS1_LPDDR_PE_TRAS_CNT(x)

Extract the LPDDR_PE_TRAS_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRAS_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRAS_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TXSR_CNT

LPDDR tXSR clock count

XS1_LPDDR_PE_TXSR_CNT_SHIFT

XS1_LPDDR_PE_TXSR_CNT_SIZE

XS1_LPDDR_PE_TXSR_CNT_MASK

XS1_LPDDR_PE_TXSR_CNT(x)

Extract the LPDDR_PE_TXSR_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TXSR_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TXSR_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TWR_CNT

LPDDR tWR clock count

XS1_LPDDR_PE_TWR_CNT_SHIFT

XS1_LPDDR_PE_TWR_CNT_SIZE

XS1_LPDDR_PE_TWR_CNT_MASK

XS1_LPDDR_PE_TWR_CNT(x)

Extract the LPDDR_PE_TWR_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TWR_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TWR_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRC_CNT

LPDDR tRC clock count

XS1_LPDDR_PE_TRC_CNT_SHIFT

XS1_LPDDR_PE_TRC_CNT_SIZE

XS1_LPDDR_PE_TRC_CNT_MASK

XS1_LPDDR_PE_TRC_CNT(x)

Extract the LPDDR_PE_TRC_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRC_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRC_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRCD_CNT

LPDDR tRCD clock count

XS1_LPDDR_PE_TRCD_CNT_SHIFT

XS1_LPDDR_PE_TRCD_CNT_SIZE

XS1_LPDDR_PE_TRCD_CNT_MASK

XS1_LPDDR_PE_TRCD_CNT(x)

Extract the LPDDR_PE_TRCD_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRCD_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRCD_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRP_CNT

LPDDR tRP clock count

XS1_LPDDR_PE_TRP_CNT_SHIFT

XS1_LPDDR_PE_TRP_CNT_SIZE

XS1_LPDDR_PE_TRP_CNT_MASK

XS1_LPDDR_PE_TRP_CNT(x)

Extract the LPDDR_PE_TRP_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRP_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRP_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRFC_CNT

LPDDR tRFC clock count

XS1_LPDDR_PE_TRFC_CNT_SHIFT

XS1_LPDDR_PE_TRFC_CNT_SIZE

XS1_LPDDR_PE_TRFC_CNT_MASK

XS1_LPDDR_PE_TRFC_CNT(x)

Extract the LPDDR_PE_TRFC_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRFC_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRFC_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_TRRD_CNT

LPDDR tRRD clock count

XS1_LPDDR_PE_TRRD_CNT_SHIFT

XS1_LPDDR_PE_TRRD_CNT_SIZE

XS1_LPDDR_PE_TRRD_CNT_MASK

XS1_LPDDR_PE_TRRD_CNT(x)

Extract the LPDDR_PE_TRRD_CNT bitfield from a packed word x and return it.

XS1_LPDDR_PE_TRRD_CNT_SET(x, v)

Pack the value (v) of the LPDDR_PE_TRRD_CNT bitfield into a packed word x and return the packed field.

LPDDR_PE_EN_256M_DEV_SIZE

Enable 256 Mbit device

XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT

XS1_LPDDR_PE_EN_256M_DEV_SIZE_SIZE

XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK

XS1_LPDDR_PE_EN_256M_DEV_SIZE(x)

Extract the LPDDR_PE_EN_256M_DEV_SIZE bitfield from a packed word x and return it.

XS1_LPDDR_PE_EN_256M_DEV_SIZE_SET(x, v)

Pack the value (v) of the LPDDR_PE_EN_256M_DEV_SIZE bitfield into a packed word x and return the packed field.

PADCTRL_RECEIVER_ENABLE

Set to 1 to enable the input receiver

XS1_PADCTRL_RECEIVER_ENABLE_SHIFT

XS1_PADCTRL_RECEIVER_ENABLE_SIZE

XS1_PADCTRL_RECEIVER_ENABLE_MASK

XS1_PADCTRL_RECEIVER_ENABLE(x)

Extract the PADCTRL_RECEIVER_ENABLE bitfield from a packed word x and return it.

XS1_PADCTRL_RECEIVER_ENABLE_SET(x, v)

Pack the value (v) of the PADCTRL_RECEIVER_ENABLE bitfield into a packed word x and return the packed field.

PADCTRL_PULL

Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

XS1_PADCTRL_PULL_SHIFT

XS1_PADCTRL_PULL_SIZE

XS1_PADCTRL_PULL_MASK

XS1_PADCTRL_PULL(x)

Extract the PADCTRL_PULL bitfield from a packed word x and return it.

XS1_PADCTRL_PULL_SET(x, v)

Pack the value (v) of the PADCTRL_PULL bitfield into a packed word x and return the packed field.

PADCTRL_DRIVE_STRENGTH

Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

XS1_PADCTRL_DRIVE_STRENGTH_SHIFT

XS1_PADCTRL_DRIVE_STRENGTH_SIZE

XS1_PADCTRL_DRIVE_STRENGTH_MASK

XS1_PADCTRL_DRIVE_STRENGTH(x)

Extract the PADCTRL_DRIVE_STRENGTH bitfield from a packed word x and return it.

XS1_PADCTRL_DRIVE_STRENGTH_SET(x, v)

Pack the value (v) of the PADCTRL_DRIVE_STRENGTH bitfield into a packed word x and return the packed field.

PADCTRL_SLEW_RATE_CONTROL

Set to 1 to enable slew-rate control

XS1_PADCTRL_SLEW_RATE_CONTROL_SHIFT

XS1_PADCTRL_SLEW_RATE_CONTROL_SIZE

XS1_PADCTRL_SLEW_RATE_CONTROL_MASK

XS1_PADCTRL_SLEW_RATE_CONTROL(x)

Extract the PADCTRL_SLEW_RATE_CONTROL bitfield from a packed word x and return it.

XS1_PADCTRL_SLEW_RATE_CONTROL_SET(x, v)

Pack the value (v) of the PADCTRL_SLEW_RATE_CONTROL bitfield into a packed word x and return the packed field.

PADCTRL_SCHMITT_TRIGGER_ENABLE

Set to 1 to enable the schmitt trigger

XS1_PADCTRL_SCHMITT_TRIGGER_ENABLE_SHIFT

XS1_PADCTRL_SCHMITT_TRIGGER_ENABLE_SIZE

XS1_PADCTRL_SCHMITT_TRIGGER_ENABLE_MASK

XS1_PADCTRL_SCHMITT_TRIGGER_ENABLE(x)

Extract the PADCTRL_SCHMITT_TRIGGER_ENABLE bitfield from a packed word x and return it.

XS1_PADCTRL_SCHMITT_TRIGGER_ENABLE_SET(x, v)

Pack the value (v) of the PADCTRL_SCHMITT_TRIGGER_ENABLE bitfield into a packed word x and return the packed field.

Miscellaneous definitions

group xs3a Miscellaneous Definitions

RESOURCE_TYPES_DEFS

Resource types

XS1_RES_TYPE_PORT

Ports.

XS1_RES_TYPE_TIMER

Timers.

XS1_RES_TYPE_CHANEND

Channel ends.

XS1_RES_TYPE_SYNC

Synchronisers.

XS1_RES_TYPE_THREAD

Threads.

XS1_RES_TYPE_LOCK

Lock.

XS1_RES_TYPE_CLKBLK

Clock source.

XS1_RES_TYPE_COPROC

Co-processor interface/multicycle unit.

XS1_RES_TYPE_SWMEM

SWMEM management resource.

XS1_RES_TYPE_PS

Processor state.

XS1_RES_TYPE_CONFIG

Configuration messages.

XS1_RES_TYPE_INSTRUCTION

Instruction type.

ClockBlocks_DEFS

XS1_CLKBLK_REF

XS1_CLKBLK_1

XS1_CLKBLK_2

XS1_CLKBLK_3

XS1_CLKBLK_4

XS1_CLKBLK_5

XS1_CLKBLK_6

XS1_CLKBLK_7

EXCEPTION_TYPES_DEFS

Exceptions change the normal flow of control; they may be caused by interrupts, errors arising during instruction execution and by system calls.

On an exception, the processor will save the pc and sr in spc and ssr, disable events and interrupts, and start executing an exception handler. The program counter that is saved normally points to the instruction that raised the exception. Two registers are also set. The exception-data (ed) and exception-type (et) will be set to reflect the cause of the exception. The exception handler can choose how to deal with the exception.

In this chapter the different types of exception are listed, together with their representation, their meaning, and the instructions that may cause them.

XS1_ET_LINK_ERROR

Link errors.

XS1_ET_ILLEGAL_PC

see [[XcoreArchTraps#Illegal_PC][Illegal PC]]

XS1_ET_ILLEGAL_INSTRUCTION

see [[XcoreArchTraps#Illegal_instructionsPC][Illegal instructions]]

XS1_ET_ILLEGAL_RESOURCE

thread / synchroniser / channel end / port / lock

XS1_ET_LOAD_STORE

see [[XcoreArchTraps#Illegal_load_store][Illegal load/store]]

XS1_ET_ILLEGAL_PS

see [[XcoreArchMachineState#Traps][Traps]]

XS1_ET_ARITHMETIC

see [[XcoreArchTraps#Arithmetic_exceptions][Arithmetic exceptions]]

XS1_ET_ECALL

see [[XcoreArchTraps#Exception_calls][Exception calls]]

XS1_ET_RESOURCE_DEP

see [[XcoreArchResources#Back_to_Back_Access][Resource dependencies]]

XS1_ET_KCALL

see [[XcoreArchTraps#Kernel_calls][Kernel calls]]

XS1_ET_IOLANE

Indicates exception took place in the resource lane.

T_REG_VALUES_DEFS

Thread state register numbers for debug.

XS1_DBG_T_REG_CP_NUM

XS1_DBG_T_REG_DP_NUM

XS1_DBG_T_REG_SP_NUM

XS1_DBG_T_REG_LR_NUM

XS1_DBG_T_REG_PC_NUM

XS1_DBG_T_REG_SR_NUM

XS1_DBG_T_REG_SPC_NUM

XS1_DBG_T_REG_SSR_NUM

XS1_DBG_T_REG_ET_NUM

XS1_DBG_T_REG_ED_NUM

XS1_DBG_T_REG_SED_NUM

XS1_DBG_T_REG_KEP_NUM

XS1_DBG_T_REG_KSP_NUM

XS1_DBG_T_REG_ID_NUM

XS1_DBG_T_REG_VEC_NUM

STACK_OFFSET_DEFS

Stack offsets for ld,st instructions.

XS1_STACK_OFFSET_SPC

XS1_STACK_OFFSET_SSR

XS1_STACK_OFFSET_SED

XS1_STACK_OFFSET_ET

DBG_CAUSE_DEFS

Types of debug causes, with their value

XS1_DBG_CAUSE_NONE

XS1_DBG_CAUSE_HOST

XS1_DBG_CAUSE_DCALL

XS1_DBG_CAUSE_IBREAK

XS1_DBG_CAUSE_DWATCH

XS1_DBG_CAUSE_RWATCH

DEBUG_COMMANDS_DEFS

Debug commands.

XS1_DBG_CMD_ACK

XS1_DBG_CMD_NACK

XS1_DBG_CMD_READ

XS1_DBG_CMD_WRITE

XS1_DBG_CMD_GETPS

XS1_DBG_CMD_SETPS

XS1_DBG_CMD_GETSTATE

XS1_DBG_CMD_SETSTATE

XS1_DBG_CMD_CALL

XS1_DBG_CMD_RFDBG

XS1_DBG_CMD_READ4PI

XS1_DBG_CMD_WRITE4PI

XS1_DBG_CMD_READVEC

XS1_DBG_CMD_WRITEVEC

XS1_DBG_CMD_READSSWITCH

XS1_DBG_CMD_WRITESSWITCH

DB_SCRATCH_USAGE_DEFS

Debug scratch register usage.

XS1_PS_DBG_HANDLER

XS1_PS_DBG_COMMAND

XS1_PS_DBG_ARG0_REG

XS1_PS_DBG_ARG1_REG

XS1_PS_DBG_ARG2_REG

XS1_PS_DBG_ARG3_REG

XS1_PS_DBG_ARG4_REG

XS1_PS_DBG_ARG5_REG

XS1_NUM_DBG_SCRATCH_REGS

XS1_LOG2_NUM_DBG_SCRATCH_REGS

XS1_PSWITCH_DBG_HANDLER_NUM

XS1_PSWITCH_DBG_COMMAND_NUM

XS1_PSWITCH_DBG_ARG0_NUM

XS1_PSWITCH_DBG_ARG1_NUM

XS1_PSWITCH_DBG_ARG2_NUM

XS1_PSWITCH_DBG_ARG3_NUM

XS1_PSWITCH_DBG_ARG4_NUM

XS1_PSWITCH_DBG_ARG5_NUM

DBG_BREAKPOINTS_DEFS

Debug breakpoints and watchpoints

XS1_NUM_DBG_IBREAK

XS1_NUM_DBG_RWATCH

XS1_NUM_DBG_DWATCH

EXTMEM_DEFS

External memory definitions.

XS1_EXTMEM_BASE

XS1_EXTMEM_SIZE

XS1_EXTMEM_ADDR_WIDTH

SWMEM_DEFS

Software defined memory definitions.

XS1_SWMEM_BASE

XS1_SWMEM_SIZE

XS1_SWMEM_ADDR_WIDTH

ROM_DEFS

ROM definitions.

XS1_ROM_BASE

XS1_ROM_SIZE

XS1_ROM_ADDR_WIDTH

XS1_ROM_BASE_WIDTH

XS1_DEBUG_VECTOR

OTP_DEFS

OTP reserved location definitinos.

XS1_OTP_SECURITY_CONFIG_TILE_0_0

XS1_OTP_SECURITY_CONFIG_TILE_0_1

XS1_OTP_SECURITY_CONFIG_TILE_1_0

XS1_OTP_SECURITY_CONFIG_TILE_1_1

XS1_OTP_DAP_RFMR_0

XS1_OTP_DAP_RFMR_1

XS1_OTP_HOBBLING_CONFIG_0

XS1_OTP_HOBBLING_CONFIG_1

XS1_OTP_JTAG_USER_CONFIG_0

XS1_OTP_JTAG_USER_CONFIG_1

XS1_OTP_SBPI_PMC_ADDRESS

XS1_OTP_SBPI_DAP_ADDRESS

XS1_OTP_PMC_START_INSTRUCTION

XS1_OTP_PMC_STOP_INSTRUCTION

XS1_OTP_PMC_NOP_INSTRUCTION

XS1_OTP_PMC_DAP_RDF

XS1_OTP_PMC_DAP_WDF

XS1_OTP_PMC_BOOT_TIMING_CTRL_0_ADDR

XS1_OTP_DAP_RFMR_ADDR

OTPA_DEFS

OTPA (arbiter) definitions.

XS1_OTPA_SEL_SBPI

XS1_OTPA_SEL_Q

XS1_OTPA_SEL_Q_MIXED

XS1_OTPA_SEL_QSR_LOWER

XS1_OTPA_SEL_QRR_LOWER

USER_CONTROL_TOKENS_DEFS

User control tokens.

XS1_CT_START_TRANSACTION

Start transaction.

XS1_CT_END

End - free up interconnect and tell target.

XS1_EOM_TOKEN

End with control token bit set - free up interconnect and tell target.

XS1_CT_PAUSE

Pause - free up interconnect but don’t tell target.

XS1_PAUSE_TOKEN

Pause with control token bit set - free up interconnect but don’t tell target.

XS1_CT_ACK

Acknowledge operation completed successfully.

XS1_ACK_TOKEN

Acknowledge with control token bit set - operation completed successfully.

XS1_CT_NACK

Acknowledge that there was an error.

XS1_NACK_TOKEN

Acknowledge that there was an error with control token bit set.

XS1_CT_READN

Read data.

XS1_CT_READ1

Read one byte.

XS1_CT_READ2

Read two bytes.

XS1_CT_READ4

Read four bytes.

XS1_CT_READ8

Read eight bytes.

XS1_CT_WRITEN

Write data.

XS1_CT_WRITE1

Write one byte.

XS1_CT_WRITE2

Write two bytes.

XS1_CT_WRITE4

Write four bytes.

XS1_CT_WRITE8

Write eight bytes.

XS1_CT_CALL

Call code at the specified address.

RESOURCE_CREGS_DEFS

Resource control registers.

XS1_RES_PS_CTRL0

XS1_RES_PS_CTRL1

XS1_RES_PS_CTRL2

XS1_RES_PS_VECTOR

XS1_RES_PS_EV

XS1_RES_PS_DATA

XS1_RES_PS_CLKSRC

XS1_RES_PS_RDYSRC

XS1_RES_PS_TBV0

VSETCTRL_SHIFT_DEFS

XS1_VSETC_SHIFT_NOSHIFT

XS1_VSETC_SHIFT_SHIFTLEFT

XS1_VSETC_SHIFT_SHIFTRIGHT

VSETCTRL_TYPE_DEFS

XS1_VSETC_TYPE_INT32

XS1_VSETC_TYPE_INT16

XS1_VSETC_TYPE_INT8

SETCTRL_MODES_DEFS

XS1_SETC_MODE_INUSE

XS1_SETC_MODE_COND

XS1_SETC_MODE_IE_MODE

XS1_SETC_MODE_DRIVE

XS1_SETC_MODE_SETPADCTRL

XS1_SETC_MODE_LONG

SETCTRL_LMODE_DEFS

XS1_SETC_LMODE_RUN

XS1_SETC_LMODE_MS

XS1_SETC_LMODE_BUF

XS1_SETC_LMODE_RDY

XS1_SETC_LMODE_SDELAY

XS1_SETC_LMODE_PORT

XS1_SETC_LMODE_INV

XS1_SETC_LMODE_PIN_DELAY

XS1_SETC_LMODE_FALL_DELAY

XS1_SETC_LMODE_RISE_DELAY

CTRL_MODE_DEFS

XS1_SETC_INUSE_OFF

XS1_SETC_INUSE_ON

XS1_SETC_COND_NONE

XS1_SETC_COND_FULL

XS1_SETC_COND_AFTER

XS1_SETC_COND_EQ

XS1_SETC_COND_NEQ

XS1_SETC_COND_GREATER

XS1_SETC_COND_LESS

XS1_SETC_IE_MODE_EVENT

XS1_SETC_IE_MODE_INTERRUPT

XS1_SETC_DRIVE_DRIVE

XS1_SETC_DRIVE_PULL_DOWN

XS1_SETC_DRIVE_PULL_UP

XS1_SETC_RUN_STOPR

XS1_SETC_RUN_STARTR

XS1_SETC_RUN_CLRBUF

XS1_SETC_MS_MASTER

XS1_SETC_MS_SLAVE

XS1_SETC_BUF_NOBUFFERS

XS1_SETC_BUF_BUFFERS

XS1_SETC_RDY_NOREADY

XS1_SETC_RDY_STROBED

XS1_SETC_RDY_HANDSHAKE

XS1_SETC_SDELAY_NOSDELAY

XS1_SETC_SDELAY_SDELAY

XS1_SETC_PORT_DATAPORT

XS1_SETC_PORT_CLOCKPORT

XS1_SETC_PORT_READYPORT

XS1_SETC_INV_NOINVERT

XS1_SETC_INV_INVERT

Defines

XS1_DEVICE_ID0_VERSION_VALUE

XS1_DEVICE_ID0_REVISION_VALUE

XS1_NUM_NETWORKS

XS1_NUM_RES_TYPES

XS1_CLK_REF

XS1_CLK_XCORE

XS1_SWMEM_FILL

XS1_SWMEM_EVICT

XS1_ET_NONE

XS1_RES_ID_INVALID

XS1_KEP_ALIGNMENT

XS1_KCALL_ALIGNMENT

XS1_TRAP_KCALL_OFFSET

XS1_ARG0_REG

XS1_ARG1_REG

XS1_ARG2_REG

XS1_ARG3_REG

XS1_RET0_REG

XS1_RET1_REG

XS1_RET2_REG

XS1_RET3_REG

XS1_NUM_LOCKS

XS1_NUM_SYNCS

XS1_NUM_TIMERS

XS1_NUM_SWMEMS

XS1_NUM_THREADS

XS1_NUM_CHANENDS

XS1_NUM_CLKBLKS

XS1_NUM_MMAPS

XS1_NUM_WORDS_PER_VECTOR

XS1_DBG_BUFFER_WORDS

XS1_RAM_BASE

XS1_RAM_SIZE

XS1_RAM_ADDR_WIDTH

XS1_CT_WRITEC

Write control register.

XS1_CT_READC

Read control register.

XS1_CT_PSCTRL

PSwitch configuration message data value.

XS1_CT_SSCTRL

SSwitch configuration message data value.

XS1_XMOS_PHY_CONF_WIDTH

XS1_USB_PHY_VCONTROL_SETUP_LENGTH

XS1_USB_PHY_ENTER_BIST_LENGTH

XS1_USB_PHY_CLKCNT_WIDTH

XS1_USB_BISTGO_CTR_WIDTH

XS1_USB_TESTGO_CTR_WIDTH

XS1_USB_TESTGO_PULSE_LENGTH

XS1_USB_BISTGO_PULSE_LENGTH

XS1_CRC5_RESULT_WIDTH

XS1_MS_NIBBLE

XS1_LS_NIBBLE

Port definitions

group xs3a Port Definitions

Defines

XS1_NUM_1BIT_GPIO_PORTS

XS1_NUM_4BIT_GPIO_PORTS

XS1_NUM_8BIT_GPIO_PORTS

XS1_NUM_16BIT_GPIO_PORTS

XS1_NUM_32BIT_GPIO_PORTS

XS1_NUM_16BIT_PERIPH_PORTS

XS1_NUM_32BIT_PERIPH_PORTS

XS1_NUM_1BIT_PORTS

XS1_NUM_4BIT_PORTS

XS1_NUM_8BIT_PORTS

XS1_NUM_16BIT_PORTS

XS1_NUM_32BIT_PORTS