XS3 Definitions

Processor State Registers

Processor State Registers (also called “processor status registers” or “processor configuration registers”) are registers that exist on a specific tile, and can be accessed with a single instruction (either getps or setps). From C, getps() and setps() can be used.

group xs3aPSRegisters

PS_DBG_SCRATCH

A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Debug Scratch registers in the xCORE tile configuration.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_SCRATCH 0x8

XS1_PS_DBG_SCRATCH_0 0x200b

PS_DBG_SCRATCH 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_1 0x210b

PS_DBG_SCRATCH 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_2 0x220b

PS_DBG_SCRATCH 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_3 0x230b

PS_DBG_SCRATCH 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_4 0x240b

PS_DBG_SCRATCH 4 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_5 0x250b

PS_DBG_SCRATCH 5 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_6 0x260b

PS_DBG_SCRATCH 6 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_SCRATCH_7 0x270b

PS_DBG_SCRATCH 7 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_IBREAK_ADDR

This register contains the address of the instruction breakpoint. If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_IBREAK_ADDR 0x4

XS1_PS_DBG_IBREAK_ADDR_0 0x300b

PS_DBG_IBREAK_ADDR 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_1 0x310b

PS_DBG_IBREAK_ADDR 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_2 0x320b

PS_DBG_IBREAK_ADDR 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_ADDR_3 0x330b

PS_DBG_IBREAK_ADDR 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_IBREAK_CTRL

This register controls which logical cores may take an instruction breakpoint, and under which condition.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

IBRK_CONDITION When 0 break when PC == IBREAK_ADDR. When 1 = break when PC != IBREAK_ADDR.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_IBREAK_CTRL 0x4

XS1_PS_DBG_IBREAK_CTRL_0 0x400b

PS_DBG_IBREAK_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_1 0x410b

PS_DBG_IBREAK_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_2 0x420b

PS_DBG_IBREAK_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_IBREAK_CTRL_3 0x430b

PS_DBG_IBREAK_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_ADDR1

This set of registers contains the first address for the four data watchpoints. Condition A of a watchpoint is met if the effective address of an instruction is greater than or equal to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition A or B, or both A and B.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_DWATCH_ADDR1 0x4

XS1_PS_DBG_DWATCH_ADDR1_0 0x500b

PS_DBG_DWATCH_ADDR1 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_1 0x510b

PS_DBG_DWATCH_ADDR1 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_2 0x520b

PS_DBG_DWATCH_ADDR1 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR1_3 0x530b

PS_DBG_DWATCH_ADDR1 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_ADDR2

This set of registers contains the second address for the four data watchpoints. Condition B of a watchpoint is met if the effective address of an instruction is less than or equal to the value in this register.

The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition A or B, or both A and B.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_DWATCH_ADDR2 0x4

XS1_PS_DBG_DWATCH_ADDR2_0 0x600b

PS_DBG_DWATCH_ADDR2 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_1 0x610b

PS_DBG_DWATCH_ADDR2 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_2 0x620b

PS_DBG_DWATCH_ADDR2 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_ADDR2_3 0x630b

PS_DBG_DWATCH_ADDR2 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_DWATCH_CTRL

This set of registers controls each of the four data watchpoints.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

DBRK_CONDITION Determines the break condition: 0 = A AND B, 1 = A OR B.

BRK_LOAD When 1 the breakpoints will be be triggered on loads.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_DWATCH_CTRL 0x4

XS1_PS_DBG_DWATCH_CTRL_0 0x700b

PS_DBG_DWATCH_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_1 0x710b

PS_DBG_DWATCH_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_2 0x720b

PS_DBG_DWATCH_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_DWATCH_CTRL_3 0x730b

PS_DBG_DWATCH_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_ADDR1

This set of registers contains the mask for the four resource watchpoints.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_RWATCH_ADDR1 0x4

XS1_PS_DBG_RWATCH_ADDR1_0 0x800b

PS_DBG_RWATCH_ADDR1 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_1 0x810b

PS_DBG_RWATCH_ADDR1 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_2 0x820b

PS_DBG_RWATCH_ADDR1 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR1_3 0x830b

PS_DBG_RWATCH_ADDR1 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_ADDR2

This set of registers contains the value for the four resource watchpoints.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PS_DBG_RWATCH_ADDR2 0x4

XS1_PS_DBG_RWATCH_ADDR2_0 0x900b

PS_DBG_RWATCH_ADDR2 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_1 0x910b

PS_DBG_RWATCH_ADDR2 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_2 0x920b

PS_DBG_RWATCH_ADDR2 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_ADDR2_3 0x930b

PS_DBG_RWATCH_ADDR2 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

PS_DBG_RWATCH_CTRL

This set of registers controls each of the four resource watchpoints.

Sub-Fields:

BRK_ENABLE When 1 the breakpoint is enabled.

RBRK_CONDITION When 0 break when condition A is met. When 1 = break when condition B is met.

BRK_THREADS A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_NUM_PS_DBG_RWATCH_CTRL 0x4

XS1_PS_DBG_RWATCH_CTRL_0 0x9c0b

PS_DBG_RWATCH_CTRL 0 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_1 0x9d0b

PS_DBG_RWATCH_CTRL 1 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_2 0x9e0b

PS_DBG_RWATCH_CTRL 2 processor state register ID.

Use getps() to access. Only accessible in debug mode.

XS1_PS_DBG_RWATCH_CTRL_3 0x9f0b

PS_DBG_RWATCH_CTRL 3 processor state register ID.

Use getps() to access. Only accessible in debug mode.

Defines

XS1_PS_RAM_BASE 0xb

PS_RAM_BASE processor state register ID.

Use getps() and setps() to access.

This register contains the base address of the RAM. It is initialized to 0x00080000.

Sub-Fields:

WORD_ADDRESS_BITS Most significant 16 bits of all addresses.

XS1_PS_VECTOR_BASE 0x10b

PS_VECTOR_BASE processor state register ID.

Use getps() and setps() to access.

Base address of event vectors in each resource. On an interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least significant 16 bits come from the event vector.

Sub-Fields:

VECTOR_BASE The event and interrupt vectors.

XS1_PS_XCORE_CTRL0 0x20b

PS_XCORE_CTRL0 processor state register ID.

Use getps() and setps() to access.

Register to control features in the xCORE tile

Sub-Fields:

XCORE_CTRL0_EXTMEM_ENABLE Enable External memory interface

XCORE_CTRL0_USB_ENABLE Enable the USB hardware support module

XCORE_CTRL0_CLK_DIVIDER_EN Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes.

XCORE_CTRL0_CLK_DIVIDER_DYN Select the dynamic mode (1) for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active threads are paused. In static mode the clock divider is always enabled.

XCORE_CTRL0_MIPI_ENABLE Enable MIPI interface periph ports

XCORE_CTRL0_MEMSLEEP_ENABLE Enable memory auto-sleep feature

XCORE_CTRL0_RAMSHUTDOWN Disable RAMs to save power (contents will be lost)

XCORE_CTRL0_EXTMEM_DEVICE_SIZE Specify size of a connected LPDDR device (options are: 128,256,512Mbits, 1Gbit),

XS1_PS_BOOT_CONFIG 0x30b

PS_BOOT_CONFIG processor state register ID.

Use getps() to access.

This read-only register describes the boot status of the xCORE tile.

Sub-Fields:

BOOT_CONFIG_PLL_MODE_PINS The boot PLL mode pin value.

BOOT_CONFIG_BOOT_FROM_JTAG Boot ROM boots from JTAG

BOOT_CONFIG_BOOT_FROM_RAM Boot ROM boots from RAM

BOOT_CONFIG_DISABLE_OTP_POLL Cause the ROM to not poll the OTP for correct read levels

BOOT_CONFIG_SECURE_BOOT Overwrite BOOT_MODE.

BOOT_CONFIG_PROCESSOR Processor number.

XS1_PS_BOOT_STATUS 0x40b

PS_BOOT_STATUS processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

BOOT_STATUS_LEDS Boot status LED value.

BOOT_STATUS_BITS Other boot status LED bits.

XS1_PS_SECURITY_CONFIG 0x50b

PS_SECURITY_CONFIG processor state register ID.

Use getps() and setps() to access.

Copy of the security register as read from OTP.

Sub-Fields:

SECUR_CFG_DISABLE_XCORE_JTAG Disable access to XCore’s JTAG debug TAP

SECUR_CFG_DISABLE_PLL_JTAG Disable JTAG access to the PLL/BOOT configuration registers

SECUR_CFG_SECURE_BOOT Override boot mode and read boot image from OTP

SECUR_CFG_OTP_COMBINED Combine OTP into a single address-space for reading.

SECUR_CFG_OTP_PROGRAM_DISABLE Prevent access to OTP SBPI interface to prevent programming and other functions.

SECUR_CFG_OTP_READ_LOCK Disable read access to OTP.

SECUR_CFG_DISABLE_GLOBAL_DEBUG Disable access to XCore’s global debug

SECUR_CFG_DISABLE_ACCESS Disables write permission on this register

XS1_PS_RING_OSC_CTRL 0x60b

PS_RING_OSC_CTRL processor state register ID.

Use getps() and setps() to access.

There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator has been stopped for at least 10 core clock cycles (this can be achieved by inserting two nop instructions between the SETPS and GETPS). The counter values can be read using two subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits.

Sub-Fields:

RING_OSC_PERPH_ENABLE Set to 1 to enable the core peripheral ring oscillator.

RING_OSC_CORE_ENABLE Core ring oscillator enable.

XS1_PS_RING_OSC_DATA0 0x70b

PS_RING_OSC_DATA0 processor state register ID.

Use getps() to access.

This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA1 0x80b

PS_RING_OSC_DATA1 processor state register ID.

Use getps() to access.

This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA2 0x90b

PS_RING_OSC_DATA2 processor state register ID.

Use getps() to access.

This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_RING_OSC_DATA3 0xa0b

PS_RING_OSC_DATA3 processor state register ID.

Use getps() to access.

This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset.

Sub-Fields:

RING_OSC_DATA Ring oscillator Counter data.

XS1_PS_UNAVAILABLE_RESOURCE 0xb0b

PS_UNAVAILABLE_RESOURCE processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

RAM_MASK Blocks of 64k rams unavailable

CORE1_DISABLE Core 1’s clock is gated off

THREAD_MASK Threads unavailable

XS1_PS_RAM_SIZE 0xc0b

PS_RAM_SIZE processor state register ID.

Use getps() to access.

The size of the RAM in bytes

Sub-Fields:

WORD_ADDRESS_BITS Most significant 16 bits of all addresses.

XS1_PS_ROM_RMA 0xf0b

PS_ROM_RMA processor state register ID.

Use getps() and setps() to access.

Sub-Fields:

RTSEL ROM debug timing adjust.

PTSEL ROM debug timing adjust.

TRB ROM debug timing adjust.

XS1_PS_DBG_SSR 0x100b

PS_DBG_SSR processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SSR register when the debugger was called.

Sub-Fields:

SR_EEBLE 1 when events are enabled for the thread.

SR_IEBLE 1 when interrupts are enabled for the thread.

SR_INENB 1 when in an event enabling sequence.

SR_ININT 1 when in an interrupt handler.

SR_INK 1 when in kernel mode.

SR_WAITING 1 when the thread is paused waiting for events, a lock or another resource.

SR_FAST 1 when the thread is in fast mode and will continually issue.

SR_DI 1 when in dual issue mode.

SR_KEDI 1 if, on kernel entry, the thread will switch to dual issue.

SR_QUEUE 1 if in high priority mode

XS1_PS_DBG_SPC 0x110b

PS_DBG_SPC processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SPC register when the debugger was called.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_SSP 0x120b

PS_DBG_SSP processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register contains the value of the SSP register when the debugger was called.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_T_NUM 0x130b

PS_DBG_T_NUM processor state register ID.

Use getps() to access. Only accessible in debug mode.

The resource ID of the logical core whose state is to be read.

Sub-Fields:

DBG_T_NUM_NUM Thread number to be read

XS1_PS_DBG_T_REG 0x140b

PS_DBG_T_REG processor state register ID.

Use getps() to access. Only accessible in debug mode.

Register number to be read by DGETREG

Sub-Fields:

DBG_T_REG_REG Register number to be read

XS1_PS_DBG_TYPE 0x150b

PS_DBG_TYPE processor state register ID.

Use getps() to access. Only accessible in debug mode.

Register that specifies what activated the debug interrupt.

Sub-Fields:

DBG_TYPE_CAUSE Indicates the cause of the debug interrupt

1: Host initiated a debug interrupt through JTAG

2: Program executed a DCALL instruction

3: Instruction breakpoint

4: Data watch point

5: Resource watch point

DBG_TYPE_T_NUM Number of thread which caused the debug interrupt (always 0 in the case of =HOST=).

DBG_TYPE_HW_NUM Number of the hardware breakpoint/watchpoint which caused the interrupt (always 0 for =HOST= and =DCALL=). If multiple breakpoints/watchpoints trigger at once, the lowest number is taken.

XS1_PS_DBG_DATA 0x160b

PS_DBG_DATA processor state register ID.

Use getps() to access. Only accessible in debug mode.

On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger. On a resource watchpoint, it countains the resource identifier.

Sub-Fields:

ALL_BITS Value.

XS1_PS_DBG_RUN_CTRL 0x180b

PS_DBG_RUN_CTRL processor state register ID.

Use getps() to access. Only accessible in debug mode.

This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented.

Sub-Fields:

DBG_RUN_CTRL_STOP 1-hot vector defining which threads are stopped when not in debug mode. Every bit which is set prevents the respective thread from running.

XS1_PS_CACHE_MISS_CNT 0xa00b

PS_CACHE_MISS_CNT processor state register ID.

Use getps() to access.

This is a free running, unresetable, read-only counter incremented on every cache miss by any thread to either SWMEM or EXTMEM.

Sub-Fields:

ALL_BITS Value.

XS1_PS_CACHE_ACCESS_CNT 0xa10b

PS_CACHE_ACCESS_CNT processor state register ID.

Use getps() to access.

This is a free running, unresetable, read-only counter incremented on every cache access by any thread to either SWMEM or EXTMEM.

Sub-Fields:

ALL_BITS Value.

Processor Switch Registers

Processor Switch Registers (also called “PSWITCH registers” or “tile configuration registers”) are registers that exist on a specific tile, and can be accessed using channels. From C, read_pswitch_reg() and write_pswitch_reg() can be used.

group xs3aPSWITCHRegisters

PSWITCH_DBG_SCRATCH

A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor status.

Sub-Fields:

ALL_BITS Value.

XS1_NUM_PSWITCH_DBG_SCRATCH 0x8

XS1_PSWITCH_DBG_SCRATCH_0_NUM 0x20

PSWITCH_DBG_SCRATCH 0 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_1_NUM 0x21

PSWITCH_DBG_SCRATCH 1 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_2_NUM 0x22

PSWITCH_DBG_SCRATCH 2 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_3_NUM 0x23

PSWITCH_DBG_SCRATCH 3 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_4_NUM 0x24

PSWITCH_DBG_SCRATCH 4 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_5_NUM 0x25

PSWITCH_DBG_SCRATCH 5 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_6_NUM 0x26

PSWITCH_DBG_SCRATCH 6 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_SCRATCH_7_NUM 0x27

PSWITCH_DBG_SCRATCH 7 processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Defines

XS1_PSWITCH_DEVICE_ID0_NUM 0x0

PSWITCH_DEVICE_ID0 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register identifies the xCORE Tile

Sub-Fields:

DEVICE_ID0_VERSION XCore version.

DEVICE_ID0_REVISION XCore revision.

DEVICE_ID0_NODE Number of the node in which this XCore is located.

DEVICE_ID0_PID Processor ID of this XCore.

XS1_PSWITCH_DEVICE_ID1_NUM 0x1

PSWITCH_DEVICE_ID1 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile.

Sub-Fields:

DEVICE_ID1_NUM_THREADS Number of threads.

DEVICE_ID1_NUM_SYNCS Number of synchronisers.

DEVICE_ID1_NUM_LOCKS Number of the locks.

DEVICE_ID1_NUM_CHANENDS Number of channel ends.

XS1_PSWITCH_DEVICE_ID2_NUM 0x2

PSWITCH_DEVICE_ID2 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register describes the number of timers and clock blocks available on this xCORE tile.

Sub-Fields:

DEVICE_ID2_NUM_TIMERS Number of timers.

DEVICE_ID2_NUM_CLKBLKS Number of clock blocks.

XS1_PSWITCH_DEVICE_ID3_NUM 0x3

PSWITCH_DEVICE_ID3 processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

XS1_PSWITCH_DBG_CTRL_NUM 0x4

PSWITCH_DBG_CTRL processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile configuration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect.

Sub-Fields:

DBG_CTRL_PSWITCH_RO_EXT When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch

DBG_CTRL_PSWITCH_RO When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch, XCore(PS_DBG_Scratch) and JTAG

XS1_PSWITCH_DBG_INT_NUM 0x5

PSWITCH_DBG_INT processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register can be used to raise a debug interrupt in this xCORE tile.

Sub-Fields:

DBG_INT_REQ_DBG Request a debug interrupt on the processor.

DBG_INT_IN_DBG 1 when the processor is in debug mode.

XS1_PSWITCH_PLL_CLK_DIVIDER_NUM 0x6

PSWITCH_PLL_CLK_DIVIDER processor switch register number.

Use read_pswitch_reg() and write_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register

Sub-Fields:

PLL_CLK_DIVIDER Clock divider.

PLL_CLK_DISABLE Clock disable. Writing ‘1’ will remove the clock to the tile.

XS1_PSWITCH_SECU_CONFIG_NUM 0x7

PSWITCH_SECU_CONFIG processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Copy of the security register as read from OTP.

Sub-Fields:

SECUR_CFG_DISABLE_XCORE_JTAG Disable access to XCore’s JTAG debug TAP

SECUR_CFG_DISABLE_PLL_JTAG Disable JTAG access to the PLL/BOOT configuration registers

SECUR_CFG_SECURE_BOOT Override boot mode and read boot image from OTP

SECUR_CFG_OTP_COMBINED Combine OTP into a single address-space for reading.

SECUR_CFG_OTP_PROGRAM_DISABLE Prevent access to OTP SBPI interface to prevent programming and other functions.

SECUR_CFG_OTP_READ_LOCK Disable read access to OTP.

SECUR_CFG_DISABLE_GLOBAL_DEBUG Disable access to XCore’s global debug

SECUR_CFG_DISABLE_ACCESS Disables write permission on this register

XS1_PSWITCH_T0_PC_NUM 0x40

PSWITCH_T0_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 0.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T1_PC_NUM 0x41

PSWITCH_T1_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 1.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T2_PC_NUM 0x42

PSWITCH_T2_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 2.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T3_PC_NUM 0x43

PSWITCH_T3_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 3.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T4_PC_NUM 0x44

PSWITCH_T4_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 4.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T5_PC_NUM 0x45

PSWITCH_T5_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 5.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T6_PC_NUM 0x46

PSWITCH_T6_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 6.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T7_PC_NUM 0x47

PSWITCH_T7_PC processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the PC of logical core 7.

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T0_SR_NUM 0x60

PSWITCH_T0_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 0

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T1_SR_NUM 0x61

PSWITCH_T1_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 1

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T2_SR_NUM 0x62

PSWITCH_T2_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 2

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T3_SR_NUM 0x63

PSWITCH_T3_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 3

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T4_SR_NUM 0x64

PSWITCH_T4_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 4

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T5_SR_NUM 0x65

PSWITCH_T5_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 5

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T6_SR_NUM 0x66

PSWITCH_T6_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 6

Sub-Fields:

ALL_BITS Value.

XS1_PSWITCH_T7_SR_NUM 0x67

PSWITCH_T7_SR processor switch register number.

Use read_pswitch_reg() to access. Only accessible if PSWITCH_DBG_CTRL is zero.

Value of the SR of logical core 7

Sub-Fields:

ALL_BITS Value.

System Switch Registers

System Switch Registers (also called “SSWITCH registers” or “node configuration registers”) are registers that are shared between all tiles on a chip, and can be accessed through the interconnect using channels. From C, read_sswitch_reg() and write_sswitch_reg() can be used.

group xs3aSSWITCHRegisters

SSWITCH_SLINK

These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of. The registers control links 0..7.

Sub-Fields:

LINK_SRC_INUSE 1 when the source side of the link is in use.

LINK_DST_INUSE 1 when the dest side of the link is in use.

LINK_JUNK 1 when the current packet is considered junk and will be thrown away.

LINK_NETWORK Determines the network to which this link belongs, reset as 0.

LINK_DIRECTION The direction that this link operates in.

SLINK_SRC_TARGET_ID When the link is in use, this is the destination link number to which all packets are sent.

SLINK_SRC_TARGET_TYPE Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_NUM_SSWITCH_SLINK 0x9

XS1_SSWITCH_SLINK_0_NUM 0x20

SSWITCH_SLINK 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_1_NUM 0x21

SSWITCH_SLINK 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_2_NUM 0x22

SSWITCH_SLINK 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_3_NUM 0x23

SSWITCH_SLINK 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_4_NUM 0x24

SSWITCH_SLINK 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_5_NUM 0x25

SSWITCH_SLINK 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_6_NUM 0x26

SSWITCH_SLINK 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_7_NUM 0x27

SSWITCH_SLINK 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_SLINK_8_NUM 0x28

SSWITCH_SLINK 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_PLINK

These registers contain status information and the network number that each processor-link belongs to.

Sub-Fields:

LINK_SRC_INUSE 1 when the source side of the link is in use.

LINK_DST_INUSE 1 when the dest side of the link is in use.

LINK_JUNK 1 when the current packet is considered junk and will be thrown away.

LINK_NETWORK Determines the network to which this link belongs, reset as 0.

PLINK_SRC_TARGET_ID When the link is in use, this is the destination link number to which all packets are sent.

PLINK_SRC_TARGET_TYPE Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 - Undefine.

XS1_NUM_SSWITCH_PLINK 0x8

XS1_SSWITCH_PLINK_0_NUM 0x40

SSWITCH_PLINK 0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_1_NUM 0x41

SSWITCH_PLINK 1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_2_NUM 0x42

SSWITCH_PLINK 2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_3_NUM 0x43

SSWITCH_PLINK 3 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_4_NUM 0x44

SSWITCH_PLINK 4 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_5_NUM 0x45

SSWITCH_PLINK 5 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_6_NUM 0x46

SSWITCH_PLINK 6 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_PLINK_7_NUM 0x47

SSWITCH_PLINK 7 system switch register number.

Use read_sswitch_reg() to access.

SSWITCH_XLINK

These registers contain configuration and debugging information specific to external links. The link speed and width can be set, the link can be initialized, and the link status can be monitored. The registers control links 0..7.

Sub-Fields:

XLINK_INTER_TOKEN_DELAY Specify min. number of idle system clocks between two continuous transmit tokens -1.

XLINK_INTRA_TOKEN_DELAY Specify min. number of idle system clocks between two continuous symbols witin a transmit token -1.

XLINK_RX_RESET Reset the receiver. The next symbol that is detected will be the first symbol in a token.

XLINK_HELLO Clear this end of the xlink’s credit and issue a HELLO token.

TX_CREDIT This end of the xlink has credit to allow it to transmit.

RX_CREDIT This end of the xlink has issued credit to allow the remote end to transmit

XLINK_RX_ERROR Rx buffer overflow or illegal token encoding received.

XLINK_WIDE 0: operate in 2 wire mode; 1: operate in 5 wire mode

XLINK_ENABLE Write to this bit with ‘1’ will enable the XLink, writing ‘0’ will disable it. This bit controls the muxing of ports with overlapping xlinks.

XS1_NUM_SSWITCH_XLINK 0x9

XS1_SSWITCH_XLINK_0_NUM 0x80

SSWITCH_XLINK 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_1_NUM 0x81

SSWITCH_XLINK 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_2_NUM 0x82

SSWITCH_XLINK 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_3_NUM 0x83

SSWITCH_XLINK 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_4_NUM 0x84

SSWITCH_XLINK 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_5_NUM 0x85

SSWITCH_XLINK 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_6_NUM 0x86

SSWITCH_XLINK 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_7_NUM 0x87

SSWITCH_XLINK 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XLINK_8_NUM 0x88

SSWITCH_XLINK 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_XSTATIC

These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order.

Sub-Fields:

XSTATIC_DEST_CHAN_END The destination channel end on this node that packets received in static mode are forwarded to.

XSTATIC_DEST_PROC The destination processor on this node that packets received in static mode are forwarded to.

XSTATIC_ENABLE Enable static forwarding.

XS1_NUM_SSWITCH_XSTATIC 0x8

XS1_SSWITCH_XSTATIC_0_NUM 0xa0

SSWITCH_XSTATIC 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_1_NUM 0xa1

SSWITCH_XSTATIC 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_2_NUM 0xa2

SSWITCH_XSTATIC 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_3_NUM 0xa3

SSWITCH_XSTATIC 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_4_NUM 0xa4

SSWITCH_XSTATIC 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_5_NUM 0xa5

SSWITCH_XSTATIC 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_6_NUM 0xa6

SSWITCH_XSTATIC 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_XSTATIC_7_NUM 0xa7

SSWITCH_XSTATIC 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_MIPI_XCFGI_REG

Internal MIPI config registers

XS1_NUM_SSWITCH_MIPI_XCFGI_REG 0x13

XS1_SSWITCH_MIPI_XCFGI_REG_0_NUM 0xe000

SSWITCH_MIPI_XCFGI_REG 0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_1_NUM 0xe001

SSWITCH_MIPI_XCFGI_REG 1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_2_NUM 0xe002

SSWITCH_MIPI_XCFGI_REG 2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_3_NUM 0xe003

SSWITCH_MIPI_XCFGI_REG 3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_4_NUM 0xe004

SSWITCH_MIPI_XCFGI_REG 4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_5_NUM 0xe005

SSWITCH_MIPI_XCFGI_REG 5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_6_NUM 0xe006

SSWITCH_MIPI_XCFGI_REG 6 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_7_NUM 0xe007

SSWITCH_MIPI_XCFGI_REG 7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_8_NUM 0xe008

SSWITCH_MIPI_XCFGI_REG 8 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_9_NUM 0xe009

SSWITCH_MIPI_XCFGI_REG 9 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_10_NUM 0xe00a

SSWITCH_MIPI_XCFGI_REG 10 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_11_NUM 0xe00b

SSWITCH_MIPI_XCFGI_REG 11 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_12_NUM 0xe00c

SSWITCH_MIPI_XCFGI_REG 12 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_13_NUM 0xe00d

SSWITCH_MIPI_XCFGI_REG 13 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_14_NUM 0xe00e

SSWITCH_MIPI_XCFGI_REG 14 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_15_NUM 0xe00f

SSWITCH_MIPI_XCFGI_REG 15 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_16_NUM 0xe010

SSWITCH_MIPI_XCFGI_REG 16 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_17_NUM 0xe011

SSWITCH_MIPI_XCFGI_REG 17 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGI_REG_18_NUM 0xe012

SSWITCH_MIPI_XCFGI_REG 18 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

SSWITCH_MIPI_XCFGO_REG

Internal MIPI config registers

XS1_NUM_SSWITCH_MIPI_XCFGO_REG 0x3

XS1_SSWITCH_MIPI_XCFGO_REG_0_NUM 0xe020

SSWITCH_MIPI_XCFGO_REG 0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGO_REG_1_NUM 0xe021

SSWITCH_MIPI_XCFGO_REG 1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_MIPI_XCFGO_REG_2_NUM 0xe022

SSWITCH_MIPI_XCFGO_REG 2 system switch register number.

Use read_sswitch_reg() to access.

Defines

XS1_SSWITCH_DEVICE_ID0_NUM 0x0

SSWITCH_DEVICE_ID0 system switch register number.

Use read_sswitch_reg() to access.

This register contains version and revision identifiers and the mode-pins as sampled at boot-time.

Sub-Fields:

SS_DEVICE_ID0_VERSION SSwitch version.

SS_DEVICE_ID0_REVISION SSwitch revision.

SS_DEVICE_ID0_BOOT_CTRL Sampled values of BootCtl pins on Power On Reset.

XS1_SSWITCH_DEVICE_ID1_NUM 0x1

SSWITCH_DEVICE_ID1 system switch register number.

Use read_sswitch_reg() to access.

This register specifies the number of processors and links that are connected to this switch.

Sub-Fields:

SS_DEVICE_ID1_NUM_PLINKS_PER_PROC Number of processors on the device.

SS_DEVICE_ID1_NUM_PROCESSORS Number of processors on the SSwitch.

SS_DEVICE_ID1_NUM_SLINKS Number of SLinks on the SSwitch.

XS1_SSWITCH_DEVICE_ID2_NUM 0x2

SSWITCH_DEVICE_ID2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_DEVICE_ID3_NUM 0x3

SSWITCH_DEVICE_ID3 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_NODE_CONFIG_NUM 0x4

SSWITCH_NODE_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode.

Sub-Fields:

SS_NODE_CONFIG_HEADERS 0 = 2-byte headers, 1 = 1-byte headers (reset as 0).

SS_NODE_CONFIG_DISABLE_PLL_CTL_REG 0 = PLL_CTL_REG has write access. 1 = PLL_CTL_REG can not be written to.

SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE 0 = SSCTL registers have write access. 1 = SSCTL registers can not be written to.

XS1_SSWITCH_NODE_ID_NUM 0x5

SSWITCH_NODE_ID system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains the node identifier.

Sub-Fields:

SS_NODE_ID_ID The unique ID of this node.

XS1_SSWITCH_PLL_CTL_NUM 0x6

SSWITCH_PLL_CTL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset.

Sub-Fields:

SS_PLL_CTL_INPUT_DIVISOR Oscilator input divider value range from 0 (0x00) to 63 (0x3F). R value.

SS_PLL_CTL_FEEDBACK_MUL Feedback multiplication ratio, range from 1 (0x0001) to 8191 (0x1FFF). F value.

SS_PLL_CTL_POST_DIVISOR Output divider value range from 0 to 7. OD value.

SS_PLL_CTL_DISABLE If set to 1, the PLL is disabled.

SS_TEST_MODE_BOOT_RAM If set to 1, set the boot mode to jump to RAM

SS_TEST_MODE_PLL_BYPASS If set to 1, set the PLL to be bypassed

SS_TEST_MODE_BOOT_JTAG If set to 1, set the boot mode to boot from JTAG

SS_PLL_CTL_NLOCK If set to 1, the chip will not wait for the PLL to re-lock. Only use this if a gradual change is made to the PLL

SS_PLL_CTL_NRESET If set to 1, the chip will not be reset

XS1_SSWITCH_CLK_DIVIDER_NUM 0x7

SSWITCH_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL clock and the switch clock.

Sub-Fields:

SS_CLK_DIVIDER_CLK_DIV SSwitch clock divider

XS1_SSWITCH_REF_CLK_DIVIDER_NUM 0x8

SSWITCH_REF_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL clock and the reference clock used by the node.

Sub-Fields:

SS_SSWITCH_REF_CLK_DIV Software reference clock divider

XS1_SSWITCH_JTAG_DEVICE_ID_NUM 0x9

SSWITCH_JTAG_DEVICE_ID system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

SS_JTAG_DEVICE_ID_CONST_VAL

SS_JTAG_DEVICE_ID_MANU_ID

SS_JTAG_DEVICE_ID_PART_NUM

SS_JTAG_DEVICE_ID_VERSION

XS1_SSWITCH_JTAG_USERCODE_NUM 0xa

SSWITCH_JTAG_USERCODE system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

SS_JTAG_USERCODE_MASKID metal fixable ID code

SS_JTAG_USERCODE_OTP JTAG USERCODE value programmed into OTP SR

XS1_SSWITCH_DDR_CLK_DIVIDER_NUM 0xb

SSWITCH_DDR_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sets the ratio of the PLL/APP PLL clock and the LPDDR clock. There is a divide by 2 permanently after the clock divider to create a matched mark space ratio. The LPDDR clock needs to be set to be twice the frequency required.

Sub-Fields:

SS_DDR_CLK_DIV LPDDR clock divider. When set to X the input clock is divided by 2(X+1).

SS_DDR_CLK_DIV_DISABLE LPDDR clock divider disable. When set to 0, the divider is enabled.

SS_DDR_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the LPDDR clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_DIMENSION_DIRECTION0_NUM 0xc

SSWITCH_DIMENSION_DIRECTION0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains eight directions, for packets with a mismatch in bits 7..0 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit.

Sub-Fields:

DIM0_DIR The direction for packets whose dimension is 0.

DIM1_DIR The direction for packets whose dimension is 1.

DIM2_DIR The direction for packets whose dimension is 2.

DIM3_DIR The direction for packets whose dimension is 3.

DIM4_DIR The direction for packets whose dimension is 4.

DIM5_DIR The direction for packets whose dimension is 5.

DIM6_DIR The direction for packets whose dimension is 6.

DIM7_DIR The direction for packets whose dimension is 7.

XS1_SSWITCH_DIMENSION_DIRECTION1_NUM 0xd

SSWITCH_DIMENSION_DIRECTION1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit.

Sub-Fields:

DIM8_DIR The direction for packets whose dimension is 8.

DIM9_DIR The direction for packets whose dimension is 9.

DIMA_DIR The direction for packets whose dimension is A.

DIMB_DIR The direction for packets whose dimension is B.

DIMC_DIR The direction for packets whose dimension is C.

DIMD_DIR The direction for packets whose dimension is D.

DIME_DIR The direction for packets whose dimension is E.

DIMF_DIR The direction for packets whose dimension is F.

XS1_SSWITCH_SS_APP_CLK_DIVIDER_NUM 0xe

SSWITCH_SS_APP_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

The clock divider and output of the secondary PLL can be set in this register

Sub-Fields:

SS_APP_CLK_DIV Application clock divider. When set to X, the output of the secondary PLL will be divided by 2(X+1) in order to form the output on the output pin

SS_APP_CLK_DIV_DISABLE Application clock divider disable. When set to 0, the divider is enabled, and pin X1D11 will be connected to the application clock rather than to port 1D.

SS_APP_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the application clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_SS_APP_PLL_CTL_NUM 0xf

SSWITCH_SS_APP_PLL_CTL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

A secondary on-chip PLL multiplies the input clock up to a higher frequency clock. See Section secondary-pll.

Sub-Fields:

SS_PLL_CTL_INPUT_DIVISOR Oscilator input divider value range from 0 (0x00) to 63 (0x3F). R value.

SS_PLL_CTL_FEEDBACK_MUL Feedback multiplication ratio, range from 1 (0x0001) to 8191 (0x1FFF). F value.

SS_PLL_CTL_POST_DIVISOR Output divider value range from 0 to 7. OD value.

SS_APP_PLL_ENABLE If set to 1, enable the secondary PLL

SS_APP_PLL_INPUT_FROM_SYS_PLL If set to 1, use the output of the core PLL as input, otherwise use the crystal oscillator as input.

SS_APP_PLL_BYPASS If set to 1, set the APP PLL to be bypassed

XS1_SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG_NUM 0x10

SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

if DEBUGN Configures the behavior of the DEBUG_N pin.else Reserved.

Sub-Fields:

GLOBAL_DEBUG_ENABLE_INDEBUG if DEBUGN Set 1 to enable inDebug bit to drive GlobalDebug.else Reserved.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ if DEBUGN Set 1 to enable GlobalDebug to generate debug request to XCore.else Reserved.

XS1_SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG_NUM 0x11

SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

if DEBUGN Configures the behavior of the DEBUG_N pin.else Reserved.

Sub-Fields:

GLOBAL_DEBUG_ENABLE_INDEBUG if DEBUGN Set 1 to enable inDebug bit to drive GlobalDebug.else Reserved.

GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ if DEBUGN Set 1 to enable GlobalDebug to generate debug request to XCore.else Reserved.

XS1_SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER_NUM 0x12

SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls an optional fractional N Divider on the secondary PLL. When enabled, the multiplier F for the secondary PLL will effectively become F+\frac{f+1}{p+1}, f must be less than p. This is achieved by running the PLL with a divider F for the first part of the fractional period, and then F+1 for the remainder of the period. The period is measured in input clocks divided by R+1.

Sub-Fields:

SS_FRAC_N_PERIOD_CYC_CNT The p value for the fractional divider. The period over which the fractional N divider oscillates between F and F+1 is p+1

SS_FRAC_N_F_HIGH_CYC_CNT The f value for the fractional divider. The number of clock cycles in the period that a divider F+1 is used is f+1.

SS_FRAC_N_ENABLE When set to 1, the secondary PLL will be a fractional N divided PLL

XS1_SSWITCH_SS_LPDDR_CONTROLLER_CONFIG_NUM 0x13

SSWITCH_SS_LPDDR_CONTROLLER_CONFIG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls whether LPDDR Controller is enabled, and which core it is accessible to through the mux.

Sub-Fields:

SS_LPDDR_ENABLE When set to 1 this will allow the LPDDR controller to access the pads

SS_LPDDR_MUXTO_CORE1 Defines which xCORE has access to the LPDDR controller via the mux

XS1_SSWITCH_MIPI_CLK_DIVIDER_NUM 0x14

SSWITCH_MIPI_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the clock to the MIPI shim, the hardware block interfacing the MIPI PHY to the xCORE.

Sub-Fields:

SS_SSWITCH_MIPI_CLK_DIV MIPI shim clock divider. When set to X the input clock is divided by 2(X+1).

SS_SSWITCH_MIPI_CLK_DIV_DISABLE MIPI clock divider disable. When set to 0, the divider is enabled.

SS_MIPI_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the MIPI shim clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_MIPI_CFG_CLK_DIVIDER_NUM 0x15

SSWITCH_MIPI_CFG_CLK_DIVIDER system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the clock to the MIPI PHY.

Sub-Fields:

SS_MIPI_CFG_CLK_DIV MIPI PHY clock divider. When set to X, the input clock will be divided by 2(X+1).

SS_MIPI_CFG_CLK_DIV_DISABLE MIPI PHY clock divider disable. When set to 0, the divider is enabled.

SS_MIPI_CFG_CLK_FROM_APP_PLL If set to 1, the secondary PLL is used as a source for the MIPI PHY clock divider. By default, the output of the core PLL is used.

XS1_SSWITCH_GLOBAL_DEBUG_SOURCE_NUM 0x1f

SSWITCH_GLOBAL_DEBUG_SOURCE system switch register number.

Use read_sswitch_reg() to access.

Contains the source of the most recent debug event.

Sub-Fields:

GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG If set, XCore0 is the source of last GlobalDebug event.

GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG If set, XCore1 is the source of last GlobalDebug event.

GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG if DEBUGN If set, external pin, is the source of last GlobalDebug event.else Reserved.

XS1_SSWITCH_USB_XCFGI_REG0_NUM 0xf000

SSWITCH_USB_XCFGI_REG0 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFGI_REG1_NUM 0xf001

SSWITCH_USB_XCFGI_REG1 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFGI_REG2_NUM 0xf002

SSWITCH_USB_XCFGI_REG2 system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_COARSE_TUNE_NUM 0xf003

SSWITCH_USB_XCFG_COARSE_TUNE system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_FINE_TUNE_NUM 0xf004

SSWITCH_USB_XCFG_FINE_TUNE system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MAX_NUM 0xf005

SSWITCH_USB_XCFG_LOCK_RANGE_MAX system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MIN_NUM 0xf006

SSWITCH_USB_XCFG_LOCK_RANGE_MIN system switch register number.

Use read_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_CFG0_NUM 0xf008

SSWITCH_USB_PHY_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register configures the UTMI signals to the USB PHY. See the UTMI specification for more details. The oscillator speed should be set to match the crystal on XIN/XOUT.

Sub-Fields:

USB_PHY_CFG0_UTMI_XCVRSELECT Value of the UTMI XCVRSelect signals to the USB Phy

USB_PHY_CFG0_UTMI_TERMSELECT Value of the UTMI Terminal Select signal to the USB Phy

USB_PHY_CFG0_UTMI_OPMODE Value of the UTMI OpMode signals to the USB Phy

USB_PHY_CFG0_UTMI_SUSPENDM Value of the UTMI SuspendM signal to the USB Phy

USB_PHY_CFG0_DPPULLDOWN Set to 1 to enable the DP Pulldown

USB_PHY_CFG0_DMPULLDOWN Set to 1 to enable the DM Pulldown

USB_PHY_CFG0_TXBITSTUFF_EN Set to 1 to enable USB Tx BitStuffing

USB_PHY_CFG0_PLL_EN Set to 1 to enable the USB PLL

USB_PHY_CFG0_LPM_ALIVE Set to 1 to enable USB LPM

USB_PHY_CFG0_IDPAD_EN Set to 1 to enable the ID PAD

USB_PHY_CFG0_XTLSEL Oscillator freqeuncy. Set to: 0 (10MHz), 1 (12MHz), 2 (25MHz), 3~(30MHz), 4 (19.2MHz), 5 (24MHz), 6 (27MHz), or 7 (40MHz).

XS1_SSWITCH_USB_PHY_CFG1_NUM 0xf009

SSWITCH_USB_PHY_CFG1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_CFG2_NUM 0xf00a

SSWITCH_USB_PHY_CFG2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

USB_PHY_CFG2_PONRST USB PHY reset, set to 1 to take the PHY out of reset

USB_PHY_CFG2_UTMI_RESET UTMI reset, set to 0 to take UTMI out of reset

XS1_SSWITCH_USB_PHY_CFG3_NUM 0xf00b

SSWITCH_USB_PHY_CFG3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

USB_PHY_CFG3_VCONTROL USB VCONTROL

USB_PHY_CFG3_EXTERNAL_TEST_MODE USB EXTERNAL TEST MODE

USB_PHY_CFG3_LS_EN USB LS Enable

USB_PHY_CFG3_UTMI_VCONTROLLOADM USB UTMI VCONTROLLOADM

USB_PHY_CFG3_HS_BIST_MODE USB HS BIST Mode

XS1_SSWITCH_USB_SHIM_CFG_NUM 0xf00c

SSWITCH_USB_SHIM_CFG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register contains the hardware interfacing the USB PHY and the xCORE. It governs how the rxActive, rxValid, and line-state signals are mapped onto two one-bit ports.

Sub-Fields:

USB_SHIM_CFG_AND_RXV_RXA When enabled RxValid output to xCore is AND’d with RxActive

USB_SHIM_CFG_FLAG_MODE USB flag mode selection: 1 selects linestate; 0 selects RxActive and RxValid

XS1_SSWITCH_USB_PHY_XCFGO_REG0_NUM 0xf010

SSWITCH_USB_PHY_XCFGO_REG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_USB_PHY_STATUS_NUM 0xf011

SSWITCH_USB_PHY_STATUS system switch register number.

Use read_sswitch_reg() to access.

Sub-Fields:

USB_PHY_STATUS_UTMI_LINESTATE The UTMI line state; 0: SE0, 1: J, 2: K, 3: SE1

USB_PHY_STATUS_HOSTDISCONNECT Set to 1 if no peripheral is connected

USB_PHY_STATUS_IDPAD 1 if resistance of IDPAD to ground is > 100 kOhm (mini B plug)

USB_PHY_STATUS_BIST_OK 1 if BIST succeeded

USB_PHY_STATUS_DEBUG_OUT Debug output signals

XS1_SSWITCH_USB_SHIM_STATUS_NUM 0xf018

SSWITCH_USB_SHIM_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register does not do anything

XS1_SSWITCH_USB_STATUS_CLR_NUM 0xf019

SSWITCH_USB_STATUS_CLR system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register does not do anything

XS1_SSWITCH_WATCHDOG_CFG_NUM 0xf020

SSWITCH_WATCHDOG_CFG system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to control the watchdog. By default the watchdog is neither counting, nor triggering. When used as a watchdog it should be set to both count and trigger a reset on reaching 0. It can be set to just count for debugging purposes

Sub-Fields:

WATCHDOG_COUNT_ENABLE Set this bit to 1 to enable the watchdog counter.

WATCHDOG_TRIGGER_ENABLE Set this bit to 1 to enable the watchdog to actually reset the chip.

XS1_SSWITCH_WATCHDOG_PRESCALER_NUM 0xf021

SSWITCH_WATCHDOG_PRESCALER system switch register number.

Use read_sswitch_reg() to access.

Register to read out the current divider counter. Can be used to implement a timer that is independent of the PLL.

Sub-Fields:

WATCHDOG_PRESCALER_VALUE This is the current count of the prescaler. One is added one every input clock edge on the oscillator (XIN). When it reaches the prescaler wrap value (see below), it resets to zero and one is subtracted from the watchdog count (see below).

XS1_SSWITCH_WATCHDOG_PRESCALER_WRAP_NUM 0xf022

SSWITCH_WATCHDOG_PRESCALER_WRAP system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to set the watchdog pre-scale divider value.

Sub-Fields:

WATCHDOG_PRESCALER_WRAP_VALUE This is the prescaler divider. The input clock on XIN is divided by this value plus one, before being used to adjust the watchdog count (see below).

XS1_SSWITCH_WATCHDOG_COUNT_NUM 0xf023

SSWITCH_WATCHDOG_COUNT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register to set the value at which the watchdog timer should time out. This register must be overwritten regularly to stop the watchdog from resetting the chip.

Sub-Fields:

WATCHDOG_COUNT_VALUE This is the watchdog counter. It counts down every PRESCALER_WRAP_VALUE input clock edges. When it reaches zero the chip is reset. The maximum time for the watchdog is 2^{12} \times 2^{16} = 2^{28} = 268,435,456 input clocks.

XS1_SSWITCH_WATCHDOG_STATUS_NUM 0xf024

SSWITCH_WATCHDOG_STATUS system switch register number.

Use read_sswitch_reg() to access.

Register that can be used to inspect whether the watchdog has triggered.

Sub-Fields:

WATCHDOG_HAS_TRIGGERED When 1, the watchdog has been triggered. This bit is only reset to 0 on a power-on-reset.

XS1_SSWITCH_MIPI_STATUS0_NUM 0xe013

SSWITCH_MIPI_STATUS0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_STATUS0_OSC_CLK_ACT Test mode osc clock act

MIPI_STATUS0_OSC_CLK_READY Test mode osc clock ready

MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G Test mode bit clk greater than 2400G

MIPI_STATUS0_DATA_CORRECT_LAN0 Test mode data correct lan0

MIPI_STATUS0_DATA_CORRECT_LAN1 Test mode data correct lan1

MIPI_STATUS0_DATA_CORRECT_LAN2 Test mode data correct lan2

MIPI_STATUS0_DA_CDPHY_R100_CTRL0_2D1C Test mode da cdphy r100 control0 2d1c

MIPI_STATUS0_STOPSTATE_CLK Clock lane is in the stop state

MIPI_STATUS0_STOPSTATE_LAN0 Lane 0 is in the stop state

MIPI_STATUS0_STOPSTATE_LAN1 Lane 1 is in the stop state

XS1_SSWITCH_MIPI_SHIM_STATUS_NUM 0xe014

SSWITCH_MIPI_SHIM_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register provides status for the MIPI demuxing logic

Sub-Fields:

MIPI_SHIM_STATUS_REG Set to 1 if an overflow has been detected in the DEMUXER. This is not recoverable, and indicates that the MIPI_CLK is too slow for the rate at which data is received.

XS1_SSWITCH_MIPI_DPHY_CFG0_NUM 0xe018

SSWITCH_MIPI_DPHY_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Controls the reset signals to the MIPI D-PHY

Sub-Fields:

MIPI_DPHY_CFG0_HW_RSTN Reset, set to 1 to take the MIPI PHY out of reset

MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON Set to 1

XS1_SSWITCH_MIPI_DPHY_CFG1_NUM 0xe019

SSWITCH_MIPI_DPHY_CFG1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG1_MP_TEST_EN MIPI dphy config1 mp test mode enable

MIPI_DPHY_CFG1_MP_TEST_MODE_SEL MIPI dphy config1 mp test mode select

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN MIPI dphy config1 cdphy r100 control 0 2d1c efuse enable

MIPI_DPHY_CFG1_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN MIPI dphy config1 cdphy r100 control 0 2d1c efuse in

XS1_SSWITCH_MIPI_DPHY_CFG2_NUM 0xe01a

SSWITCH_MIPI_DPHY_CFG2 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG2_PLL_CLK_SEL MIPI dphy config2 pll clock select

XS1_SSWITCH_MIPI_DPHY_CFG3_NUM 0xe01b

SSWITCH_MIPI_DPHY_CFG3 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Configures the settings for the three lanes, in particular, where the wires appear on the physical interfaces and which ones are enabled.

Sub-Fields:

MIPI_DPHY_CFG3_LANE_SWAP_CLK The DP/DN pair over which to input the clock

MIPI_DPHY_CFG3_LANE_SWAP_LAN0 The DP/DN pair over which to input lane 0

MIPI_DPHY_CFG3_LANE_SWAP_LAN1 The DP/DN pair over which to input lane 1 (if two lanes are needed)

MIPI_DPHY_CFG3_DPDN_SWAP_CLK Set to 1 to swap the DN/DP pair on the clock lane

MIPI_DPHY_CFG3_DPDN_SWAP_LAN0 Set to 1 to swap the DN/DP pair on the lane 0

MIPI_DPHY_CFG3_DPDN_SWAP_LAN1 Set to 1 to swap the DN/DP pair on the lane 1

MIPI_DPHY_CFG3_ENABLE_CLK Set to 0 to disable the clock lane receiver

MIPI_DPHY_CFG3_ENABLE_LAN0 Set to 0 to disable lane 0 receiver

MIPI_DPHY_CFG3_ENABLE_LAN1 Set to 0 to disable lane 1 receiver

XS1_SSWITCH_MIPI_DPHY_CFG4_NUM 0xe01c

SSWITCH_MIPI_DPHY_CFG4 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK MIPI dphy Tclk-settle for clock

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0 MIPI dphy Tclk-settle in lane 0

MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN1 MIPI dphy Tclk-settle in lane 1

XS1_SSWITCH_MIPI_DPHY_CFG5_NUM 0xe01d

SSWITCH_MIPI_DPHY_CFG5 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

MIPI_DPHY_CFG5_DEBUG_MODE_SEL MIPI dphy debug mode select

XS1_SSWITCH_MIPI_SHIM_CFG0_NUM 0xe01f

SSWITCH_MIPI_SHIM_CFG0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register is used to configure the MIPI shim, the hardware block interfacing the MIPI D-PHY to the xCORE. By default the MIPI shim just passes the data from the MIPI D-PHY straight through to the receiver. This register enables you to demultiplex 10-bit, 12-bit, 14-bit and 565-data into 16-bit and 8-bit values. When the demultiplexer is enabled, you must specify the CSI-2 packet type that demultiplexing should apply to. Optionally, you can choose to align add an extra fourth byte for RGB formats, or you can choose to bias the data so that all the data values are signed.

Sub-Fields:

MIPI_SHIM_CFG0_PIXEL_DEMUX_EN Set to 1 to enable the MIPI shim to demultiplex data according to the demux mode and stuff fields. Demuxing is only applied to packets that have the correct datatype.

MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE This field needs to be set to the CSI-2 packet type that needs to be demuxed. Only packets with a matching type are demultiplexed.

MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE Specifies how the demultiplexer operates. The modes supported are 10to16, 12to16, 14to16, rgb565to888, rgb888to888.

MIPI_SHIM_DEMUX_STUFF Set to 1 to add an extra data byte after every RGB565 or RGB888 pixel. This will align pixels to a 32-bit word.

MIPI_SHIM_BIAS Set to 1 to offset the output pixels with -0x80 (for 8-bit outputs) or -0x8000 (for 16-bit outputs). This can be used to make unsigned data signed around zero.

MIPI_SHIM_CFG0_SEL_DEBUG_OUT MIPI shim config0 sel debug out

MIPI_SHIM_CFG0_SEL_DEBUG MIPI shim config0 sel debug

XS1_SSWITCH_LPDDR_IID_ENABLE_NUM 0xc000

SSWITCH_LPDDR_IID_ENABLE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

This register is used to enable one or more threads to route its requests through specified queues. There are three queues (one read-only queue, RO, and two read-write queues, RW0/RW1) and for each thread instruction accesses and data accesses can be routed through specified queues.

Sub-Fields:

LPDDR_IID_ENABLE Two 8-bit masks, one bit per thread. Top eight bits enable instructions to be routed through a specified queue, bottom eight bits enable data to be routed through a specified queue.

XS1_SSWITCH_LPDDR_IID_0_7_NUM 0xc001

SSWITCH_LPDDR_IID_0_7 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

For each thread, this register specifies which queue a data access should be routed through.

Sub-Fields:

LPDDR_IID_0_7 Four bits per thread. Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_SSWITCH_LPDDR_IID_8_15_NUM 0xc002

SSWITCH_LPDDR_IID_8_15 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

For each thread, this register specifies which queue an instruction access should be routed through.

Sub-Fields:

LPDDR_IID_8_15 Four bits per thread. Top bit sets the queue type that this thread should be using (0: RO, 1: RW), further three bits the number of the queue. Valid values for the further three bits are 000 for RO queues, and 000/001 for a RW queue.

XS1_SSWITCH_LPDDR_QUEUE_CONT_NUM 0xc003

SSWITCH_LPDDR_QUEUE_CONT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_QUEUE_CONT Slow sys clock. Set this bit if the tile clock is less than the LPDDR clock.

XS1_SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY_NUM 0xc008

SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_RO_PRI Priority for RO queue. Zero is lowest priority.

XS1_SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY_NUM 0xc009

SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_RW0_PRI Priority for RW queue 0. Zero is lowest priority.

LPDDR_RW1_PRI Priority for RW queue 1. Zero is lowest priority.

XS1_SSWITCH_LPDDR_ARBITRATION_TIMEOUT_NUM 0xc00a

SSWITCH_LPDDR_ARBITRATION_TIMEOUT system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Setting this to a non-zero value guarantees that each queue is served at least every N transactions and prevents starvation.

Sub-Fields:

LPDDR_TOUT Maximum number of transactions until a queue is served. Set to 0 to disable a timeout

XS1_SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND_NUM 0xc010

SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_MTG_CMD MTG Commands status for CSR Read

XS1_SSWITCH_LPDDR_DLL_CONTROL_NUM 0xc014

SSWITCH_LPDDR_DLL_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_CONTROL DLL Control

XS1_SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS_NUM 0xc015

SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_MEASUREMENT_STATUS Measurement status of the DLL

XS1_SSWITCH_LPDDR_DLL_MANUAL_CONTROL_NUM 0xc016

SSWITCH_LPDDR_DLL_MANUAL_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_MANUAL_CONTROL DLL Manual Control

XS1_SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA_NUM 0xc017

SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_DLL_PHY_CALIBRATION_DATA DLL Calibration Data

XS1_SSWITCH_LPDDR_PHY_CONTROL_NUM 0xc01d

SSWITCH_LPDDR_PHY_CONTROL system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_PHY_CONTROL PHY Control

XS1_SSWITCH_LPDDR_LMR_OPCODE_NUM 0xc01e

SSWITCH_LPDDR_LMR_OPCODE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_LMR_OPCODE LMR opcode

XS1_SSWITCH_LPDDR_EMR_OPCODE_NUM 0xc01f

SSWITCH_LPDDR_EMR_OPCODE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Sub-Fields:

LPDDR_EMR_OPCODE EMR opcode

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0_NUM 0xc020

SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register used to set the tREFI, tRAS, tXSR, and tWR timings, all measured in terms of LPDDR clocks

Sub-Fields:

LPDDR_PE_TREFI_CNT LPDDR tREFI clock count

LPDDR_PE_TRAS_CNT LPDDR tRAS clock count

LPDDR_PE_TXSR_CNT LPDDR tXSR clock count

LPDDR_PE_TWR_CNT LPDDR tWR clock count

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1_NUM 0xc021

SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1 system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

Register used to set the tRRC, tRCD, tRP, tRFC, and tRRD timings, all measured in terms of LPDDR clocks. This register is also used to configure the use of 256 bit memories.

Sub-Fields:

LPDDR_PE_TRC_CNT LPDDR tRC clock count

LPDDR_PE_TRCD_CNT LPDDR tRCD clock count

LPDDR_PE_TRP_CNT LPDDR tRP clock count

LPDDR_PE_TRFC_CNT LPDDR tRFC clock count

LPDDR_PE_TRRD_CNT LPDDR tRRD clock count

LPDDR_PE_EN_256M_DEV_SIZE Enable 256 Mbit device

XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS_NUM 0xc022

SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

XS1_SSWITCH_PADCTRL_CLK_NUM 0xd000

SSWITCH_PADCTRL_CLK system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CLK and CLK_N pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CKE_NUM 0xd001

SSWITCH_PADCTRL_CKE system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CKE pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CS_N_NUM 0xd002

SSWITCH_PADCTRL_CS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_WE_N_NUM 0xd003

SSWITCH_PADCTRL_WE_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the WE_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_CAS_N_NUM 0xd004

SSWITCH_PADCTRL_CAS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the CAS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_RAS_N_NUM 0xd005

SSWITCH_PADCTRL_RAS_N system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the RAS_N pin

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_ADDR_NUM 0xd006

SSWITCH_PADCTRL_ADDR system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the A0-A13 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_BA_NUM 0xd007

SSWITCH_PADCTRL_BA system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the BA0 and BA1 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DQ_NUM 0xd008

SSWITCH_PADCTRL_DQ system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the DQ0-DQ15 pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DQS_NUM 0xd009

SSWITCH_PADCTRL_DQS system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the UDQS and LDQS pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

XS1_SSWITCH_PADCTRL_DM_NUM 0xd00a

SSWITCH_PADCTRL_DM system switch register number.

Use read_sswitch_reg() and write_sswitch_reg() to access.

When LPDDR is enabled, this register controls the PAD properties for the UDM and LDM pins

Sub-Fields:

PADCTRL_RECEIVER_ENABLE Set to 1 to enable the input receiver

PADCTRL_PULL Pull resistor: 00 for none; 01 for weak pull-up; 10 for weak pull-down; or 11 for weak bus-keep.

PADCTRL_DRIVE_STRENGTH Pad drive strength: 00 for 2 mA; 01 for 4 mA; 10 for 8 mA; or 11 for 12 mA.

PADCTRL_SCHMITT_TRIGGER_ENABLE Set to 1 to enable the schmitt trigger

PADCTRL_SLEW_RATE_CONTROL Set to 1 to enable slew-rate control

Register Bitfields

These definitions allow packing and unpacking subfields from the other registers.

group xs3aRegisterBitfields

VSR_HEADROOM

Max headroom seen on VST

XS1_VSR_HEADROOM_SHIFT 0x0

XS1_VSR_HEADROOM_SIZE 0x5

XS1_VSR_HEADROOM_MASK (((1 << XS1_VSR_HEADROOM_SIZE) - 1) << XS1_VSR_HEADROOM_SHIFT)

XS1_VSR_HEADROOM(x) (((x) & XS1_VSR_HEADROOM_MASK) >> XS1_VSR_HEADROOM_SHIFT)

Extract the VSR_HEADROOM bitfield from a packed word x and return it.

XS1_VSR_HEADROOM_SET(x, v) (((x) & ~XS1_VSR_HEADROOM_MASK) | (((v) << XS1_VSR_HEADROOM_SHIFT) & XS1_VSR_HEADROOM_MASK))

Pack the value (v) of the VSR_HEADROOM bitfield into a packed word x and return the packed field.

VSR_SHIFT

Shift none/left/right on VLBUT

XS1_VSR_SHIFT_SHIFT 0x6

XS1_VSR_SHIFT_SIZE 0x2

XS1_VSR_SHIFT_MASK (((1 << XS1_VSR_SHIFT_SIZE) - 1) << XS1_VSR_SHIFT_SHIFT)

XS1_VSR_SHIFT(x) (((x) & XS1_VSR_SHIFT_MASK) >> XS1_VSR_SHIFT_SHIFT)

Extract the VSR_SHIFT bitfield from a packed word x and return it.

XS1_VSR_SHIFT_SET(x, v) (((x) & ~XS1_VSR_SHIFT_MASK) | (((v) << XS1_VSR_SHIFT_SHIFT) & XS1_VSR_SHIFT_MASK))

Pack the value (v) of the VSR_SHIFT bitfield into a packed word x and return the packed field.

VSR_TYPE

Data type of VC, VD, RC

XS1_VSR_TYPE_SHIFT 0x8

XS1_VSR_TYPE_SIZE 0x4

XS1_VSR_TYPE_MASK (((1 << XS1_VSR_TYPE_SIZE) - 1) << XS1_VSR_TYPE_SHIFT)

XS1_VSR_TYPE(x) (((x) & XS1_VSR_TYPE_MASK) >> XS1_VSR_TYPE_SHIFT)

Extract the VSR_TYPE bitfield from a packed word x and return it.

XS1_VSR_TYPE_SET(x, v) (((x) & ~XS1_VSR_TYPE_MASK) | (((v) << XS1_VSR_TYPE_SHIFT) & XS1_VSR_TYPE_MASK))

Pack the value (v) of the VSR_TYPE bitfield into a packed word x and return the packed field.

VSR_LENGTH

Log2(convolution length)

XS1_VSR_LENGTH_SHIFT 0xc

XS1_VSR_LENGTH_SIZE 0x4

XS1_VSR_LENGTH_MASK (((1 << XS1_VSR_LENGTH_SIZE) - 1) << XS1_VSR_LENGTH_SHIFT)

XS1_VSR_LENGTH(x) (((x) & XS1_VSR_LENGTH_MASK) >> XS1_VSR_LENGTH_SHIFT)

Extract the VSR_LENGTH bitfield from a packed word x and return it.

XS1_VSR_LENGTH_SET(x, v) (((x) & ~XS1_VSR_LENGTH_MASK) | (((v) << XS1_VSR_LENGTH_SHIFT) & XS1_VSR_LENGTH_MASK))

Pack the value (v) of the VSR_LENGTH bitfield into a packed word x and return the packed field.

SR_EEBLE

1 when events are enabled for the thread.

XS1_SR_EEBLE_SHIFT 0x0

XS1_SR_EEBLE_SIZE 0x1

XS1_SR_EEBLE_MASK (((1 << XS1_SR_EEBLE_SIZE) - 1) << XS1_SR_EEBLE_SHIFT)

XS1_SR_EEBLE(x) (((x) & XS1_SR_EEBLE_MASK) >> XS1_SR_EEBLE_SHIFT)

Extract the SR_EEBLE bitfield from a packed word x and return it.

XS1_SR_EEBLE_SET(x, v) (((x) & ~XS1_SR_EEBLE_MASK) | (((v) << XS1_SR_EEBLE_SHIFT) & XS1_SR_EEBLE_MASK))

Pack the value (v) of the SR_EEBLE bitfield into a packed word x and return the packed field.

SR_IEBLE

1 when interrupts are enabled for the thread.

XS1_SR_IEBLE_SHIFT 0x1

XS1_SR_IEBLE_SIZE 0x1

XS1_SR_IEBLE_MASK (((1 << XS1_SR_IEBLE_SIZE) - 1) << XS1_SR_IEBLE_SHIFT)

XS1_SR_IEBLE(x) (((x) & XS1_SR_IEBLE_MASK) >> XS1_SR_IEBLE_SHIFT)

Extract the SR_IEBLE bitfield from a packed word x and return it.

XS1_SR_IEBLE_SET(x, v) (((x) & ~XS1_SR_IEBLE_MASK) | (((v) << XS1_SR_IEBLE_SHIFT) & XS1_SR_IEBLE_MASK))

Pack the value (v) of the SR_IEBLE bitfield into a packed word x and return the packed field.

SR_INENB

1 when in an event enabling sequence.

XS1_SR_INENB_SHIFT 0x2

XS1_SR_INENB_SIZE 0x1

XS1_SR_INENB_MASK (((1 << XS1_SR_INENB_SIZE) - 1) << XS1_SR_INENB_SHIFT)

XS1_SR_INENB(x) (((x) & XS1_SR_INENB_MASK) >> XS1_SR_INENB_SHIFT)

Extract the SR_INENB bitfield from a packed word x and return it.

XS1_SR_INENB_SET(x, v) (((x) & ~XS1_SR_INENB_MASK) | (((v) << XS1_SR_INENB_SHIFT) & XS1_SR_INENB_MASK))

Pack the value (v) of the SR_INENB bitfield into a packed word x and return the packed field.

SR_ININT

1 when in an interrupt handler.

XS1_SR_ININT_SHIFT 0x3

XS1_SR_ININT_SIZE 0x1

XS1_SR_ININT_MASK (((1 << XS1_SR_ININT_SIZE) - 1) << XS1_SR_ININT_SHIFT)

XS1_SR_ININT(x) (((x) & XS1_SR_ININT_MASK) >> XS1_SR_ININT_SHIFT)

Extract the SR_ININT bitfield from a packed word x and return it.

XS1_SR_ININT_SET(x, v) (((x) & ~XS1_SR_ININT_MASK) | (((v) << XS1_SR_ININT_SHIFT) & XS1_SR_ININT_MASK))

Pack the value (v) of the SR_ININT bitfield into a packed word x and return the packed field.

SR_INK

1 when in kernel mode.

XS1_SR_INK_SHIFT 0x4

XS1_SR_INK_SIZE 0x1

XS1_SR_INK_MASK (((1 << XS1_SR_INK_SIZE) - 1) << XS1_SR_INK_SHIFT)

XS1_SR_INK(x) (((x) & XS1_SR_INK_MASK) >> XS1_SR_INK_SHIFT)

Extract the SR_INK bitfield from a packed word x and return it.

XS1_SR_INK_SET(x, v) (((x) & ~XS1_SR_INK_MASK) | (((v) << XS1_SR_INK_SHIFT) & XS1_SR_INK_MASK))

Pack the value (v) of the SR_INK bitfield into a packed word x and return the packed field.

SR_SINK

Copy of the SSR INK bit.

XS1_SR_SINK_SHIFT 0x5

XS1_SR_SINK_SIZE 0x1

XS1_SR_SINK_MASK (((1 << XS1_SR_SINK_SIZE) - 1) << XS1_SR_SINK_SHIFT)

XS1_SR_SINK(x) (((x) & XS1_SR_SINK_MASK) >> XS1_SR_SINK_SHIFT)

Extract the SR_SINK bitfield from a packed word x and return it.

XS1_SR_SINK_SET(x, v) (((x) & ~XS1_SR_SINK_MASK) | (((v) << XS1_SR_SINK_SHIFT) & XS1_SR_SINK_MASK))

Pack the value (v) of the SR_SINK bitfield into a packed word x and return the packed field.

SR_WAITING

1 when the thread is paused waiting for events, a lock or another resource.

XS1_SR_WAITING_SHIFT 0x6

XS1_SR_WAITING_SIZE 0x1

XS1_SR_WAITING_MASK (((1 << XS1_SR_WAITING_SIZE) - 1) << XS1_SR_WAITING_SHIFT)

XS1_SR_WAITING(x) (((x) & XS1_SR_WAITING_MASK) >> XS1_SR_WAITING_SHIFT)

Extract the SR_WAITING bitfield from a packed word x and return it.

XS1_SR_WAITING_SET(x, v) (((x) & ~XS1_SR_WAITING_MASK) | (((v) << XS1_SR_WAITING_SHIFT) & XS1_SR_WAITING_MASK))

Pack the value (v) of the SR_WAITING bitfield into a packed word x and return the packed field.

SR_FAST

1 when the thread is in fast mode and will continually issue.

XS1_SR_FAST_SHIFT 0x7

XS1_SR_FAST_SIZE 0x1

XS1_SR_FAST_MASK (((1 << XS1_SR_FAST_SIZE) - 1) << XS1_SR_FAST_SHIFT)

XS1_SR_FAST(x) (((x) & XS1_SR_FAST_MASK) >> XS1_SR_FAST_SHIFT)

Extract the SR_FAST bitfield from a packed word x and return it.

XS1_SR_FAST_SET(x, v) (((x) & ~XS1_SR_FAST_MASK) | (((v) << XS1_SR_FAST_SHIFT) & XS1_SR_FAST_MASK))

Pack the value (v) of the SR_FAST bitfield into a packed word x and return the packed field.

SR_DI

1 when in dual issue mode.

XS1_SR_DI_SHIFT 0x8

XS1_SR_DI_SIZE 0x1

XS1_SR_DI_MASK (((1 << XS1_SR_DI_SIZE) - 1) << XS1_SR_DI_SHIFT)

XS1_SR_DI(x) (((x) & XS1_SR_DI_MASK) >> XS1_SR_DI_SHIFT)

Extract the SR_DI bitfield from a packed word x and return it.

XS1_SR_DI_SET(x, v) (((x) & ~XS1_SR_DI_MASK) | (((v) << XS1_SR_DI_SHIFT) & XS1_SR_DI_MASK))

Pack the value (v) of the SR_DI bitfield into a packed word x and return the packed field.

SR_KEDI

1 if, on kernel entry, the thread will switch to dual issue.

XS1_SR_KEDI_SHIFT 0x9

XS1_SR_KEDI_SIZE 0x1

XS1_SR_KEDI_MASK (((1 << XS1_SR_KEDI_SIZE) - 1) << XS1_SR_KEDI_SHIFT)

XS1_SR_KEDI(x) (((x) & XS1_SR_KEDI_MASK) >> XS1_SR_KEDI_SHIFT)

Extract the SR_KEDI bitfield from a packed word x and return it.

XS1_SR_KEDI_SET(x, v) (((x) & ~XS1_SR_KEDI_MASK) | (((v) << XS1_SR_KEDI_SHIFT) & XS1_SR_KEDI_MASK))

Pack the value (v) of the SR_KEDI bitfield into a packed word x and return the packed field.

SR_QUEUE

1 if in high priority mode

XS1_SR_QUEUE_SHIFT 0xa

XS1_SR_QUEUE_SIZE 0x1

XS1_SR_QUEUE_MASK (((1 << XS1_SR_QUEUE_SIZE) - 1) << XS1_SR_QUEUE_SHIFT)

XS1_SR_QUEUE(x) (((x) & XS1_SR_QUEUE_MASK) >> XS1_SR_QUEUE_SHIFT)

Extract the SR_QUEUE bitfield from a packed word x and return it.

XS1_SR_QUEUE_SET(x, v) (((x) & ~XS1_SR_QUEUE_MASK) | (((v) << XS1_SR_QUEUE_SHIFT) & XS1_SR_QUEUE_MASK))

Pack the value (v) of the SR_QUEUE bitfield into a packed word x and return the packed field.

ID_ID

Number of the thread.

XS1_ID_ID_SHIFT 0x0

XS1_ID_ID_SIZE 0x6

XS1_ID_ID_MASK (((1 << XS1_ID_ID_SIZE) - 1) << XS1_ID_ID_SHIFT)

XS1_ID_ID(x) (((x) & XS1_ID_ID_MASK) >> XS1_ID_ID_SHIFT)

Extract the ID_ID bitfield from a packed word x and return it.

XS1_ID_ID_SET(x, v) (((x) & ~XS1_ID_ID_MASK) | (((v) << XS1_ID_ID_SHIFT) & XS1_ID_ID_MASK))

Pack the value (v) of the ID_ID bitfield into a packed word x and return the packed field.

EXCEPTION_TYPE

The exception type.

XS1_EXCEPTION_TYPE_SHIFT 0x0

XS1_EXCEPTION_TYPE_SIZE 0x5

XS1_EXCEPTION_TYPE_MASK (((1 << XS1_EXCEPTION_TYPE_SIZE) - 1) << XS1_EXCEPTION_TYPE_SHIFT)

XS1_EXCEPTION_TYPE(x) (((x) & XS1_EXCEPTION_TYPE_MASK) >> XS1_EXCEPTION_TYPE_SHIFT)

Extract the EXCEPTION_TYPE bitfield from a packed word x and return it.

XS1_EXCEPTION_TYPE_SET(x, v) (((x) & ~XS1_EXCEPTION_TYPE_MASK) | (((v) << XS1_EXCEPTION_TYPE_SHIFT) & XS1_EXCEPTION_TYPE_MASK))

Pack the value (v) of the EXCEPTION_TYPE bitfield into a packed word x and return the packed field.

DBG_T_NUM_NUM

Thread number to be read

XS1_DBG_T_NUM_NUM_SHIFT 0x0

XS1_DBG_T_NUM_NUM_SIZE 0x8

XS1_DBG_T_NUM_NUM_MASK (((1 << XS1_DBG_T_NUM_NUM_SIZE) - 1) << XS1_DBG_T_NUM_NUM_SHIFT)

XS1_DBG_T_NUM_NUM(x) (((x) & XS1_DBG_T_NUM_NUM_MASK) >> XS1_DBG_T_NUM_NUM_SHIFT)

Extract the DBG_T_NUM_NUM bitfield from a packed word x and return it.

XS1_DBG_T_NUM_NUM_SET(x, v) (((x) & ~XS1_DBG_T_NUM_NUM_MASK) | (((v) << XS1_DBG_T_NUM_NUM_SHIFT) & XS1_DBG_T_NUM_NUM_MASK))

Pack the value (v) of the DBG_T_NUM_NUM bitfield into a packed word x and return the packed field.

DBG_T_REG_REG

Register number to be read

XS1_DBG_T_REG_REG_SHIFT 0x0

XS1_DBG_T_REG_REG_SIZE 0x5

XS1_DBG_T_REG_REG_MASK (((1 << XS1_DBG_T_REG_REG_SIZE) - 1) << XS1_DBG_T_REG_REG_SHIFT)

XS1_DBG_T_REG_REG(x) (((x) & XS1_DBG_T_REG_REG_MASK) >> XS1_DBG_T_REG_REG_SHIFT)

Extract the DBG_T_REG_REG bitfield from a packed word x and return it.

XS1_DBG_T_REG_REG_SET(x, v) (((x) & ~XS1_DBG_T_REG_REG_MASK) | (((v) << XS1_DBG_T_REG_REG_SHIFT) & XS1_DBG_T_REG_REG_MASK))

Pack the value (v) of the DBG_T_REG_REG bitfield into a packed word x and return the packed field.

BRK_ENABLE

When 1 the breakpoint is enabled.

XS1_BRK_ENABLE_SHIFT 0x0

XS1_BRK_ENABLE_SIZE 0x1

XS1_BRK_ENABLE_MASK (((1 << XS1_BRK_ENABLE_SIZE) - 1) << XS1_BRK_ENABLE_SHIFT)

XS1_BRK_ENABLE(x) (((x) & XS1_BRK_ENABLE_MASK) >> XS1_BRK_ENABLE_SHIFT)

Extract the BRK_ENABLE bitfield from a packed word x and return it.

XS1_BRK_ENABLE_SET(x, v) (((x) & ~XS1_BRK_ENABLE_MASK) | (((v) << XS1_BRK_ENABLE_SHIFT) & XS1_BRK_ENABLE_MASK))

Pack the value (v) of the BRK_ENABLE bitfield into a packed word x and return the packed field.

ALL_BITS

Value.

XS1_ALL_BITS_SHIFT 0x0

XS1_ALL_BITS_SIZE 0x20

XS1_ALL_BITS_MASK (((1 << XS1_ALL_BITS_SIZE) - 1) << XS1_ALL_BITS_SHIFT)

XS1_ALL_BITS(x) (((x) & XS1_ALL_BITS_MASK) >> XS1_ALL_BITS_SHIFT)

Extract the ALL_BITS bitfield from a packed word x and return it.

XS1_ALL_BITS_SET(x, v) (((x) & ~XS1_ALL_BITS_MASK) | (((v) << XS1_ALL_BITS_SHIFT) & XS1_ALL_BITS_MASK))

Pack the value (v) of the ALL_BITS bitfield into a packed word x and return the packed field.

KEP_ADDRESS_BITS

KEP Address bits

XS1_KEP_ADDRESS_BITS_SHIFT 0x7

XS1_KEP_ADDRESS_BITS_SIZE 0x19

XS1_KEP_ADDRESS_BITS_MASK (((1 << XS1_KEP_ADDRESS_BITS_SIZE) - 1) << XS1_KEP_ADDRESS_BITS_SHIFT)

XS1_KEP_ADDRESS_BITS(x) (((x) & XS1_KEP_ADDRESS_BITS_MASK) >> XS1_KEP_ADDRESS_BITS_SHIFT)

Extract the KEP_ADDRESS_BITS bitfield from a packed word x and return it.

XS1_KEP_ADDRESS_BITS_SET(x, v) (((x) & ~XS1_KEP_ADDRESS_BITS_MASK) | (((v) << XS1_KEP_ADDRESS_BITS_SHIFT) & XS1_KEP_ADDRESS_BITS_MASK))

Pack the value (v) of the KEP_ADDRESS_BITS bitfield into a packed word x and return the packed field.

WORD_ADDRESS_BITS

Most significant 16 bits of all addresses.

XS1_WORD_ADDRESS_BITS_SHIFT 0x2

XS1_WORD_ADDRESS_BITS_SIZE 0x1e

XS1_WORD_ADDRESS_BITS_MASK (((1 << XS1_WORD_ADDRESS_BITS_SIZE) - 1) << XS1_WORD_ADDRESS_BITS_SHIFT)

XS1_WORD_ADDRESS_BITS(x) (((x) & XS1_WORD_ADDRESS_BITS_MASK) >> XS1_WORD_ADDRESS_BITS_SHIFT)

Extract the WORD_ADDRESS_BITS bitfield from a packed word x and return it.

XS1_WORD_ADDRESS_BITS_SET(x, v) (((x) & ~XS1_WORD_ADDRESS_BITS_MASK) | (((v) << XS1_WORD_ADDRESS_BITS_SHIFT) & XS1_WORD_ADDRESS_BITS_MASK))

Pack the value (v) of the WORD_ADDRESS_BITS bitfield into a packed word x and return the packed field.

VECTOR_BASE

The event and interrupt vectors.

XS1_VECTOR_BASE_SHIFT 0x13

XS1_VECTOR_BASE_SIZE 0xd

XS1_VECTOR_BASE_MASK (((1 << XS1_VECTOR_BASE_SIZE) - 1) << XS1_VECTOR_BASE_SHIFT)

XS1_VECTOR_BASE(x) (((x) & XS1_VECTOR_BASE_MASK) >> XS1_VECTOR_BASE_SHIFT)

Extract the VECTOR_BASE bitfield from a packed word x and return it.

XS1_VECTOR_BASE_SET(x, v) (((x) & ~XS1_VECTOR_BASE_MASK) | (((v) << XS1_VECTOR_BASE_SHIFT) & XS1_VECTOR_BASE_MASK))

Pack the value (v) of the VECTOR_BASE bitfield into a packed word x and return the packed field.

IBRK_CONDITION

When 0 break when PC == IBREAK_ADDR. When 1 = break when PC != IBREAK_ADDR.

XS1_IBRK_CONDITION_SHIFT 0x1

XS1_IBRK_CONDITION_SIZE 0x1

XS1_IBRK_CONDITION_MASK (((1 << XS1_IBRK_CONDITION_SIZE) - 1) << XS1_IBRK_CONDITION_SHIFT)

XS1_IBRK_CONDITION(x) (((x) & XS1_IBRK_CONDITION_MASK) >> XS1_IBRK_CONDITION_SHIFT)

Extract the IBRK_CONDITION bitfield from a packed word x and return it.

XS1_IBRK_CONDITION_SET(x, v) (((x) & ~XS1_IBRK_CONDITION_MASK) | (((v) << XS1_IBRK_CONDITION_SHIFT) & XS1_IBRK_CONDITION_MASK))

Pack the value (v) of the IBRK_CONDITION bitfield into a packed word x and return the packed field.

DBRK_CONDITION

Determines the break condition: 0 = A AND B, 1 = A OR B.

XS1_DBRK_CONDITION_SHIFT 0x1

XS1_DBRK_CONDITION_SIZE 0x1

XS1_DBRK_CONDITION_MASK (((1 << XS1_DBRK_CONDITION_SIZE) - 1) << XS1_DBRK_CONDITION_SHIFT)

XS1_DBRK_CONDITION(x) (((x) & XS1_DBRK_CONDITION_MASK) >> XS1_DBRK_CONDITION_SHIFT)

Extract the DBRK_CONDITION bitfield from a packed word x and return it.

XS1_DBRK_CONDITION_SET(x, v) (((x) & ~XS1_DBRK_CONDITION_MASK) | (((v) << XS1_DBRK_CONDITION_SHIFT) & XS1_DBRK_CONDITION_MASK))

Pack the value (v) of the DBRK_CONDITION bitfield into a packed word x and return the packed field.

RBRK_CONDITION

When 0 break when condition A is met. When 1 = break when condition B is met.

XS1_RBRK_CONDITION_SHIFT 0x1

XS1_RBRK_CONDITION_SIZE 0x1

XS1_RBRK_CONDITION_MASK (((1 << XS1_RBRK_CONDITION_SIZE) - 1) << XS1_RBRK_CONDITION_SHIFT)

XS1_RBRK_CONDITION(x) (((x) & XS1_RBRK_CONDITION_MASK) >> XS1_RBRK_CONDITION_SHIFT)

Extract the RBRK_CONDITION bitfield from a packed word x and return it.

XS1_RBRK_CONDITION_SET(x, v) (((x) & ~XS1_RBRK_CONDITION_MASK) | (((v) << XS1_RBRK_CONDITION_SHIFT) & XS1_RBRK_CONDITION_MASK))

Pack the value (v) of the RBRK_CONDITION bitfield into a packed word x and return the packed field.

BRK_LOAD

When 1 the breakpoints will be be triggered on loads.

XS1_BRK_LOAD_SHIFT 0x2

XS1_BRK_LOAD_SIZE 0x1

XS1_BRK_LOAD_MASK (((1 << XS1_BRK_LOAD_SIZE) - 1) << XS1_BRK_LOAD_SHIFT)

XS1_BRK_LOAD(x) (((x) & XS1_BRK_LOAD_MASK) >> XS1_BRK_LOAD_SHIFT)

Extract the BRK_LOAD bitfield from a packed word x and return it.

XS1_BRK_LOAD_SET(x, v) (((x) & ~XS1_BRK_LOAD_MASK) | (((v) << XS1_BRK_LOAD_SHIFT) & XS1_BRK_LOAD_MASK))

Pack the value (v) of the BRK_LOAD bitfield into a packed word x and return the packed field.

BRK_THREADS

A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread.

XS1_BRK_THREADS_SHIFT 0x10

XS1_BRK_THREADS_SIZE 0x8

XS1_BRK_THREADS_MASK (((1 << XS1_BRK_THREADS_SIZE) - 1) << XS1_BRK_THREADS_SHIFT)

XS1_BRK_THREADS(x) (((x) & XS1_BRK_THREADS_MASK) >> XS1_BRK_THREADS_SHIFT)

Extract the BRK_THREADS bitfield from a packed word x and return it.

XS1_BRK_THREADS_SET(x, v) (((x) & ~XS1_BRK_THREADS_MASK) | (((v) << XS1_BRK_THREADS_SHIFT) & XS1_BRK_THREADS_MASK))

Pack the value (v) of the BRK_THREADS bitfield into a packed word x and return the packed field.

DBG_TYPE_CAUSE

Indicates the cause of the debug interrupt

1: Host initiated a debug interrupt through JTAG

2: Program executed a DCALL instruction

3: Instruction breakpoint

4: Data watch point

5: Resource watch point

XS1_DBG_TYPE_CAUSE_SHIFT 0x0

XS1_DBG_TYPE_CAUSE_SIZE 0x3

XS1_DBG_TYPE_CAUSE_MASK (((1 << XS1_DBG_TYPE_CAUSE_SIZE) - 1) << XS1_DBG_TYPE_CAUSE_SHIFT)

XS1_DBG_TYPE_CAUSE(x) (((x) & XS1_DBG_TYPE_CAUSE_MASK) >> XS1_DBG_TYPE_CAUSE_SHIFT)

Extract the DBG_TYPE_CAUSE bitfield from a packed word x and return it.

XS1_DBG_TYPE_CAUSE_SET(x, v) (((x) & ~XS1_DBG_TYPE_CAUSE_MASK) | (((v) << XS1_DBG_TYPE_CAUSE_SHIFT) & XS1_DBG_TYPE_CAUSE_MASK))

Pack the value (v) of the DBG_TYPE_CAUSE bitfield into a packed word x and return the packed field.

DBG_TYPE_T_NUM

Number of thread which caused the debug interrupt (always 0 in the case of =HOST=).

XS1_DBG_TYPE_T_NUM_SHIFT 0x8

XS1_DBG_TYPE_T_NUM_SIZE 0x8

XS1_DBG_TYPE_T_NUM_MASK (((1 << XS1_DBG_TYPE_T_NUM_SIZE) - 1) << XS1_DBG_TYPE_T_NUM_SHIFT)

XS1_DBG_TYPE_T_NUM(x) (((x) & XS1_DBG_TYPE_T_NUM_MASK) >> XS1_DBG_TYPE_T_NUM_SHIFT)

Extract the DBG_TYPE_T_NUM bitfield from a packed word x and return it.

XS1_DBG_TYPE_T_NUM_SET(x, v) (((x) & ~XS1_DBG_TYPE_T_NUM_MASK) | (((v) << XS1_DBG_TYPE_T_NUM_SHIFT) & XS1_DBG_TYPE_T_NUM_MASK))

Pack the value (v) of the DBG_TYPE_T_NUM bitfield into a packed word x and return the packed field.

DBG_TYPE_HW_NUM

Number of the hardware breakpoint/watchpoint which caused the interrupt (always 0 for =HOST= and =DCALL=). If multiple breakpoints/watchpoints trigger at once, the lowest number is taken.

XS1_DBG_TYPE_HW_NUM_SHIFT 0x10

XS1_DBG_TYPE_HW_NUM_SIZE 0x2

XS1_DBG_TYPE_HW_NUM_MASK (((1 << XS1_DBG_TYPE_HW_NUM_SIZE) - 1) << XS1_DBG_TYPE_HW_NUM_SHIFT)

XS1_DBG_TYPE_HW_NUM(x) (((x) & XS1_DBG_TYPE_HW_NUM_MASK) >> XS1_DBG_TYPE_HW_NUM_SHIFT)

Extract the DBG_TYPE_HW_NUM bitfield from a packed word x and return it.

XS1_DBG_TYPE_HW_NUM_SET(x, v) (((x) & ~XS1_DBG_TYPE_HW_NUM_MASK) | (((v) << XS1_DBG_TYPE_HW_NUM_SHIFT) & XS1_DBG_TYPE_HW_NUM_MASK))

Pack the value (v) of the DBG_TYPE_HW_NUM bitfield into a packed word x and return the packed field.

DBG_RUN_CTRL_STOP

1-hot vector defining which threads are stopped when not in debug mode. Every bit which is set prevents the respective thread from running.

XS1_DBG_RUN_CTRL_STOP_SHIFT 0x0

XS1_DBG_RUN_CTRL_STOP_SIZE 0x8

XS1_DBG_RUN_CTRL_STOP_MASK (((1 << XS1_DBG_RUN_CTRL_STOP_SIZE) - 1) << XS1_DBG_RUN_CTRL_STOP_SHIFT)

XS1_DBG_RUN_CTRL_STOP(x) (((x) & XS1_DBG_RUN_CTRL_STOP_MASK) >> XS1_DBG_RUN_CTRL_STOP_SHIFT)

Extract the DBG_RUN_CTRL_STOP bitfield from a packed word x and return it.

XS1_DBG_RUN_CTRL_STOP_SET(x, v) (((x) & ~XS1_DBG_RUN_CTRL_STOP_MASK) | (((v) << XS1_DBG_RUN_CTRL_STOP_SHIFT) & XS1_DBG_RUN_CTRL_STOP_MASK))

Pack the value (v) of the DBG_RUN_CTRL_STOP bitfield into a packed word x and return the packed field.

XCORE_CTRL0_EXTMEM_ENABLE

Enable External memory interface

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SHIFT 0x0

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SIZE 0x1

XS1_XCORE_CTRL0_EXTMEM_ENABLE_MASK (((1 << XS1_XCORE_CTRL0_EXTMEM_ENABLE_SIZE) - 1) << XS1_XCORE_CTRL0_EXTMEM_ENABLE_SHIFT)

XS1_XCORE_CTRL0_EXTMEM_ENABLE(x) (((x) & XS1_XCORE_CTRL0_EXTMEM_ENABLE_MASK) >> XS1_XCORE_CTRL0_EXTMEM_ENABLE_SHIFT)

Extract the XCORE_CTRL0_EXTMEM_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_EXTMEM_ENABLE_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_EXTMEM_ENABLE_MASK) | (((v) << XS1_XCORE_CTRL0_EXTMEM_ENABLE_SHIFT) & XS1_XCORE_CTRL0_EXTMEM_ENABLE_MASK))

Pack the value (v) of the XCORE_CTRL0_EXTMEM_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_USB_ENABLE

Enable the USB hardware support module

XS1_XCORE_CTRL0_USB_ENABLE_SHIFT 0x1

XS1_XCORE_CTRL0_USB_ENABLE_SIZE 0x1

XS1_XCORE_CTRL0_USB_ENABLE_MASK (((1 << XS1_XCORE_CTRL0_USB_ENABLE_SIZE) - 1) << XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)

XS1_XCORE_CTRL0_USB_ENABLE(x) (((x) & XS1_XCORE_CTRL0_USB_ENABLE_MASK) >> XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)

Extract the XCORE_CTRL0_USB_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_USB_ENABLE_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_USB_ENABLE_MASK) | (((v) << XS1_XCORE_CTRL0_USB_ENABLE_SHIFT) & XS1_XCORE_CTRL0_USB_ENABLE_MASK))

Pack the value (v) of the XCORE_CTRL0_USB_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_CLK_DIVIDER_EN

Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes.

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT 0x4

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE 0x1

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK (((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE) - 1) << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)

XS1_XCORE_CTRL0_CLK_DIVIDER_EN(x) (((x) & XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) >> XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)

Extract the XCORE_CTRL0_CLK_DIVIDER_EN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) | (((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT) & XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK))

Pack the value (v) of the XCORE_CTRL0_CLK_DIVIDER_EN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_CLK_DIVIDER_DYN

Select the dynamic mode (1) for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active threads are paused. In static mode the clock divider is always enabled.

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT 0x5

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE 0x1

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK (((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE) - 1) << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN(x) (((x) & XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) >> XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)

Extract the XCORE_CTRL0_CLK_DIVIDER_DYN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) | (((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT) & XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK))

Pack the value (v) of the XCORE_CTRL0_CLK_DIVIDER_DYN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_MIPI_ENABLE

Enable MIPI interface periph ports

XS1_XCORE_CTRL0_MIPI_ENABLE_SHIFT 0x8

XS1_XCORE_CTRL0_MIPI_ENABLE_SIZE 0x1

XS1_XCORE_CTRL0_MIPI_ENABLE_MASK (((1 << XS1_XCORE_CTRL0_MIPI_ENABLE_SIZE) - 1) << XS1_XCORE_CTRL0_MIPI_ENABLE_SHIFT)

XS1_XCORE_CTRL0_MIPI_ENABLE(x) (((x) & XS1_XCORE_CTRL0_MIPI_ENABLE_MASK) >> XS1_XCORE_CTRL0_MIPI_ENABLE_SHIFT)

Extract the XCORE_CTRL0_MIPI_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_MIPI_ENABLE_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_MIPI_ENABLE_MASK) | (((v) << XS1_XCORE_CTRL0_MIPI_ENABLE_SHIFT) & XS1_XCORE_CTRL0_MIPI_ENABLE_MASK))

Pack the value (v) of the XCORE_CTRL0_MIPI_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_MEMSLEEP_ENABLE

Enable memory auto-sleep feature

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SHIFT 0x9

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SIZE 0x1

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_MASK (((1 << XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SIZE) - 1) << XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SHIFT)

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE(x) (((x) & XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_MASK) >> XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SHIFT)

Extract the XCORE_CTRL0_MEMSLEEP_ENABLE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_MASK) | (((v) << XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_SHIFT) & XS1_XCORE_CTRL0_MEMSLEEP_ENABLE_MASK))

Pack the value (v) of the XCORE_CTRL0_MEMSLEEP_ENABLE bitfield into a packed word x and return the packed field.

XCORE_CTRL0_RAMSHUTDOWN

Disable RAMs to save power (contents will be lost)

XS1_XCORE_CTRL0_RAMSHUTDOWN_SHIFT 0xa

XS1_XCORE_CTRL0_RAMSHUTDOWN_SIZE 0x1

XS1_XCORE_CTRL0_RAMSHUTDOWN_MASK (((1 << XS1_XCORE_CTRL0_RAMSHUTDOWN_SIZE) - 1) << XS1_XCORE_CTRL0_RAMSHUTDOWN_SHIFT)

XS1_XCORE_CTRL0_RAMSHUTDOWN(x) (((x) & XS1_XCORE_CTRL0_RAMSHUTDOWN_MASK) >> XS1_XCORE_CTRL0_RAMSHUTDOWN_SHIFT)

Extract the XCORE_CTRL0_RAMSHUTDOWN bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_RAMSHUTDOWN_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_RAMSHUTDOWN_MASK) | (((v) << XS1_XCORE_CTRL0_RAMSHUTDOWN_SHIFT) & XS1_XCORE_CTRL0_RAMSHUTDOWN_MASK))

Pack the value (v) of the XCORE_CTRL0_RAMSHUTDOWN bitfield into a packed word x and return the packed field.

XCORE_CTRL0_EXTMEM_DEVICE_SIZE

Specify size of a connected LPDDR device (options are: 128,256,512Mbits, 1Gbit),

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SHIFT 0xb

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SIZE 0x2

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_MASK (((1 << XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SIZE) - 1) << XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SHIFT)

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE(x) (((x) & XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_MASK) >> XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SHIFT)

Extract the XCORE_CTRL0_EXTMEM_DEVICE_SIZE bitfield from a packed word x and return it.

XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SET(x, v) (((x) & ~XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_MASK) | (((v) << XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_SHIFT) & XS1_XCORE_CTRL0_EXTMEM_DEVICE_SIZE_MASK))

Pack the value (v) of the XCORE_CTRL0_EXTMEM_DEVICE_SIZE bitfield into a packed word x and return the packed field.

BOOT_CONFIG_PLL_MODE_PINS

The boot PLL mode pin value.

XS1_BOOT_CONFIG_PLL_MODE_PINS_SHIFT 0x0

XS1_BOOT_CONFIG_PLL_MODE_PINS_SIZE 0x2

XS1_BOOT_CONFIG_PLL_MODE_PINS_MASK (((1 << XS1_BOOT_CONFIG_PLL_MODE_PINS_SIZE) - 1) << XS1_BOOT_CONFIG_PLL_MODE_PINS_SHIFT)

XS1_BOOT_CONFIG_PLL_MODE_PINS(x) (((x) & XS1_BOOT_CONFIG_PLL_MODE_PINS_MASK) >> XS1_BOOT_CONFIG_PLL_MODE_PINS_SHIFT)

Extract the BOOT_CONFIG_PLL_MODE_PINS bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_PLL_MODE_PINS_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_PLL_MODE_PINS_MASK) | (((v) << XS1_BOOT_CONFIG_PLL_MODE_PINS_SHIFT) & XS1_BOOT_CONFIG_PLL_MODE_PINS_MASK))

Pack the value (v) of the BOOT_CONFIG_PLL_MODE_PINS bitfield into a packed word x and return the packed field.

BOOT_CONFIG_BOOT_FROM_JTAG

Boot ROM boots from JTAG

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SHIFT 0x2

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SIZE 0x1

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_MASK (((1 << XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SIZE) - 1) << XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SHIFT)

XS1_BOOT_CONFIG_BOOT_FROM_JTAG(x) (((x) & XS1_BOOT_CONFIG_BOOT_FROM_JTAG_MASK) >> XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SHIFT)

Extract the BOOT_CONFIG_BOOT_FROM_JTAG bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_BOOT_FROM_JTAG_MASK) | (((v) << XS1_BOOT_CONFIG_BOOT_FROM_JTAG_SHIFT) & XS1_BOOT_CONFIG_BOOT_FROM_JTAG_MASK))

Pack the value (v) of the BOOT_CONFIG_BOOT_FROM_JTAG bitfield into a packed word x and return the packed field.

BOOT_CONFIG_BOOT_FROM_RAM

Boot ROM boots from RAM

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SHIFT 0x3

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SIZE 0x1

XS1_BOOT_CONFIG_BOOT_FROM_RAM_MASK (((1 << XS1_BOOT_CONFIG_BOOT_FROM_RAM_SIZE) - 1) << XS1_BOOT_CONFIG_BOOT_FROM_RAM_SHIFT)

XS1_BOOT_CONFIG_BOOT_FROM_RAM(x) (((x) & XS1_BOOT_CONFIG_BOOT_FROM_RAM_MASK) >> XS1_BOOT_CONFIG_BOOT_FROM_RAM_SHIFT)

Extract the BOOT_CONFIG_BOOT_FROM_RAM bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_BOOT_FROM_RAM_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_BOOT_FROM_RAM_MASK) | (((v) << XS1_BOOT_CONFIG_BOOT_FROM_RAM_SHIFT) & XS1_BOOT_CONFIG_BOOT_FROM_RAM_MASK))

Pack the value (v) of the BOOT_CONFIG_BOOT_FROM_RAM bitfield into a packed word x and return the packed field.

BOOT_CONFIG_DISABLE_OTP_POLL

Cause the ROM to not poll the OTP for correct read levels

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SHIFT 0x4

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SIZE 0x1

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_MASK (((1 << XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SIZE) - 1) << XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SHIFT)

XS1_BOOT_CONFIG_DISABLE_OTP_POLL(x) (((x) & XS1_BOOT_CONFIG_DISABLE_OTP_POLL_MASK) >> XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SHIFT)

Extract the BOOT_CONFIG_DISABLE_OTP_POLL bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_DISABLE_OTP_POLL_MASK) | (((v) << XS1_BOOT_CONFIG_DISABLE_OTP_POLL_SHIFT) & XS1_BOOT_CONFIG_DISABLE_OTP_POLL_MASK))

Pack the value (v) of the BOOT_CONFIG_DISABLE_OTP_POLL bitfield into a packed word x and return the packed field.

BOOT_CONFIG_CORE1_POWER_DOWN_N

Indicates if core1 has been powered off

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SHIFT 0x5

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SIZE 0x1

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_MASK (((1 << XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SIZE) - 1) << XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SHIFT)

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N(x) (((x) & XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_MASK) >> XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SHIFT)

Extract the BOOT_CONFIG_CORE1_POWER_DOWN_N bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_MASK) | (((v) << XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_SHIFT) & XS1_BOOT_CONFIG_CORE1_POWER_DOWN_N_MASK))

Pack the value (v) of the BOOT_CONFIG_CORE1_POWER_DOWN_N bitfield into a packed word x and return the packed field.

BOOT_CONFIG_SECURE_BOOT

Overwrite BOOT_MODE.

XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT 0x8

XS1_BOOT_CONFIG_SECURE_BOOT_SIZE 0x1

XS1_BOOT_CONFIG_SECURE_BOOT_MASK (((1 << XS1_BOOT_CONFIG_SECURE_BOOT_SIZE) - 1) << XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)

XS1_BOOT_CONFIG_SECURE_BOOT(x) (((x) & XS1_BOOT_CONFIG_SECURE_BOOT_MASK) >> XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)

Extract the BOOT_CONFIG_SECURE_BOOT bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_SECURE_BOOT_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_SECURE_BOOT_MASK) | (((v) << XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT) & XS1_BOOT_CONFIG_SECURE_BOOT_MASK))

Pack the value (v) of the BOOT_CONFIG_SECURE_BOOT bitfield into a packed word x and return the packed field.

BOOT_CONFIG_PROCESSOR

Processor number.

XS1_BOOT_CONFIG_PROCESSOR_SHIFT 0x10

XS1_BOOT_CONFIG_PROCESSOR_SIZE 0x8

XS1_BOOT_CONFIG_PROCESSOR_MASK (((1 << XS1_BOOT_CONFIG_PROCESSOR_SIZE) - 1) << XS1_BOOT_CONFIG_PROCESSOR_SHIFT)

XS1_BOOT_CONFIG_PROCESSOR(x) (((x) & XS1_BOOT_CONFIG_PROCESSOR_MASK) >> XS1_BOOT_CONFIG_PROCESSOR_SHIFT)

Extract the BOOT_CONFIG_PROCESSOR bitfield from a packed word x and return it.

XS1_BOOT_CONFIG_PROCESSOR_SET(x, v) (((x) & ~XS1_BOOT_CONFIG_PROCESSOR_MASK) | (((v) << XS1_BOOT_CONFIG_PROCESSOR_SHIFT) & XS1_BOOT_CONFIG_PROCESSOR_MASK))

Pack the value (v) of the BOOT_CONFIG_PROCESSOR bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_XCORE_JTAG

Disable access to XCore’s JTAG debug TAP

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SHIFT 0x0

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SIZE 0x1

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_MASK (((1 << XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SIZE) - 1) << XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SHIFT)

XS1_SECUR_CFG_DISABLE_XCORE_JTAG(x) (((x) & XS1_SECUR_CFG_DISABLE_XCORE_JTAG_MASK) >> XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SHIFT)

Extract the SECUR_CFG_DISABLE_XCORE_JTAG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SET(x, v) (((x) & ~XS1_SECUR_CFG_DISABLE_XCORE_JTAG_MASK) | (((v) << XS1_SECUR_CFG_DISABLE_XCORE_JTAG_SHIFT) & XS1_SECUR_CFG_DISABLE_XCORE_JTAG_MASK))

Pack the value (v) of the SECUR_CFG_DISABLE_XCORE_JTAG bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_XCORE_PLINK

Disable PLinks

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SHIFT 0x1

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SIZE 0x1

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_MASK (((1 << XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SIZE) - 1) << XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SHIFT)

XS1_SECUR_CFG_DISABLE_XCORE_PLINK(x) (((x) & XS1_SECUR_CFG_DISABLE_XCORE_PLINK_MASK) >> XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SHIFT)

Extract the SECUR_CFG_DISABLE_XCORE_PLINK bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SET(x, v) (((x) & ~XS1_SECUR_CFG_DISABLE_XCORE_PLINK_MASK) | (((v) << XS1_SECUR_CFG_DISABLE_XCORE_PLINK_SHIFT) & XS1_SECUR_CFG_DISABLE_XCORE_PLINK_MASK))

Pack the value (v) of the SECUR_CFG_DISABLE_XCORE_PLINK bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_PLL_JTAG

Disable JTAG access to the PLL/BOOT configuration registers

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SHIFT 0x4

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SIZE 0x1

XS1_SECUR_CFG_DISABLE_PLL_JTAG_MASK (((1 << XS1_SECUR_CFG_DISABLE_PLL_JTAG_SIZE) - 1) << XS1_SECUR_CFG_DISABLE_PLL_JTAG_SHIFT)

XS1_SECUR_CFG_DISABLE_PLL_JTAG(x) (((x) & XS1_SECUR_CFG_DISABLE_PLL_JTAG_MASK) >> XS1_SECUR_CFG_DISABLE_PLL_JTAG_SHIFT)

Extract the SECUR_CFG_DISABLE_PLL_JTAG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_PLL_JTAG_SET(x, v) (((x) & ~XS1_SECUR_CFG_DISABLE_PLL_JTAG_MASK) | (((v) << XS1_SECUR_CFG_DISABLE_PLL_JTAG_SHIFT) & XS1_SECUR_CFG_DISABLE_PLL_JTAG_MASK))

Pack the value (v) of the SECUR_CFG_DISABLE_PLL_JTAG bitfield into a packed word x and return the packed field.

SECUR_CFG_SECURE_BOOT

Override boot mode and read boot image from OTP

XS1_SECUR_CFG_SECURE_BOOT_SHIFT 0x5

XS1_SECUR_CFG_SECURE_BOOT_SIZE 0x1

XS1_SECUR_CFG_SECURE_BOOT_MASK (((1 << XS1_SECUR_CFG_SECURE_BOOT_SIZE) - 1) << XS1_SECUR_CFG_SECURE_BOOT_SHIFT)

XS1_SECUR_CFG_SECURE_BOOT(x) (((x) & XS1_SECUR_CFG_SECURE_BOOT_MASK) >> XS1_SECUR_CFG_SECURE_BOOT_SHIFT)

Extract the SECUR_CFG_SECURE_BOOT bitfield from a packed word x and return it.

XS1_SECUR_CFG_SECURE_BOOT_SET(x, v) (((x) & ~XS1_SECUR_CFG_SECURE_BOOT_MASK) | (((v) << XS1_SECUR_CFG_SECURE_BOOT_SHIFT) & XS1_SECUR_CFG_SECURE_BOOT_MASK))

Pack the value (v) of the SECUR_CFG_SECURE_BOOT bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_COMBINED

Combine OTP into a single address-space for reading.

XS1_SECUR_CFG_OTP_COMBINED_SHIFT 0x7

XS1_SECUR_CFG_OTP_COMBINED_SIZE 0x1

XS1_SECUR_CFG_OTP_COMBINED_MASK (((1 << XS1_SECUR_CFG_OTP_COMBINED_SIZE) - 1) << XS1_SECUR_CFG_OTP_COMBINED_SHIFT)

XS1_SECUR_CFG_OTP_COMBINED(x) (((x) & XS1_SECUR_CFG_OTP_COMBINED_MASK) >> XS1_SECUR_CFG_OTP_COMBINED_SHIFT)

Extract the SECUR_CFG_OTP_COMBINED bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_COMBINED_SET(x, v) (((x) & ~XS1_SECUR_CFG_OTP_COMBINED_MASK) | (((v) << XS1_SECUR_CFG_OTP_COMBINED_SHIFT) & XS1_SECUR_CFG_OTP_COMBINED_MASK))

Pack the value (v) of the SECUR_CFG_OTP_COMBINED bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_PROGRAM_DISABLE

Prevent access to OTP SBPI interface to prevent programming and other functions.

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SHIFT 0x8

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SIZE 0x1

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_MASK (((1 << XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SIZE) - 1) << XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SHIFT)

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE(x) (((x) & XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_MASK) >> XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SHIFT)

Extract the SECUR_CFG_OTP_PROGRAM_DISABLE bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SET(x, v) (((x) & ~XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_MASK) | (((v) << XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_SHIFT) & XS1_SECUR_CFG_OTP_PROGRAM_DISABLE_MASK))

Pack the value (v) of the SECUR_CFG_OTP_PROGRAM_DISABLE bitfield into a packed word x and return the packed field.

SECUR_CFG_OTP_READ_LOCK

Disable read access to OTP.

XS1_SECUR_CFG_OTP_READ_LOCK_SHIFT 0x9

XS1_SECUR_CFG_OTP_READ_LOCK_SIZE 0x1

XS1_SECUR_CFG_OTP_READ_LOCK_MASK (((1 << XS1_SECUR_CFG_OTP_READ_LOCK_SIZE) - 1) << XS1_SECUR_CFG_OTP_READ_LOCK_SHIFT)

XS1_SECUR_CFG_OTP_READ_LOCK(x) (((x) & XS1_SECUR_CFG_OTP_READ_LOCK_MASK) >> XS1_SECUR_CFG_OTP_READ_LOCK_SHIFT)

Extract the SECUR_CFG_OTP_READ_LOCK bitfield from a packed word x and return it.

XS1_SECUR_CFG_OTP_READ_LOCK_SET(x, v) (((x) & ~XS1_SECUR_CFG_OTP_READ_LOCK_MASK) | (((v) << XS1_SECUR_CFG_OTP_READ_LOCK_SHIFT) & XS1_SECUR_CFG_OTP_READ_LOCK_MASK))

Pack the value (v) of the SECUR_CFG_OTP_READ_LOCK bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_GLOBAL_DEBUG

Disable access to XCore’s global debug

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SHIFT 0xe

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SIZE 0x1

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_MASK (((1 << XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SIZE) - 1) << XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SHIFT)

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG(x) (((x) & XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_MASK) >> XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SHIFT)

Extract the SECUR_CFG_DISABLE_GLOBAL_DEBUG bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SET(x, v) (((x) & ~XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_MASK) | (((v) << XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_SHIFT) & XS1_SECUR_CFG_DISABLE_GLOBAL_DEBUG_MASK))

Pack the value (v) of the SECUR_CFG_DISABLE_GLOBAL_DEBUG bitfield into a packed word x and return the packed field.

SECUR_CFG_DISABLE_ACCESS

Disables write permission on this register

XS1_SECUR_CFG_DISABLE_ACCESS_SHIFT 0x1f

XS1_SECUR_CFG_DISABLE_ACCESS_SIZE 0x1

XS1_SECUR_CFG_DISABLE_ACCESS_MASK (((1 << XS1_SECUR_CFG_DISABLE_ACCESS_SIZE) - 1) << XS1_SECUR_CFG_DISABLE_ACCESS_SHIFT)

XS1_SECUR_CFG_DISABLE_ACCESS(x) (((x) & XS1_SECUR_CFG_DISABLE_ACCESS_MASK) >> XS1_SECUR_CFG_DISABLE_ACCESS_SHIFT)

Extract the SECUR_CFG_DISABLE_ACCESS bitfield from a packed word x and return it.

XS1_SECUR_CFG_DISABLE_ACCESS_SET(x, v) (((x) & ~XS1_SECUR_CFG_DISABLE_ACCESS_MASK) | (((v) << XS1_SECUR_CFG_DISABLE_ACCESS_SHIFT) & XS1_SECUR_CFG_DISABLE_ACCESS_MASK))

Pack the value (v) of the SECUR_CFG_DISABLE_ACCESS bitfield into a packed word x and return the packed field.

BOOT_STATUS_LEDS

Boot status LED value.

XS1_BOOT_STATUS_LEDS_SHIFT 0x0

XS1_BOOT_STATUS_LEDS_SIZE 0x4

XS1_BOOT_STATUS_LEDS_MASK (((1 << XS1_BOOT_STATUS_LEDS_SIZE) - 1) << XS1_BOOT_STATUS_LEDS_SHIFT)

XS1_BOOT_STATUS_LEDS(x) (((x) & XS1_BOOT_STATUS_LEDS_MASK) >> XS1_BOOT_STATUS_LEDS_SHIFT)

Extract the BOOT_STATUS_LEDS bitfield from a packed word x and return it.

XS1_BOOT_STATUS_LEDS_SET(x, v) (((x) & ~XS1_BOOT_STATUS_LEDS_MASK) | (((v) << XS1_BOOT_STATUS_LEDS_SHIFT) & XS1_BOOT_STATUS_LEDS_MASK))

Pack the value (v) of the BOOT_STATUS_LEDS bitfield into a packed word x and return the packed field.

BOOT_STATUS_BITS

Other boot status LED bits.

XS1_BOOT_STATUS_BITS_SHIFT 0x4

XS1_BOOT_STATUS_BITS_SIZE 0x1c

XS1_BOOT_STATUS_BITS_MASK (((1 << XS1_BOOT_STATUS_BITS_SIZE) - 1) << XS1_BOOT_STATUS_BITS_SHIFT)

XS1_BOOT_STATUS_BITS(x) (((x) & XS1_BOOT_STATUS_BITS_MASK) >> XS1_BOOT_STATUS_BITS_SHIFT)

Extract the BOOT_STATUS_BITS bitfield from a packed word x and return it.

XS1_BOOT_STATUS_BITS_SET(x, v) (((x) & ~XS1_BOOT_STATUS_BITS_MASK) | (((v) << XS1_BOOT_STATUS_BITS_SHIFT) & XS1_BOOT_STATUS_BITS_MASK))

Pack the value (v) of the BOOT_STATUS_BITS bitfield into a packed word x and return the packed field.

RING_OSC_PERPH_ENABLE

Set to 1 to enable the core peripheral ring oscillator.

XS1_RING_OSC_PERPH_ENABLE_SHIFT 0x0

XS1_RING_OSC_PERPH_ENABLE_SIZE 0x1

XS1_RING_OSC_PERPH_ENABLE_MASK (((1 << XS1_RING_OSC_PERPH_ENABLE_SIZE) - 1) << XS1_RING_OSC_PERPH_ENABLE_SHIFT)

XS1_RING_OSC_PERPH_ENABLE(x) (((x) & XS1_RING_OSC_PERPH_ENABLE_MASK) >> XS1_RING_OSC_PERPH_ENABLE_SHIFT)

Extract the RING_OSC_PERPH_ENABLE bitfield from a packed word x and return it.

XS1_RING_OSC_PERPH_ENABLE_SET(x, v) (((x) & ~XS1_RING_OSC_PERPH_ENABLE_MASK) | (((v) << XS1_RING_OSC_PERPH_ENABLE_SHIFT) & XS1_RING_OSC_PERPH_ENABLE_MASK))

Pack the value (v) of the RING_OSC_PERPH_ENABLE bitfield into a packed word x and return the packed field.

RING_OSC_CORE_ENABLE

Core ring oscillator enable.

XS1_RING_OSC_CORE_ENABLE_SHIFT 0x1

XS1_RING_OSC_CORE_ENABLE_SIZE 0x1

XS1_RING_OSC_CORE_ENABLE_MASK (((1 << XS1_RING_OSC_CORE_ENABLE_SIZE) - 1) << XS1_RING_OSC_CORE_ENABLE_SHIFT)

XS1_RING_OSC_CORE_ENABLE(x) (((x) & XS1_RING_OSC_CORE_ENABLE_MASK) >> XS1_RING_OSC_CORE_ENABLE_SHIFT)

Extract the RING_OSC_CORE_ENABLE bitfield from a packed word x and return it.

XS1_RING_OSC_CORE_ENABLE_SET(x, v) (((x) & ~XS1_RING_OSC_CORE_ENABLE_MASK) | (((v) << XS1_RING_OSC_CORE_ENABLE_SHIFT) & XS1_RING_OSC_CORE_ENABLE_MASK))

Pack the value (v) of the RING_OSC_CORE_ENABLE bitfield into a packed word x and return the packed field.

RING_OSC_DATA

Ring oscillator Counter data.

XS1_RING_OSC_DATA_SHIFT 0x0

XS1_RING_OSC_DATA_SIZE 0x10

XS1_RING_OSC_DATA_MASK (((1 << XS1_RING_OSC_DATA_SIZE) - 1) << XS1_RING_OSC_DATA_SHIFT)

XS1_RING_OSC_DATA(x) (((x) & XS1_RING_OSC_DATA_MASK) >> XS1_RING_OSC_DATA_SHIFT)

Extract the RING_OSC_DATA bitfield from a packed word x and return it.

XS1_RING_OSC_DATA_SET(x, v) (((x) & ~XS1_RING_OSC_DATA_MASK) | (((v) << XS1_RING_OSC_DATA_SHIFT) & XS1_RING_OSC_DATA_MASK))

Pack the value (v) of the RING_OSC_DATA bitfield into a packed word x and return the packed field.

PLL_CLK_DIVIDER

Clock divider.

XS1_PLL_CLK_DIVIDER_SHIFT 0x0

XS1_PLL_CLK_DIVIDER_SIZE 0x10

XS1_PLL_CLK_DIVIDER_MASK (((1 << XS1_PLL_CLK_DIVIDER_SIZE) - 1) << XS1_PLL_CLK_DIVIDER_SHIFT)

XS1_PLL_CLK_DIVIDER(x) (((x) & XS1_PLL_CLK_DIVIDER_MASK) >> XS1_PLL_CLK_DIVIDER_SHIFT)

Extract the PLL_CLK_DIVIDER bitfield from a packed word x and return it.

XS1_PLL_CLK_DIVIDER_SET(x, v) (((x) & ~XS1_PLL_CLK_DIVIDER_MASK) | (((v) << XS1_PLL_CLK_DIVIDER_SHIFT) & XS1_PLL_CLK_DIVIDER_MASK))

Pack the value (v) of the PLL_CLK_DIVIDER bitfield into a packed word x and return the packed field.

PLL_CLK_DISABLE

Clock disable. Writing ‘1’ will remove the clock to the tile.

XS1_PLL_CLK_DISABLE_SHIFT 0x1f

XS1_PLL_CLK_DISABLE_SIZE 0x1

XS1_PLL_CLK_DISABLE_MASK (((1 << XS1_PLL_CLK_DISABLE_SIZE) - 1) << XS1_PLL_CLK_DISABLE_SHIFT)

XS1_PLL_CLK_DISABLE(x) (((x) & XS1_PLL_CLK_DISABLE_MASK) >> XS1_PLL_CLK_DISABLE_SHIFT)

Extract the PLL_CLK_DISABLE bitfield from a packed word x and return it.

XS1_PLL_CLK_DISABLE_SET(x, v) (((x) & ~XS1_PLL_CLK_DISABLE_MASK) | (((v) << XS1_PLL_CLK_DISABLE_SHIFT) & XS1_PLL_CLK_DISABLE_MASK))

Pack the value (v) of the PLL_CLK_DISABLE bitfield into a packed word x and return the packed field.

RTSEL

ROM debug timing adjust.

XS1_RTSEL_SHIFT 0x0

XS1_RTSEL_SIZE 0x2

XS1_RTSEL_MASK (((1 << XS1_RTSEL_SIZE) - 1) << XS1_RTSEL_SHIFT)

XS1_RTSEL(x) (((x) & XS1_RTSEL_MASK) >> XS1_RTSEL_SHIFT)

Extract the RTSEL bitfield from a packed word x and return it.

XS1_RTSEL_SET(x, v) (((x) & ~XS1_RTSEL_MASK) | (((v) << XS1_RTSEL_SHIFT) & XS1_RTSEL_MASK))

Pack the value (v) of the RTSEL bitfield into a packed word x and return the packed field.

PTSEL

ROM debug timing adjust.

XS1_PTSEL_SHIFT 0x2

XS1_PTSEL_SIZE 0x2

XS1_PTSEL_MASK (((1 << XS1_PTSEL_SIZE) - 1) << XS1_PTSEL_SHIFT)

XS1_PTSEL(x) (((x) & XS1_PTSEL_MASK) >> XS1_PTSEL_SHIFT)

Extract the PTSEL bitfield from a packed word x and return it.

XS1_PTSEL_SET(x, v) (((x) & ~XS1_PTSEL_MASK) | (((v) << XS1_PTSEL_SHIFT) & XS1_PTSEL_MASK))

Pack the value (v) of the PTSEL bitfield into a packed word x and return the packed field.

TRB

ROM debug timing adjust.

XS1_TRB_SHIFT 0x4

XS1_TRB_SIZE 0x2

XS1_TRB_MASK (((1 << XS1_TRB_SIZE) - 1) << XS1_TRB_SHIFT)

XS1_TRB(x) (((x) & XS1_TRB_MASK) >> XS1_TRB_SHIFT)

Extract the TRB bitfield from a packed word x and return it.

XS1_TRB_SET(x, v) (((x) & ~XS1_TRB_MASK) | (((v) << XS1_TRB_SHIFT) & XS1_TRB_MASK))

Pack the value (v) of the TRB bitfield into a packed word x and return the packed field.

RAM_MASK

Blocks of 64k rams unavailable

XS1_RAM_MASK_SHIFT 0x0

XS1_RAM_MASK_SIZE 0x2

XS1_RAM_MASK_MASK (((1 << XS1_RAM_MASK_SIZE) - 1) << XS1_RAM_MASK_SHIFT)

XS1_RAM_MASK(x) (((x) & XS1_RAM_MASK_MASK) >> XS1_RAM_MASK_SHIFT)

Extract the RAM_MASK bitfield from a packed word x and return it.

XS1_RAM_MASK_SET(x, v) (((x) & ~XS1_RAM_MASK_MASK) | (((v) << XS1_RAM_MASK_SHIFT) & XS1_RAM_MASK_MASK))

Pack the value (v) of the RAM_MASK bitfield into a packed word x and return the packed field.

CORE1_DISABLE

Core 1’s clock is gated off

XS1_CORE1_DISABLE_SHIFT 0x8

XS1_CORE1_DISABLE_SIZE 0x1

XS1_CORE1_DISABLE_MASK (((1 << XS1_CORE1_DISABLE_SIZE) - 1) << XS1_CORE1_DISABLE_SHIFT)

XS1_CORE1_DISABLE(x) (((x) & XS1_CORE1_DISABLE_MASK) >> XS1_CORE1_DISABLE_SHIFT)

Extract the CORE1_DISABLE bitfield from a packed word x and return it.

XS1_CORE1_DISABLE_SET(x, v) (((x) & ~XS1_CORE1_DISABLE_MASK) | (((v) << XS1_CORE1_DISABLE_SHIFT) & XS1_CORE1_DISABLE_MASK))

Pack the value (v) of the CORE1_DISABLE bitfield into a packed word x and return the packed field.

THREAD_MASK

Threads unavailable

XS1_THREAD_MASK_SHIFT 0x9

XS1_THREAD_MASK_SIZE 0x7

XS1_THREAD_MASK_MASK (((1 << XS1_THREAD_MASK_SIZE) - 1) << XS1_THREAD_MASK_SHIFT)

XS1_THREAD_MASK(x) (((x) & XS1_THREAD_MASK_MASK) >> XS1_THREAD_MASK_SHIFT)

Extract the THREAD_MASK bitfield from a packed word x and return it.

XS1_THREAD_MASK_SET(x, v) (((x) & ~XS1_THREAD_MASK_MASK) | (((v) << XS1_THREAD_MASK_SHIFT) & XS1_THREAD_MASK_MASK))

Pack the value (v) of the THREAD_MASK bitfield into a packed word x and return the packed field.

THREAD_CTRL0_INUSE

Returns 1 when the thread is in use, 0 otherwise.

XS1_THREAD_CTRL0_INUSE_SHIFT 0x0

XS1_THREAD_CTRL0_INUSE_SIZE 0x1

XS1_THREAD_CTRL0_INUSE_MASK (((1 << XS1_THREAD_CTRL0_INUSE_SIZE) - 1) << XS1_THREAD_CTRL0_INUSE_SHIFT)

XS1_THREAD_CTRL0_INUSE(x) (((x) & XS1_THREAD_CTRL0_INUSE_MASK) >> XS1_THREAD_CTRL0_INUSE_SHIFT)

Extract the THREAD_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_THREAD_CTRL0_INUSE_MASK) | (((v) << XS1_THREAD_CTRL0_INUSE_SHIFT) & XS1_THREAD_CTRL0_INUSE_MASK))

Pack the value (v) of the THREAD_CTRL0_INUSE bitfield into a packed word x and return the packed field.

THREAD_CTRL0_MSYNC

1 when the thread is msyncing, 0 otherwise.

XS1_THREAD_CTRL0_MSYNC_SHIFT 0x1

XS1_THREAD_CTRL0_MSYNC_SIZE 0x1

XS1_THREAD_CTRL0_MSYNC_MASK (((1 << XS1_THREAD_CTRL0_MSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_MSYNC_SHIFT)

XS1_THREAD_CTRL0_MSYNC(x) (((x) & XS1_THREAD_CTRL0_MSYNC_MASK) >> XS1_THREAD_CTRL0_MSYNC_SHIFT)

Extract the THREAD_CTRL0_MSYNC bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_MSYNC_SET(x, v) (((x) & ~XS1_THREAD_CTRL0_MSYNC_MASK) | (((v) << XS1_THREAD_CTRL0_MSYNC_SHIFT) & XS1_THREAD_CTRL0_MSYNC_MASK))

Pack the value (v) of the THREAD_CTRL0_MSYNC bitfield into a packed word x and return the packed field.

THREAD_CTRL0_SSYNC

1 when the thread is ssyncing, 0 otherwise.

XS1_THREAD_CTRL0_SSYNC_SHIFT 0x2

XS1_THREAD_CTRL0_SSYNC_SIZE 0x1

XS1_THREAD_CTRL0_SSYNC_MASK (((1 << XS1_THREAD_CTRL0_SSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_SSYNC_SHIFT)

XS1_THREAD_CTRL0_SSYNC(x) (((x) & XS1_THREAD_CTRL0_SSYNC_MASK) >> XS1_THREAD_CTRL0_SSYNC_SHIFT)

Extract the THREAD_CTRL0_SSYNC bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_SSYNC_SET(x, v) (((x) & ~XS1_THREAD_CTRL0_SSYNC_MASK) | (((v) << XS1_THREAD_CTRL0_SSYNC_SHIFT) & XS1_THREAD_CTRL0_SSYNC_MASK))

Pack the value (v) of the THREAD_CTRL0_SSYNC bitfield into a packed word x and return the packed field.

THREAD_CTRL0_MASTER

Returns the ID of this thread’s master.

XS1_THREAD_CTRL0_MASTER_SHIFT 0x8

XS1_THREAD_CTRL0_MASTER_SIZE 0x8

XS1_THREAD_CTRL0_MASTER_MASK (((1 << XS1_THREAD_CTRL0_MASTER_SIZE) - 1) << XS1_THREAD_CTRL0_MASTER_SHIFT)

XS1_THREAD_CTRL0_MASTER(x) (((x) & XS1_THREAD_CTRL0_MASTER_MASK) >> XS1_THREAD_CTRL0_MASTER_SHIFT)

Extract the THREAD_CTRL0_MASTER bitfield from a packed word x and return it.

XS1_THREAD_CTRL0_MASTER_SET(x, v) (((x) & ~XS1_THREAD_CTRL0_MASTER_MASK) | (((v) << XS1_THREAD_CTRL0_MASTER_SHIFT) & XS1_THREAD_CTRL0_MASTER_MASK))

Pack the value (v) of the THREAD_CTRL0_MASTER bitfield into a packed word x and return the packed field.

PORT_CTRL0_INUSE

Returns 1 when the port is in use, 0 otherwise.

XS1_PORT_CTRL0_INUSE_SHIFT 0x0

XS1_PORT_CTRL0_INUSE_SIZE 0x1

XS1_PORT_CTRL0_INUSE_MASK (((1 << XS1_PORT_CTRL0_INUSE_SIZE) - 1) << XS1_PORT_CTRL0_INUSE_SHIFT)

XS1_PORT_CTRL0_INUSE(x) (((x) & XS1_PORT_CTRL0_INUSE_MASK) >> XS1_PORT_CTRL0_INUSE_SHIFT)

Extract the PORT_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_PORT_CTRL0_INUSE_MASK) | (((v) << XS1_PORT_CTRL0_INUSE_SHIFT) & XS1_PORT_CTRL0_INUSE_MASK))

Pack the value (v) of the PORT_CTRL0_INUSE bitfield into a packed word x and return the packed field.

PORT_CTRL0_IE_MODE

0 when this port will cause events, 1 when it will raise interrupts. It is controlled using the SETC instruction.

XS1_PORT_CTRL0_IE_MODE_SHIFT 0x1

XS1_PORT_CTRL0_IE_MODE_SIZE 0x1

XS1_PORT_CTRL0_IE_MODE_MASK (((1 << XS1_PORT_CTRL0_IE_MODE_SIZE) - 1) << XS1_PORT_CTRL0_IE_MODE_SHIFT)

XS1_PORT_CTRL0_IE_MODE(x) (((x) & XS1_PORT_CTRL0_IE_MODE_MASK) >> XS1_PORT_CTRL0_IE_MODE_SHIFT)

Extract the PORT_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_IE_MODE_SET(x, v) (((x) & ~XS1_PORT_CTRL0_IE_MODE_MASK) | (((v) << XS1_PORT_CTRL0_IE_MODE_SHIFT) & XS1_PORT_CTRL0_IE_MODE_MASK))

Pack the value (v) of the PORT_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

PORT_CTRL0_IE_ENABLED

1 when events or interrupts on this port are active. It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_PORT_CTRL0_IE_ENABLED_SHIFT 0x2

XS1_PORT_CTRL0_IE_ENABLED_SIZE 0x1

XS1_PORT_CTRL0_IE_ENABLED_MASK (((1 << XS1_PORT_CTRL0_IE_ENABLED_SIZE) - 1) << XS1_PORT_CTRL0_IE_ENABLED_SHIFT)

XS1_PORT_CTRL0_IE_ENABLED(x) (((x) & XS1_PORT_CTRL0_IE_ENABLED_MASK) >> XS1_PORT_CTRL0_IE_ENABLED_SHIFT)

Extract the PORT_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_PORT_CTRL0_IE_ENABLED_SET(x, v) (((x) & ~XS1_PORT_CTRL0_IE_ENABLED_MASK) | (((v) << XS1_PORT_CTRL0_IE_ENABLED_SHIFT) & XS1_PORT_CTRL0_IE_ENABLED_MASK))

Pack the value (v) of the PORT_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

PORT_CTRL0_DIRECTION

0 when it is in input mode, 1 when this port is in output mode.

XS1_PORT_CTRL0_DIRECTION_SHIFT 0x3

XS1_PORT_CTRL0_DIRECTION_SIZE 0x1

XS1_PORT_CTRL0_DIRECTION_MASK (((1 << XS1_PORT_CTRL0_DIRECTION_SIZE) - 1) << XS1_PORT_CTRL0_DIRECTION_SHIFT)

XS1_PORT_CTRL0_DIRECTION(x) (((x) & XS1_PORT_CTRL0_DIRECTION_MASK) >> XS1_PORT_CTRL0_DIRECTION_SHIFT)

Extract the PORT_CTRL0_DIRECTION bitfield from a packed word x and return it.

XS1_PORT_CTRL0_DIRECTION_SET(x, v) (((x) & ~XS1_PORT_CTRL0_DIRECTION_MASK) | (((v) << XS1_PORT_CTRL0_DIRECTION_SHIFT) & XS1_PORT_CTRL0_DIRECTION_MASK))

Pack the value (v) of the PORT_CTRL0_DIRECTION bitfield into a packed word x and return the packed field.

PORT_CTRL0_COND

Shows the current condition of the port. The condition is set using the SETC instruction.

XS1_PORT_CTRL0_COND_SHIFT 0x4

XS1_PORT_CTRL0_COND_SIZE 0x4

XS1_PORT_CTRL0_COND_MASK (((1 << XS1_PORT_CTRL0_COND_SIZE) - 1) << XS1_PORT_CTRL0_COND_SHIFT)

XS1_PORT_CTRL0_COND(x) (((x) & XS1_PORT_CTRL0_COND_MASK) >> XS1_PORT_CTRL0_COND_SHIFT)

Extract the PORT_CTRL0_COND bitfield from a packed word x and return it.

XS1_PORT_CTRL0_COND_SET(x, v) (((x) & ~XS1_PORT_CTRL0_COND_MASK) | (((v) << XS1_PORT_CTRL0_COND_SHIFT) & XS1_PORT_CTRL0_COND_MASK))

Pack the value (v) of the PORT_CTRL0_COND bitfield into a packed word x and return the packed field.

PORT_CTRL0_MASTER_SLAVE

0 when the port is a master, 1 when it is a slave.

XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT 0x8

XS1_PORT_CTRL0_MASTER_SLAVE_SIZE 0x1

XS1_PORT_CTRL0_MASTER_SLAVE_MASK (((1 << XS1_PORT_CTRL0_MASTER_SLAVE_SIZE) - 1) << XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)

XS1_PORT_CTRL0_MASTER_SLAVE(x) (((x) & XS1_PORT_CTRL0_MASTER_SLAVE_MASK) >> XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)

Extract the PORT_CTRL0_MASTER_SLAVE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_MASTER_SLAVE_SET(x, v) (((x) & ~XS1_PORT_CTRL0_MASTER_SLAVE_MASK) | (((v) << XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT) & XS1_PORT_CTRL0_MASTER_SLAVE_MASK))

Pack the value (v) of the PORT_CTRL0_MASTER_SLAVE bitfield into a packed word x and return the packed field.

PORT_CTRL0_BUFFERS

When 0 there is no buffering between the port and pins. When 1 there is buffering between the port and instructions.

XS1_PORT_CTRL0_BUFFERS_SHIFT 0x9

XS1_PORT_CTRL0_BUFFERS_SIZE 0x1

XS1_PORT_CTRL0_BUFFERS_MASK (((1 << XS1_PORT_CTRL0_BUFFERS_SIZE) - 1) << XS1_PORT_CTRL0_BUFFERS_SHIFT)

XS1_PORT_CTRL0_BUFFERS(x) (((x) & XS1_PORT_CTRL0_BUFFERS_MASK) >> XS1_PORT_CTRL0_BUFFERS_SHIFT)

Extract the PORT_CTRL0_BUFFERS bitfield from a packed word x and return it.

XS1_PORT_CTRL0_BUFFERS_SET(x, v) (((x) & ~XS1_PORT_CTRL0_BUFFERS_MASK) | (((v) << XS1_PORT_CTRL0_BUFFERS_SHIFT) & XS1_PORT_CTRL0_BUFFERS_MASK))

Pack the value (v) of the PORT_CTRL0_BUFFERS bitfield into a packed word x and return the packed field.

PORT_CTRL0_READY_MODE

0 - no ready signals used, 1 - strobed port, 2 - handshaken port

XS1_PORT_CTRL0_READY_MODE_SHIFT 0xa

XS1_PORT_CTRL0_READY_MODE_SIZE 0x2

XS1_PORT_CTRL0_READY_MODE_MASK (((1 << XS1_PORT_CTRL0_READY_MODE_SIZE) - 1) << XS1_PORT_CTRL0_READY_MODE_SHIFT)

XS1_PORT_CTRL0_READY_MODE(x) (((x) & XS1_PORT_CTRL0_READY_MODE_MASK) >> XS1_PORT_CTRL0_READY_MODE_SHIFT)

Extract the PORT_CTRL0_READY_MODE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_READY_MODE_SET(x, v) (((x) & ~XS1_PORT_CTRL0_READY_MODE_MASK) | (((v) << XS1_PORT_CTRL0_READY_MODE_SHIFT) & XS1_PORT_CTRL0_READY_MODE_MASK))

Pack the value (v) of the PORT_CTRL0_READY_MODE bitfield into a packed word x and return the packed field.

PORT_CTRL0_PORT_TYPE

0 - data port, 1 - clock port (1-bit ports only), 2 - ready port (1-bit ports only)

XS1_PORT_CTRL0_PORT_TYPE_SHIFT 0xc

XS1_PORT_CTRL0_PORT_TYPE_SIZE 0x2

XS1_PORT_CTRL0_PORT_TYPE_MASK (((1 << XS1_PORT_CTRL0_PORT_TYPE_SIZE) - 1) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT)

XS1_PORT_CTRL0_PORT_TYPE(x) (((x) & XS1_PORT_CTRL0_PORT_TYPE_MASK) >> XS1_PORT_CTRL0_PORT_TYPE_SHIFT)

Extract the PORT_CTRL0_PORT_TYPE bitfield from a packed word x and return it.

XS1_PORT_CTRL0_PORT_TYPE_SET(x, v) (((x) & ~XS1_PORT_CTRL0_PORT_TYPE_MASK) | (((v) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT) & XS1_PORT_CTRL0_PORT_TYPE_MASK))

Pack the value (v) of the PORT_CTRL0_PORT_TYPE bitfield into a packed word x and return the packed field.

PORT_CTRL0_INVERT

When 1 the port is inverted, otherwise it is not inverted. Only possible on 1-bit ports.

XS1_PORT_CTRL0_INVERT_SHIFT 0xe

XS1_PORT_CTRL0_INVERT_SIZE 0x1

XS1_PORT_CTRL0_INVERT_MASK (((1 << XS1_PORT_CTRL0_INVERT_SIZE) - 1) << XS1_PORT_CTRL0_INVERT_SHIFT)

XS1_PORT_CTRL0_INVERT(x) (((x) & XS1_PORT_CTRL0_INVERT_MASK) >> XS1_PORT_CTRL0_INVERT_SHIFT)

Extract the PORT_CTRL0_INVERT bitfield from a packed word x and return it.

XS1_PORT_CTRL0_INVERT_SET(x, v) (((x) & ~XS1_PORT_CTRL0_INVERT_MASK) | (((v) << XS1_PORT_CTRL0_INVERT_SHIFT) & XS1_PORT_CTRL0_INVERT_MASK))

Pack the value (v) of the PORT_CTRL0_INVERT bitfield into a packed word x and return the packed field.

PORT_CTRL0_SDELAY

0 when the input uses the rising edge, 1 when it uses the falling edge of the clock.

XS1_PORT_CTRL0_SDELAY_SHIFT 0xf

XS1_PORT_CTRL0_SDELAY_SIZE 0x1

XS1_PORT_CTRL0_SDELAY_MASK (((1 << XS1_PORT_CTRL0_SDELAY_SIZE) - 1) << XS1_PORT_CTRL0_SDELAY_SHIFT)

XS1_PORT_CTRL0_SDELAY(x) (((x) & XS1_PORT_CTRL0_SDELAY_MASK) >> XS1_PORT_CTRL0_SDELAY_SHIFT)

Extract the PORT_CTRL0_SDELAY bitfield from a packed word x and return it.

XS1_PORT_CTRL0_SDELAY_SET(x, v) (((x) & ~XS1_PORT_CTRL0_SDELAY_MASK) | (((v) << XS1_PORT_CTRL0_SDELAY_SHIFT) & XS1_PORT_CTRL0_SDELAY_MASK))

Pack the value (v) of the PORT_CTRL0_SDELAY bitfield into a packed word x and return the packed field.

PORT_CTRL0_EV_VALID

1 when the Environment Vector is valid. When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_PORT_CTRL0_EV_VALID_SHIFT 0x16

XS1_PORT_CTRL0_EV_VALID_SIZE 0x1

XS1_PORT_CTRL0_EV_VALID_MASK (((1 << XS1_PORT_CTRL0_EV_VALID_SIZE) - 1) << XS1_PORT_CTRL0_EV_VALID_SHIFT)

XS1_PORT_CTRL0_EV_VALID(x) (((x) & XS1_PORT_CTRL0_EV_VALID_MASK) >> XS1_PORT_CTRL0_EV_VALID_SHIFT)

Extract the PORT_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_PORT_CTRL0_EV_VALID_SET(x, v) (((x) & ~XS1_PORT_CTRL0_EV_VALID_MASK) | (((v) << XS1_PORT_CTRL0_EV_VALID_SHIFT) & XS1_PORT_CTRL0_EV_VALID_MASK))

Pack the value (v) of the PORT_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

PORT_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this port.

XS1_PORT_CTRL0_T_WAITING_SHIFT 0x17

XS1_PORT_CTRL0_T_WAITING_SIZE 0x1

XS1_PORT_CTRL0_T_WAITING_MASK (((1 << XS1_PORT_CTRL0_T_WAITING_SIZE) - 1) << XS1_PORT_CTRL0_T_WAITING_SHIFT)

XS1_PORT_CTRL0_T_WAITING(x) (((x) & XS1_PORT_CTRL0_T_WAITING_MASK) >> XS1_PORT_CTRL0_T_WAITING_SHIFT)

Extract the PORT_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_PORT_CTRL0_T_WAITING_SET(x, v) (((x) & ~XS1_PORT_CTRL0_T_WAITING_MASK) | (((v) << XS1_PORT_CTRL0_T_WAITING_SHIFT) & XS1_PORT_CTRL0_T_WAITING_MASK))

Pack the value (v) of the PORT_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

PORT_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this port.

XS1_PORT_CTRL0_T_NUM_SHIFT 0x18

XS1_PORT_CTRL0_T_NUM_SIZE 0x8

XS1_PORT_CTRL0_T_NUM_MASK (((1 << XS1_PORT_CTRL0_T_NUM_SIZE) - 1) << XS1_PORT_CTRL0_T_NUM_SHIFT)

XS1_PORT_CTRL0_T_NUM(x) (((x) & XS1_PORT_CTRL0_T_NUM_MASK) >> XS1_PORT_CTRL0_T_NUM_SHIFT)

Extract the PORT_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_PORT_CTRL0_T_NUM_SET(x, v) (((x) & ~XS1_PORT_CTRL0_T_NUM_MASK) | (((v) << XS1_PORT_CTRL0_T_NUM_SHIFT) & XS1_PORT_CTRL0_T_NUM_MASK))

Pack the value (v) of the PORT_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

PORT_CTRL1_DRIVE

Determines whether the output is driving, open drain or pull down.

XS1_PORT_CTRL1_DRIVE_SHIFT 0x0

XS1_PORT_CTRL1_DRIVE_SIZE 0x8

XS1_PORT_CTRL1_DRIVE_MASK (((1 << XS1_PORT_CTRL1_DRIVE_SIZE) - 1) << XS1_PORT_CTRL1_DRIVE_SHIFT)

XS1_PORT_CTRL1_DRIVE(x) (((x) & XS1_PORT_CTRL1_DRIVE_MASK) >> XS1_PORT_CTRL1_DRIVE_SHIFT)

Extract the PORT_CTRL1_DRIVE bitfield from a packed word x and return it.

XS1_PORT_CTRL1_DRIVE_SET(x, v) (((x) & ~XS1_PORT_CTRL1_DRIVE_MASK) | (((v) << XS1_PORT_CTRL1_DRIVE_SHIFT) & XS1_PORT_CTRL1_DRIVE_MASK))

Pack the value (v) of the PORT_CTRL1_DRIVE bitfield into a packed word x and return the packed field.

PORT_CTRL1_TWIDTH

The transfer width of the port in bits

XS1_PORT_CTRL1_TWIDTH_SHIFT 0x8

XS1_PORT_CTRL1_TWIDTH_SIZE 0x8

XS1_PORT_CTRL1_TWIDTH_MASK (((1 << XS1_PORT_CTRL1_TWIDTH_SIZE) - 1) << XS1_PORT_CTRL1_TWIDTH_SHIFT)

XS1_PORT_CTRL1_TWIDTH(x) (((x) & XS1_PORT_CTRL1_TWIDTH_MASK) >> XS1_PORT_CTRL1_TWIDTH_SHIFT)

Extract the PORT_CTRL1_TWIDTH bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TWIDTH_SET(x, v) (((x) & ~XS1_PORT_CTRL1_TWIDTH_MASK) | (((v) << XS1_PORT_CTRL1_TWIDTH_SHIFT) & XS1_PORT_CTRL1_TWIDTH_MASK))

Pack the value (v) of the PORT_CTRL1_TWIDTH bitfield into a packed word x and return the packed field.

PORT_CTRL1_SREG_COUNT

The shift register count in port widths.

XS1_PORT_CTRL1_SREG_COUNT_SHIFT 0x10

XS1_PORT_CTRL1_SREG_COUNT_SIZE 0x8

XS1_PORT_CTRL1_SREG_COUNT_MASK (((1 << XS1_PORT_CTRL1_SREG_COUNT_SIZE) - 1) << XS1_PORT_CTRL1_SREG_COUNT_SHIFT)

XS1_PORT_CTRL1_SREG_COUNT(x) (((x) & XS1_PORT_CTRL1_SREG_COUNT_MASK) >> XS1_PORT_CTRL1_SREG_COUNT_SHIFT)

Extract the PORT_CTRL1_SREG_COUNT bitfield from a packed word x and return it.

XS1_PORT_CTRL1_SREG_COUNT_SET(x, v) (((x) & ~XS1_PORT_CTRL1_SREG_COUNT_MASK) | (((v) << XS1_PORT_CTRL1_SREG_COUNT_SHIFT) & XS1_PORT_CTRL1_SREG_COUNT_MASK))

Pack the value (v) of the PORT_CTRL1_SREG_COUNT bitfield into a packed word x and return the packed field.

PORT_CTRL1_TREG_FULL

1 when the transfer register is full.

XS1_PORT_CTRL1_TREG_FULL_SHIFT 0x18

XS1_PORT_CTRL1_TREG_FULL_SIZE 0x1

XS1_PORT_CTRL1_TREG_FULL_MASK (((1 << XS1_PORT_CTRL1_TREG_FULL_SIZE) - 1) << XS1_PORT_CTRL1_TREG_FULL_SHIFT)

XS1_PORT_CTRL1_TREG_FULL(x) (((x) & XS1_PORT_CTRL1_TREG_FULL_MASK) >> XS1_PORT_CTRL1_TREG_FULL_SHIFT)

Extract the PORT_CTRL1_TREG_FULL bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TREG_FULL_SET(x, v) (((x) & ~XS1_PORT_CTRL1_TREG_FULL_MASK) | (((v) << XS1_PORT_CTRL1_TREG_FULL_SHIFT) & XS1_PORT_CTRL1_TREG_FULL_MASK))

Pack the value (v) of the PORT_CTRL1_TREG_FULL bitfield into a packed word x and return the packed field.

PORT_CTRL1_CHANGE_DIR

0 when the direction is fixed, 1 when it is going to change.

XS1_PORT_CTRL1_CHANGE_DIR_SHIFT 0x19

XS1_PORT_CTRL1_CHANGE_DIR_SIZE 0x1

XS1_PORT_CTRL1_CHANGE_DIR_MASK (((1 << XS1_PORT_CTRL1_CHANGE_DIR_SIZE) - 1) << XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)

XS1_PORT_CTRL1_CHANGE_DIR(x) (((x) & XS1_PORT_CTRL1_CHANGE_DIR_MASK) >> XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)

Extract the PORT_CTRL1_CHANGE_DIR bitfield from a packed word x and return it.

XS1_PORT_CTRL1_CHANGE_DIR_SET(x, v) (((x) & ~XS1_PORT_CTRL1_CHANGE_DIR_MASK) | (((v) << XS1_PORT_CTRL1_CHANGE_DIR_SHIFT) & XS1_PORT_CTRL1_CHANGE_DIR_MASK))

Pack the value (v) of the PORT_CTRL1_CHANGE_DIR bitfield into a packed word x and return the packed field.

PORT_CTRL1_SYNCR

1 when a SYNCR instruction is pending completion.

XS1_PORT_CTRL1_SYNCR_SHIFT 0x1a

XS1_PORT_CTRL1_SYNCR_SIZE 0x1

XS1_PORT_CTRL1_SYNCR_MASK (((1 << XS1_PORT_CTRL1_SYNCR_SIZE) - 1) << XS1_PORT_CTRL1_SYNCR_SHIFT)

XS1_PORT_CTRL1_SYNCR(x) (((x) & XS1_PORT_CTRL1_SYNCR_MASK) >> XS1_PORT_CTRL1_SYNCR_SHIFT)

Extract the PORT_CTRL1_SYNCR bitfield from a packed word x and return it.

XS1_PORT_CTRL1_SYNCR_SET(x, v) (((x) & ~XS1_PORT_CTRL1_SYNCR_MASK) | (((v) << XS1_PORT_CTRL1_SYNCR_SHIFT) & XS1_PORT_CTRL1_SYNCR_MASK))

Pack the value (v) of the PORT_CTRL1_SYNCR bitfield into a packed word x and return the packed field.

PORT_CTRL1_INST_COMMITTED

1 when an instruction has committed to operating on the port.

XS1_PORT_CTRL1_INST_COMMITTED_SHIFT 0x1b

XS1_PORT_CTRL1_INST_COMMITTED_SIZE 0x1

XS1_PORT_CTRL1_INST_COMMITTED_MASK (((1 << XS1_PORT_CTRL1_INST_COMMITTED_SIZE) - 1) << XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)

XS1_PORT_CTRL1_INST_COMMITTED(x) (((x) & XS1_PORT_CTRL1_INST_COMMITTED_MASK) >> XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)

Extract the PORT_CTRL1_INST_COMMITTED bitfield from a packed word x and return it.

XS1_PORT_CTRL1_INST_COMMITTED_SET(x, v) (((x) & ~XS1_PORT_CTRL1_INST_COMMITTED_MASK) | (((v) << XS1_PORT_CTRL1_INST_COMMITTED_SHIFT) & XS1_PORT_CTRL1_INST_COMMITTED_MASK))

Pack the value (v) of the PORT_CTRL1_INST_COMMITTED bitfield into a packed word x and return the packed field.

PORT_CTRL1_HOLD_DATA

1 data has been captured for a condition and is being held.

XS1_PORT_CTRL1_HOLD_DATA_SHIFT 0x1c

XS1_PORT_CTRL1_HOLD_DATA_SIZE 0x1

XS1_PORT_CTRL1_HOLD_DATA_MASK (((1 << XS1_PORT_CTRL1_HOLD_DATA_SIZE) - 1) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT)

XS1_PORT_CTRL1_HOLD_DATA(x) (((x) & XS1_PORT_CTRL1_HOLD_DATA_MASK) >> XS1_PORT_CTRL1_HOLD_DATA_SHIFT)

Extract the PORT_CTRL1_HOLD_DATA bitfield from a packed word x and return it.

XS1_PORT_CTRL1_HOLD_DATA_SET(x, v) (((x) & ~XS1_PORT_CTRL1_HOLD_DATA_MASK) | (((v) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT) & XS1_PORT_CTRL1_HOLD_DATA_MASK))

Pack the value (v) of the PORT_CTRL1_HOLD_DATA bitfield into a packed word x and return the packed field.

PORT_CTRL1_WAIT_FOR_TIME

1 when waiting for the port time to be met.

XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT 0x1d

XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE 0x1

XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK (((1 << XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE) - 1) << XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)

XS1_PORT_CTRL1_WAIT_FOR_TIME(x) (((x) & XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) >> XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)

Extract the PORT_CTRL1_WAIT_FOR_TIME bitfield from a packed word x and return it.

XS1_PORT_CTRL1_WAIT_FOR_TIME_SET(x, v) (((x) & ~XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) | (((v) << XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT) & XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK))

Pack the value (v) of the PORT_CTRL1_WAIT_FOR_TIME bitfield into a packed word x and return the packed field.

PORT_CTRL1_TIMEMET

1 when a SETPT is used.

XS1_PORT_CTRL1_TIMEMET_SHIFT 0x1e

XS1_PORT_CTRL1_TIMEMET_SIZE 0x1

XS1_PORT_CTRL1_TIMEMET_MASK (((1 << XS1_PORT_CTRL1_TIMEMET_SIZE) - 1) << XS1_PORT_CTRL1_TIMEMET_SHIFT)

XS1_PORT_CTRL1_TIMEMET(x) (((x) & XS1_PORT_CTRL1_TIMEMET_MASK) >> XS1_PORT_CTRL1_TIMEMET_SHIFT)

Extract the PORT_CTRL1_TIMEMET bitfield from a packed word x and return it.

XS1_PORT_CTRL1_TIMEMET_SET(x, v) (((x) & ~XS1_PORT_CTRL1_TIMEMET_MASK) | (((v) << XS1_PORT_CTRL1_TIMEMET_SHIFT) & XS1_PORT_CTRL1_TIMEMET_MASK))

Pack the value (v) of the PORT_CTRL1_TIMEMET bitfield into a packed word x and return the packed field.

PORT_CTRL1_ENDIN

1 when an ENDIN is used on a BUFFERS port and the tReg was full.

XS1_PORT_CTRL1_ENDIN_SHIFT 0x1f

XS1_PORT_CTRL1_ENDIN_SIZE 0x1

XS1_PORT_CTRL1_ENDIN_MASK (((1 << XS1_PORT_CTRL1_ENDIN_SIZE) - 1) << XS1_PORT_CTRL1_ENDIN_SHIFT)

XS1_PORT_CTRL1_ENDIN(x) (((x) & XS1_PORT_CTRL1_ENDIN_MASK) >> XS1_PORT_CTRL1_ENDIN_SHIFT)

Extract the PORT_CTRL1_ENDIN bitfield from a packed word x and return it.

XS1_PORT_CTRL1_ENDIN_SET(x, v) (((x) & ~XS1_PORT_CTRL1_ENDIN_MASK) | (((v) << XS1_PORT_CTRL1_ENDIN_SHIFT) & XS1_PORT_CTRL1_ENDIN_MASK))

Pack the value (v) of the PORT_CTRL1_ENDIN bitfield into a packed word x and return the packed field.

PORT_CTRL2_TIME

The port time value.

XS1_PORT_CTRL2_TIME_SHIFT 0x0

XS1_PORT_CTRL2_TIME_SIZE 0x10

XS1_PORT_CTRL2_TIME_MASK (((1 << XS1_PORT_CTRL2_TIME_SIZE) - 1) << XS1_PORT_CTRL2_TIME_SHIFT)

XS1_PORT_CTRL2_TIME(x) (((x) & XS1_PORT_CTRL2_TIME_MASK) >> XS1_PORT_CTRL2_TIME_SHIFT)

Extract the PORT_CTRL2_TIME bitfield from a packed word x and return it.

XS1_PORT_CTRL2_TIME_SET(x, v) (((x) & ~XS1_PORT_CTRL2_TIME_MASK) | (((v) << XS1_PORT_CTRL2_TIME_SHIFT) & XS1_PORT_CTRL2_TIME_MASK))

Pack the value (v) of the PORT_CTRL2_TIME bitfield into a packed word x and return the packed field.

PORT_CTRL2_PIN_DELAY

The port pin delay.

XS1_PORT_CTRL2_PIN_DELAY_SHIFT 0x10

XS1_PORT_CTRL2_PIN_DELAY_SIZE 0x3

XS1_PORT_CTRL2_PIN_DELAY_MASK (((1 << XS1_PORT_CTRL2_PIN_DELAY_SIZE) - 1) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT)

XS1_PORT_CTRL2_PIN_DELAY(x) (((x) & XS1_PORT_CTRL2_PIN_DELAY_MASK) >> XS1_PORT_CTRL2_PIN_DELAY_SHIFT)

Extract the PORT_CTRL2_PIN_DELAY bitfield from a packed word x and return it.

XS1_PORT_CTRL2_PIN_DELAY_SET(x, v) (((x) & ~XS1_PORT_CTRL2_PIN_DELAY_MASK) | (((v) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT) & XS1_PORT_CTRL2_PIN_DELAY_MASK))

Pack the value (v) of the PORT_CTRL2_PIN_DELAY bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_OEN

The pad control output enable.

XS1_PORT_PAD_CTRL_OEN_SHIFT 0x0

XS1_PORT_PAD_CTRL_OEN_SIZE 0x1

XS1_PORT_PAD_CTRL_OEN_MASK (((1 << XS1_PORT_PAD_CTRL_OEN_SIZE) - 1) << XS1_PORT_PAD_CTRL_OEN_SHIFT)

XS1_PORT_PAD_CTRL_OEN(x) (((x) & XS1_PORT_PAD_CTRL_OEN_MASK) >> XS1_PORT_PAD_CTRL_OEN_SHIFT)

Extract the PORT_PAD_CTRL_OEN bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_OEN_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_OEN_MASK) | (((v) << XS1_PORT_PAD_CTRL_OEN_SHIFT) & XS1_PORT_PAD_CTRL_OEN_MASK))

Pack the value (v) of the PORT_PAD_CTRL_OEN bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_REN

The pad control read enable.

XS1_PORT_PAD_CTRL_REN_SHIFT 0x1

XS1_PORT_PAD_CTRL_REN_SIZE 0x1

XS1_PORT_PAD_CTRL_REN_MASK (((1 << XS1_PORT_PAD_CTRL_REN_SIZE) - 1) << XS1_PORT_PAD_CTRL_REN_SHIFT)

XS1_PORT_PAD_CTRL_REN(x) (((x) & XS1_PORT_PAD_CTRL_REN_MASK) >> XS1_PORT_PAD_CTRL_REN_SHIFT)

Extract the PORT_PAD_CTRL_REN bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_REN_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_REN_MASK) | (((v) << XS1_PORT_PAD_CTRL_REN_SHIFT) & XS1_PORT_PAD_CTRL_REN_MASK))

Pack the value (v) of the PORT_PAD_CTRL_REN bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_P

The pad control pull.

XS1_PORT_PAD_CTRL_P_SHIFT 0x2

XS1_PORT_PAD_CTRL_P_SIZE 0x2

XS1_PORT_PAD_CTRL_P_MASK (((1 << XS1_PORT_PAD_CTRL_P_SIZE) - 1) << XS1_PORT_PAD_CTRL_P_SHIFT)

XS1_PORT_PAD_CTRL_P(x) (((x) & XS1_PORT_PAD_CTRL_P_MASK) >> XS1_PORT_PAD_CTRL_P_SHIFT)

Extract the PORT_PAD_CTRL_P bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_P_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_P_MASK) | (((v) << XS1_PORT_PAD_CTRL_P_SHIFT) & XS1_PORT_PAD_CTRL_P_MASK))

Pack the value (v) of the PORT_PAD_CTRL_P bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_E

The pad control drive strength.

XS1_PORT_PAD_CTRL_E_SHIFT 0x4

XS1_PORT_PAD_CTRL_E_SIZE 0x2

XS1_PORT_PAD_CTRL_E_MASK (((1 << XS1_PORT_PAD_CTRL_E_SIZE) - 1) << XS1_PORT_PAD_CTRL_E_SHIFT)

XS1_PORT_PAD_CTRL_E(x) (((x) & XS1_PORT_PAD_CTRL_E_MASK) >> XS1_PORT_PAD_CTRL_E_SHIFT)

Extract the PORT_PAD_CTRL_E bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_E_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_E_MASK) | (((v) << XS1_PORT_PAD_CTRL_E_SHIFT) & XS1_PORT_PAD_CTRL_E_MASK))

Pack the value (v) of the PORT_PAD_CTRL_E bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_SR

The pad control slew rate.

XS1_PORT_PAD_CTRL_SR_SHIFT 0x6

XS1_PORT_PAD_CTRL_SR_SIZE 0x1

XS1_PORT_PAD_CTRL_SR_MASK (((1 << XS1_PORT_PAD_CTRL_SR_SIZE) - 1) << XS1_PORT_PAD_CTRL_SR_SHIFT)

XS1_PORT_PAD_CTRL_SR(x) (((x) & XS1_PORT_PAD_CTRL_SR_MASK) >> XS1_PORT_PAD_CTRL_SR_SHIFT)

Extract the PORT_PAD_CTRL_SR bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_SR_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_SR_MASK) | (((v) << XS1_PORT_PAD_CTRL_SR_SHIFT) & XS1_PORT_PAD_CTRL_SR_MASK))

Pack the value (v) of the PORT_PAD_CTRL_SR bitfield into a packed word x and return the packed field.

PORT_PAD_CTRL_SMT

The pad control Schmitt trigger enable.

XS1_PORT_PAD_CTRL_SMT_SHIFT 0x7

XS1_PORT_PAD_CTRL_SMT_SIZE 0x1

XS1_PORT_PAD_CTRL_SMT_MASK (((1 << XS1_PORT_PAD_CTRL_SMT_SIZE) - 1) << XS1_PORT_PAD_CTRL_SMT_SHIFT)

XS1_PORT_PAD_CTRL_SMT(x) (((x) & XS1_PORT_PAD_CTRL_SMT_MASK) >> XS1_PORT_PAD_CTRL_SMT_SHIFT)

Extract the PORT_PAD_CTRL_SMT bitfield from a packed word x and return it.

XS1_PORT_PAD_CTRL_SMT_SET(x, v) (((x) & ~XS1_PORT_PAD_CTRL_SMT_MASK) | (((v) << XS1_PORT_PAD_CTRL_SMT_SHIFT) & XS1_PORT_PAD_CTRL_SMT_MASK))

Pack the value (v) of the PORT_PAD_CTRL_SMT bitfield into a packed word x and return the packed field.

TIMER_CTRL0_INUSE

Returns 1 when it in use, 0 otherwise.

XS1_TIMER_CTRL0_INUSE_SHIFT 0x0

XS1_TIMER_CTRL0_INUSE_SIZE 0x1

XS1_TIMER_CTRL0_INUSE_MASK (((1 << XS1_TIMER_CTRL0_INUSE_SIZE) - 1) << XS1_TIMER_CTRL0_INUSE_SHIFT)

XS1_TIMER_CTRL0_INUSE(x) (((x) & XS1_TIMER_CTRL0_INUSE_MASK) >> XS1_TIMER_CTRL0_INUSE_SHIFT)

Extract the TIMER_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_INUSE_MASK) | (((v) << XS1_TIMER_CTRL0_INUSE_SHIFT) & XS1_TIMER_CTRL0_INUSE_MASK))

Pack the value (v) of the TIMER_CTRL0_INUSE bitfield into a packed word x and return the packed field.

TIMER_CTRL0_IE_MODE

0 when this timer will cause events, 1 when it will raise interrupts. It is controlled using the SETC instruction.

XS1_TIMER_CTRL0_IE_MODE_SHIFT 0x1

XS1_TIMER_CTRL0_IE_MODE_SIZE 0x1

XS1_TIMER_CTRL0_IE_MODE_MASK (((1 << XS1_TIMER_CTRL0_IE_MODE_SIZE) - 1) << XS1_TIMER_CTRL0_IE_MODE_SHIFT)

XS1_TIMER_CTRL0_IE_MODE(x) (((x) & XS1_TIMER_CTRL0_IE_MODE_MASK) >> XS1_TIMER_CTRL0_IE_MODE_SHIFT)

Extract the TIMER_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_IE_MODE_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_IE_MODE_MASK) | (((v) << XS1_TIMER_CTRL0_IE_MODE_SHIFT) & XS1_TIMER_CTRL0_IE_MODE_MASK))

Pack the value (v) of the TIMER_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

TIMER_CTRL0_IE_ENABLED

1 when events or interrupts on this timer are active. It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_TIMER_CTRL0_IE_ENABLED_SHIFT 0x2

XS1_TIMER_CTRL0_IE_ENABLED_SIZE 0x1

XS1_TIMER_CTRL0_IE_ENABLED_MASK (((1 << XS1_TIMER_CTRL0_IE_ENABLED_SIZE) - 1) << XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)

XS1_TIMER_CTRL0_IE_ENABLED(x) (((x) & XS1_TIMER_CTRL0_IE_ENABLED_MASK) >> XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)

Extract the TIMER_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_IE_ENABLED_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_IE_ENABLED_MASK) | (((v) << XS1_TIMER_CTRL0_IE_ENABLED_SHIFT) & XS1_TIMER_CTRL0_IE_ENABLED_MASK))

Pack the value (v) of the TIMER_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

TIMER_CTRL0_READY

1 when the condition has been met. It is cleared when a SETC, SETD, SETV, SETC or IN instruction is executed on the timer. 0 when the timer is not in use.

XS1_TIMER_CTRL0_READY_SHIFT 0x3

XS1_TIMER_CTRL0_READY_SIZE 0x1

XS1_TIMER_CTRL0_READY_MASK (((1 << XS1_TIMER_CTRL0_READY_SIZE) - 1) << XS1_TIMER_CTRL0_READY_SHIFT)

XS1_TIMER_CTRL0_READY(x) (((x) & XS1_TIMER_CTRL0_READY_MASK) >> XS1_TIMER_CTRL0_READY_SHIFT)

Extract the TIMER_CTRL0_READY bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_READY_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_READY_MASK) | (((v) << XS1_TIMER_CTRL0_READY_SHIFT) & XS1_TIMER_CTRL0_READY_MASK))

Pack the value (v) of the TIMER_CTRL0_READY bitfield into a packed word x and return the packed field.

TIMER_CTRL0_COND

Shows the current condition of the timer. The condition is set using the SETC instruction.

XS1_TIMER_CTRL0_COND_SHIFT 0x4

XS1_TIMER_CTRL0_COND_SIZE 0x1

XS1_TIMER_CTRL0_COND_MASK (((1 << XS1_TIMER_CTRL0_COND_SIZE) - 1) << XS1_TIMER_CTRL0_COND_SHIFT)

XS1_TIMER_CTRL0_COND(x) (((x) & XS1_TIMER_CTRL0_COND_MASK) >> XS1_TIMER_CTRL0_COND_SHIFT)

Extract the TIMER_CTRL0_COND bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_COND_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_COND_MASK) | (((v) << XS1_TIMER_CTRL0_COND_SHIFT) & XS1_TIMER_CTRL0_COND_MASK))

Pack the value (v) of the TIMER_CTRL0_COND bitfield into a packed word x and return the packed field.

TIMER_CTRL0_EV_VALID

1 when the Environment Vector is valid. When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_TIMER_CTRL0_EV_VALID_SHIFT 0x8

XS1_TIMER_CTRL0_EV_VALID_SIZE 0x1

XS1_TIMER_CTRL0_EV_VALID_MASK (((1 << XS1_TIMER_CTRL0_EV_VALID_SIZE) - 1) << XS1_TIMER_CTRL0_EV_VALID_SHIFT)

XS1_TIMER_CTRL0_EV_VALID(x) (((x) & XS1_TIMER_CTRL0_EV_VALID_MASK) >> XS1_TIMER_CTRL0_EV_VALID_SHIFT)

Extract the TIMER_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_EV_VALID_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_EV_VALID_MASK) | (((v) << XS1_TIMER_CTRL0_EV_VALID_SHIFT) & XS1_TIMER_CTRL0_EV_VALID_MASK))

Pack the value (v) of the TIMER_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

TIMER_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this timer.

XS1_TIMER_CTRL0_T_WAITING_SHIFT 0x17

XS1_TIMER_CTRL0_T_WAITING_SIZE 0x1

XS1_TIMER_CTRL0_T_WAITING_MASK (((1 << XS1_TIMER_CTRL0_T_WAITING_SIZE) - 1) << XS1_TIMER_CTRL0_T_WAITING_SHIFT)

XS1_TIMER_CTRL0_T_WAITING(x) (((x) & XS1_TIMER_CTRL0_T_WAITING_MASK) >> XS1_TIMER_CTRL0_T_WAITING_SHIFT)

Extract the TIMER_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_T_WAITING_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_T_WAITING_MASK) | (((v) << XS1_TIMER_CTRL0_T_WAITING_SHIFT) & XS1_TIMER_CTRL0_T_WAITING_MASK))

Pack the value (v) of the TIMER_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

TIMER_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this timer.

XS1_TIMER_CTRL0_T_NUM_SHIFT 0x18

XS1_TIMER_CTRL0_T_NUM_SIZE 0x8

XS1_TIMER_CTRL0_T_NUM_MASK (((1 << XS1_TIMER_CTRL0_T_NUM_SIZE) - 1) << XS1_TIMER_CTRL0_T_NUM_SHIFT)

XS1_TIMER_CTRL0_T_NUM(x) (((x) & XS1_TIMER_CTRL0_T_NUM_MASK) >> XS1_TIMER_CTRL0_T_NUM_SHIFT)

Extract the TIMER_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_TIMER_CTRL0_T_NUM_SET(x, v) (((x) & ~XS1_TIMER_CTRL0_T_NUM_MASK) | (((v) << XS1_TIMER_CTRL0_T_NUM_SHIFT) & XS1_TIMER_CTRL0_T_NUM_MASK))

Pack the value (v) of the TIMER_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_INUSE

Returns 1 when it in use, 0 otherwise.

XS1_SWMEM_CTRL0_INUSE_SHIFT 0x0

XS1_SWMEM_CTRL0_INUSE_SIZE 0x1

XS1_SWMEM_CTRL0_INUSE_MASK (((1 << XS1_SWMEM_CTRL0_INUSE_SIZE) - 1) << XS1_SWMEM_CTRL0_INUSE_SHIFT)

XS1_SWMEM_CTRL0_INUSE(x) (((x) & XS1_SWMEM_CTRL0_INUSE_MASK) >> XS1_SWMEM_CTRL0_INUSE_SHIFT)

Extract the SWMEM_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_INUSE_MASK) | (((v) << XS1_SWMEM_CTRL0_INUSE_SHIFT) & XS1_SWMEM_CTRL0_INUSE_MASK))

Pack the value (v) of the SWMEM_CTRL0_INUSE bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_IE_MODE

0 when this SWMEM resource will cause events, 1 when it will raise interrupts. It is controlled using the SETC instruction.

XS1_SWMEM_CTRL0_IE_MODE_SHIFT 0x1

XS1_SWMEM_CTRL0_IE_MODE_SIZE 0x1

XS1_SWMEM_CTRL0_IE_MODE_MASK (((1 << XS1_SWMEM_CTRL0_IE_MODE_SIZE) - 1) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT)

XS1_SWMEM_CTRL0_IE_MODE(x) (((x) & XS1_SWMEM_CTRL0_IE_MODE_MASK) >> XS1_SWMEM_CTRL0_IE_MODE_SHIFT)

Extract the SWMEM_CTRL0_IE_MODE bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_IE_MODE_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_IE_MODE_MASK) | (((v) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT) & XS1_SWMEM_CTRL0_IE_MODE_MASK))

Pack the value (v) of the SWMEM_CTRL0_IE_MODE bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_IE_ENABLED

1 when events or interrupts on this SWMEM are active. It is set when an EEU is executed. It is cleared when a EDU or CLRE is executed. The EET and EEF will either set or clear the bit depending on the contents of the condition register.

XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT 0x2

XS1_SWMEM_CTRL0_IE_ENABLED_SIZE 0x1

XS1_SWMEM_CTRL0_IE_ENABLED_MASK (((1 << XS1_SWMEM_CTRL0_IE_ENABLED_SIZE) - 1) << XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)

XS1_SWMEM_CTRL0_IE_ENABLED(x) (((x) & XS1_SWMEM_CTRL0_IE_ENABLED_MASK) >> XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)

Extract the SWMEM_CTRL0_IE_ENABLED bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_IE_ENABLED_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_IE_ENABLED_MASK) | (((v) << XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT) & XS1_SWMEM_CTRL0_IE_ENABLED_MASK))

Pack the value (v) of the SWMEM_CTRL0_IE_ENABLED bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_READY

1 when the condition has been met. It is cleared when a SETC, SETD, SETV, SETC or IN instruction is executed on the SWMEM. 0 when the SWMEM is not in use.

XS1_SWMEM_CTRL0_READY_SHIFT 0x3

XS1_SWMEM_CTRL0_READY_SIZE 0x1

XS1_SWMEM_CTRL0_READY_MASK (((1 << XS1_SWMEM_CTRL0_READY_SIZE) - 1) << XS1_SWMEM_CTRL0_READY_SHIFT)

XS1_SWMEM_CTRL0_READY(x) (((x) & XS1_SWMEM_CTRL0_READY_MASK) >> XS1_SWMEM_CTRL0_READY_SHIFT)

Extract the SWMEM_CTRL0_READY bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_READY_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_READY_MASK) | (((v) << XS1_SWMEM_CTRL0_READY_SHIFT) & XS1_SWMEM_CTRL0_READY_MASK))

Pack the value (v) of the SWMEM_CTRL0_READY bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_COND

Shows the current condition of the SWMEM. The condition is set using the SETC instruction.

XS1_SWMEM_CTRL0_COND_SHIFT 0x4

XS1_SWMEM_CTRL0_COND_SIZE 0x1

XS1_SWMEM_CTRL0_COND_MASK (((1 << XS1_SWMEM_CTRL0_COND_SIZE) - 1) << XS1_SWMEM_CTRL0_COND_SHIFT)

XS1_SWMEM_CTRL0_COND(x) (((x) & XS1_SWMEM_CTRL0_COND_MASK) >> XS1_SWMEM_CTRL0_COND_SHIFT)

Extract the SWMEM_CTRL0_COND bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_COND_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_COND_MASK) | (((v) << XS1_SWMEM_CTRL0_COND_SHIFT) & XS1_SWMEM_CTRL0_COND_MASK))

Pack the value (v) of the SWMEM_CTRL0_COND bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_EV_VALID

1 when the Environment Vector is valid. When invalid, the resourceId is used as the environment vector. The environment vector is set using the SETEV instruction.

XS1_SWMEM_CTRL0_EV_VALID_SHIFT 0x8

XS1_SWMEM_CTRL0_EV_VALID_SIZE 0x1

XS1_SWMEM_CTRL0_EV_VALID_MASK (((1 << XS1_SWMEM_CTRL0_EV_VALID_SIZE) - 1) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT)

XS1_SWMEM_CTRL0_EV_VALID(x) (((x) & XS1_SWMEM_CTRL0_EV_VALID_MASK) >> XS1_SWMEM_CTRL0_EV_VALID_SHIFT)

Extract the SWMEM_CTRL0_EV_VALID bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_EV_VALID_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_EV_VALID_MASK) | (((v) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT) & XS1_SWMEM_CTRL0_EV_VALID_MASK))

Pack the value (v) of the SWMEM_CTRL0_EV_VALID bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_T_WAITING

1 when there is a thread waiting to be unblocked by this SWMEM.

XS1_SWMEM_CTRL0_T_WAITING_SHIFT 0x17

XS1_SWMEM_CTRL0_T_WAITING_SIZE 0x1

XS1_SWMEM_CTRL0_T_WAITING_MASK (((1 << XS1_SWMEM_CTRL0_T_WAITING_SIZE) - 1) << XS1_SWMEM_CTRL0_T_WAITING_SHIFT)

XS1_SWMEM_CTRL0_T_WAITING(x) (((x) & XS1_SWMEM_CTRL0_T_WAITING_MASK) >> XS1_SWMEM_CTRL0_T_WAITING_SHIFT)

Extract the SWMEM_CTRL0_T_WAITING bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_T_WAITING_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_T_WAITING_MASK) | (((v) << XS1_SWMEM_CTRL0_T_WAITING_SHIFT) & XS1_SWMEM_CTRL0_T_WAITING_MASK))

Pack the value (v) of the SWMEM_CTRL0_T_WAITING bitfield into a packed word x and return the packed field.

SWMEM_CTRL0_T_NUM

Number of the thread waiting for events or to be unblocked by this SWMEM resource.

XS1_SWMEM_CTRL0_T_NUM_SHIFT 0x18

XS1_SWMEM_CTRL0_T_NUM_SIZE 0x8

XS1_SWMEM_CTRL0_T_NUM_MASK (((1 << XS1_SWMEM_CTRL0_T_NUM_SIZE) - 1) << XS1_SWMEM_CTRL0_T_NUM_SHIFT)

XS1_SWMEM_CTRL0_T_NUM(x) (((x) & XS1_SWMEM_CTRL0_T_NUM_MASK) >> XS1_SWMEM_CTRL0_T_NUM_SHIFT)

Extract the SWMEM_CTRL0_T_NUM bitfield from a packed word x and return it.

XS1_SWMEM_CTRL0_T_NUM_SET(x, v) (((x) & ~XS1_SWMEM_CTRL0_T_NUM_MASK) | (((v) << XS1_SWMEM_CTRL0_T_NUM_SHIFT) & XS1_SWMEM_CTRL0_T_NUM_MASK))

Pack the value (v) of the SWMEM_CTRL0_T_NUM bitfield into a packed word x and return the packed field.

OTPA_MOSI_LSB

OTP arbiter MOSI LSB.

XS1_OTPA_MOSI_LSB_SHIFT 0x0

XS1_OTPA_MOSI_LSB_SIZE 0x1

XS1_OTPA_MOSI_LSB_MASK (((1 << XS1_OTPA_MOSI_LSB_SIZE) - 1) << XS1_OTPA_MOSI_LSB_SHIFT)

XS1_OTPA_MOSI_LSB(x) (((x) & XS1_OTPA_MOSI_LSB_MASK) >> XS1_OTPA_MOSI_LSB_SHIFT)

Extract the OTPA_MOSI_LSB bitfield from a packed word x and return it.

XS1_OTPA_MOSI_LSB_SET(x, v) (((x) & ~XS1_OTPA_MOSI_LSB_MASK) | (((v) << XS1_OTPA_MOSI_LSB_SHIFT) & XS1_OTPA_MOSI_LSB_MASK))

Pack the value (v) of the OTPA_MOSI_LSB bitfield into a packed word x and return the packed field.

OTPA_MOSI_MSB

OTP arbiter MOSI LSB.

XS1_OTPA_MOSI_MSB_SHIFT 0x7

XS1_OTPA_MOSI_MSB_SIZE 0x1

XS1_OTPA_MOSI_MSB_MASK (((1 << XS1_OTPA_MOSI_MSB_SIZE) - 1) << XS1_OTPA_MOSI_MSB_SHIFT)

XS1_OTPA_MOSI_MSB(x) (((x) & XS1_OTPA_MOSI_MSB_MASK) >> XS1_OTPA_MOSI_MSB_SHIFT)

Extract the OTPA_MOSI_MSB bitfield from a packed word x and return it.

XS1_OTPA_MOSI_MSB_SET(x, v) (((x) & ~XS1_OTPA_MOSI_MSB_MASK) | (((v) << XS1_OTPA_MOSI_MSB_SHIFT) & XS1_OTPA_MOSI_MSB_MASK))

Pack the value (v) of the OTPA_MOSI_MSB bitfield into a packed word x and return the packed field.

OTPA_CLK_IDX

OTP SBPI CLK input.

XS1_OTPA_CLK_IDX_SHIFT 0x8

XS1_OTPA_CLK_IDX_SIZE 0x1

XS1_OTPA_CLK_IDX_MASK (((1 << XS1_OTPA_CLK_IDX_SIZE) - 1) << XS1_OTPA_CLK_IDX_SHIFT)

XS1_OTPA_CLK_IDX(x) (((x) & XS1_OTPA_CLK_IDX_MASK) >> XS1_OTPA_CLK_IDX_SHIFT)

Extract the OTPA_CLK_IDX bitfield from a packed word x and return it.

XS1_OTPA_CLK_IDX_SET(x, v) (((x) & ~XS1_OTPA_CLK_IDX_MASK) | (((v) << XS1_OTPA_CLK_IDX_SHIFT) & XS1_OTPA_CLK_IDX_MASK))

Pack the value (v) of the OTPA_CLK_IDX bitfield into a packed word x and return the packed field.

OTPA_SP_IDX

OTP SBPI SP input.

XS1_OTPA_SP_IDX_SHIFT 0x9

XS1_OTPA_SP_IDX_SIZE 0x1

XS1_OTPA_SP_IDX_MASK (((1 << XS1_OTPA_SP_IDX_SIZE) - 1) << XS1_OTPA_SP_IDX_SHIFT)

XS1_OTPA_SP_IDX(x) (((x) & XS1_OTPA_SP_IDX_MASK) >> XS1_OTPA_SP_IDX_SHIFT)

Extract the OTPA_SP_IDX bitfield from a packed word x and return it.

XS1_OTPA_SP_IDX_SET(x, v) (((x) & ~XS1_OTPA_SP_IDX_MASK) | (((v) << XS1_OTPA_SP_IDX_SHIFT) & XS1_OTPA_SP_IDX_MASK))

Pack the value (v) of the OTPA_SP_IDX bitfield into a packed word x and return the packed field.

OTPA_CS_IDX

OTP SBPI CS (chip select) input.

XS1_OTPA_CS_IDX_SHIFT 0xa

XS1_OTPA_CS_IDX_SIZE 0x1

XS1_OTPA_CS_IDX_MASK (((1 << XS1_OTPA_CS_IDX_SIZE) - 1) << XS1_OTPA_CS_IDX_SHIFT)

XS1_OTPA_CS_IDX(x) (((x) & XS1_OTPA_CS_IDX_MASK) >> XS1_OTPA_CS_IDX_SHIFT)

Extract the OTPA_CS_IDX bitfield from a packed word x and return it.

XS1_OTPA_CS_IDX_SET(x, v) (((x) & ~XS1_OTPA_CS_IDX_MASK) | (((v) << XS1_OTPA_CS_IDX_SHIFT) & XS1_OTPA_CS_IDX_MASK))

Pack the value (v) of the OTPA_CS_IDX bitfield into a packed word x and return the packed field.

OTPA_CKE_IDX

OTP SBPI CKE (clock enable) input.

XS1_OTPA_CKE_IDX_SHIFT 0xb

XS1_OTPA_CKE_IDX_SIZE 0x1

XS1_OTPA_CKE_IDX_MASK (((1 << XS1_OTPA_CKE_IDX_SIZE) - 1) << XS1_OTPA_CKE_IDX_SHIFT)

XS1_OTPA_CKE_IDX(x) (((x) & XS1_OTPA_CKE_IDX_MASK) >> XS1_OTPA_CKE_IDX_SHIFT)

Extract the OTPA_CKE_IDX bitfield from a packed word x and return it.

XS1_OTPA_CKE_IDX_SET(x, v) (((x) & ~XS1_OTPA_CKE_IDX_MASK) | (((v) << XS1_OTPA_CKE_IDX_SHIFT) & XS1_OTPA_CKE_IDX_MASK))

Pack the value (v) of the OTPA_CKE_IDX bitfield into a packed word x and return the packed field.

OTPA_DCTRL_IDX

OTP USER DCTRL input.

XS1_OTPA_DCTRL_IDX_SHIFT 0xc

XS1_OTPA_DCTRL_IDX_SIZE 0x1

XS1_OTPA_DCTRL_IDX_MASK (((1 << XS1_OTPA_DCTRL_IDX_SIZE) - 1) << XS1_OTPA_DCTRL_IDX_SHIFT)

XS1_OTPA_DCTRL_IDX(x) (((x) & XS1_OTPA_DCTRL_IDX_MASK) >> XS1_OTPA_DCTRL_IDX_SHIFT)

Extract the OTPA_DCTRL_IDX bitfield from a packed word x and return it.

XS1_OTPA_DCTRL_IDX_SET(x, v) (((x) & ~XS1_OTPA_DCTRL_IDX_MASK) | (((v) << XS1_OTPA_DCTRL_IDX_SHIFT) & XS1_OTPA_DCTRL_IDX_MASK))

Pack the value (v) of the OTPA_DCTRL_IDX bitfield into a packed word x and return the packed field.

OTPA_PD_IDX

OTP USER PD input.

XS1_OTPA_PD_IDX_SHIFT 0xd

XS1_OTPA_PD_IDX_SIZE 0x1

XS1_OTPA_PD_IDX_MASK (((1 << XS1_OTPA_PD_IDX_SIZE) - 1) << XS1_OTPA_PD_IDX_SHIFT)

XS1_OTPA_PD_IDX(x) (((x) & XS1_OTPA_PD_IDX_MASK) >> XS1_OTPA_PD_IDX_SHIFT)

Extract the OTPA_PD_IDX bitfield from a packed word x and return it.

XS1_OTPA_PD_IDX_SET(x, v) (((x) & ~XS1_OTPA_PD_IDX_MASK) | (((v) << XS1_OTPA_PD_IDX_SHIFT) & XS1_OTPA_PD_IDX_MASK))

Pack the value (v) of the OTPA_PD_IDX bitfield into a packed word x and return the packed field.

OTPA_SEL_IDX

OTP USER SEL input.

XS1_OTPA_SEL_IDX_SHIFT 0xe

XS1_OTPA_SEL_IDX_SIZE 0x1

XS1_OTPA_SEL_IDX_MASK (((1 << XS1_OTPA_SEL_IDX_SIZE) - 1) << XS1_OTPA_SEL_IDX_SHIFT)

XS1_OTPA_SEL_IDX(x) (((x) & XS1_OTPA_SEL_IDX_MASK) >> XS1_OTPA_SEL_IDX_SHIFT)

Extract the OTPA_SEL_IDX bitfield from a packed word x and return it.

XS1_OTPA_SEL_IDX_SET(x, v) (((x) & ~XS1_OTPA_SEL_IDX_MASK) | (((v) << XS1_OTPA_SEL_IDX_SHIFT) & XS1_OTPA_SEL_IDX_MASK))

Pack the value (v) of the OTPA_SEL_IDX bitfield into a packed word x and return the packed field.

OTPA_CK_IDX

OTP USER CK input.

XS1_OTPA_CK_IDX_SHIFT 0xf

XS1_OTPA_CK_IDX_SIZE 0x1

XS1_OTPA_CK_IDX_MASK (((1 << XS1_OTPA_CK_IDX_SIZE) - 1) << XS1_OTPA_CK_IDX_SHIFT)

XS1_OTPA_CK_IDX(x) (((x) & XS1_OTPA_CK_IDX_MASK) >> XS1_OTPA_CK_IDX_SHIFT)

Extract the OTPA_CK_IDX bitfield from a packed word x and return it.

XS1_OTPA_CK_IDX_SET(x, v) (((x) & ~XS1_OTPA_CK_IDX_MASK) | (((v) << XS1_OTPA_CK_IDX_SHIFT) & XS1_OTPA_CK_IDX_MASK))

Pack the value (v) of the OTPA_CK_IDX bitfield into a packed word x and return the packed field.

OTPA_A_LSB

OTP USER A (address) LSB (bit 0).

XS1_OTPA_A_LSB_SHIFT 0x10

XS1_OTPA_A_LSB_SIZE 0x1

XS1_OTPA_A_LSB_MASK (((1 << XS1_OTPA_A_LSB_SIZE) - 1) << XS1_OTPA_A_LSB_SHIFT)

XS1_OTPA_A_LSB(x) (((x) & XS1_OTPA_A_LSB_MASK) >> XS1_OTPA_A_LSB_SHIFT)

Extract the OTPA_A_LSB bitfield from a packed word x and return it.

XS1_OTPA_A_LSB_SET(x, v) (((x) & ~XS1_OTPA_A_LSB_MASK) | (((v) << XS1_OTPA_A_LSB_SHIFT) & XS1_OTPA_A_LSB_MASK))

Pack the value (v) of the OTPA_A_LSB bitfield into a packed word x and return the packed field.

OTPA_A_MSB

OTP USER A (address) MSB (bit 10).

XS1_OTPA_A_MSB_SHIFT 0x1a

XS1_OTPA_A_MSB_SIZE 0x1

XS1_OTPA_A_MSB_MASK (((1 << XS1_OTPA_A_MSB_SIZE) - 1) << XS1_OTPA_A_MSB_SHIFT)

XS1_OTPA_A_MSB(x) (((x) & XS1_OTPA_A_MSB_MASK) >> XS1_OTPA_A_MSB_SHIFT)

Extract the OTPA_A_MSB bitfield from a packed word x and return it.

XS1_OTPA_A_MSB_SET(x, v) (((x) & ~XS1_OTPA_A_MSB_MASK) | (((v) << XS1_OTPA_A_MSB_SHIFT) & XS1_OTPA_A_MSB_MASK))

Pack the value (v) of the OTPA_A_MSB bitfield into a packed word x and return the packed field.

OTPA_RST_IDX

OTP reset input (active high)

XS1_OTPA_RST_IDX_SHIFT 0x1b

XS1_OTPA_RST_IDX_SIZE 0x1

XS1_OTPA_RST_IDX_MASK (((1 << XS1_OTPA_RST_IDX_SIZE) - 1) << XS1_OTPA_RST_IDX_SHIFT)

XS1_OTPA_RST_IDX(x) (((x) & XS1_OTPA_RST_IDX_MASK) >> XS1_OTPA_RST_IDX_SHIFT)

Extract the OTPA_RST_IDX bitfield from a packed word x and return it.

XS1_OTPA_RST_IDX_SET(x, v) (((x) & ~XS1_OTPA_RST_IDX_MASK) | (((v) << XS1_OTPA_RST_IDX_SHIFT) & XS1_OTPA_RST_IDX_MASK))

Pack the value (v) of the OTPA_RST_IDX bitfield into a packed word x and return the packed field.

OTPA_ARB_REQ_IDX

OTP arbiter request

XS1_OTPA_ARB_REQ_IDX_SHIFT 0x1c

XS1_OTPA_ARB_REQ_IDX_SIZE 0x1

XS1_OTPA_ARB_REQ_IDX_MASK (((1 << XS1_OTPA_ARB_REQ_IDX_SIZE) - 1) << XS1_OTPA_ARB_REQ_IDX_SHIFT)

XS1_OTPA_ARB_REQ_IDX(x) (((x) & XS1_OTPA_ARB_REQ_IDX_MASK) >> XS1_OTPA_ARB_REQ_IDX_SHIFT)

Extract the OTPA_ARB_REQ_IDX bitfield from a packed word x and return it.

XS1_OTPA_ARB_REQ_IDX_SET(x, v) (((x) & ~XS1_OTPA_ARB_REQ_IDX_MASK) | (((v) << XS1_OTPA_ARB_REQ_IDX_SHIFT) & XS1_OTPA_ARB_REQ_IDX_MASK))

Pack the value (v) of the OTPA_ARB_REQ_IDX bitfield into a packed word x and return the packed field.

OTPA_MUXSEL_LSB

OTP mux select LSB

XS1_OTPA_MUXSEL_LSB_SHIFT 0x1d

XS1_OTPA_MUXSEL_LSB_SIZE 0x1

XS1_OTPA_MUXSEL_LSB_MASK (((1 << XS1_OTPA_MUXSEL_LSB_SIZE) - 1) << XS1_OTPA_MUXSEL_LSB_SHIFT)

XS1_OTPA_MUXSEL_LSB(x) (((x) & XS1_OTPA_MUXSEL_LSB_MASK) >> XS1_OTPA_MUXSEL_LSB_SHIFT)

Extract the OTPA_MUXSEL_LSB bitfield from a packed word x and return it.

XS1_OTPA_MUXSEL_LSB_SET(x, v) (((x) & ~XS1_OTPA_MUXSEL_LSB_MASK) | (((v) << XS1_OTPA_MUXSEL_LSB_SHIFT) & XS1_OTPA_MUXSEL_LSB_MASK))

Pack the value (v) of the OTPA_MUXSEL_LSB bitfield into a packed word x and return the packed field.

OTPA_MUXSEL_MSB

OTP mux select MSB

XS1_OTPA_MUXSEL_MSB_SHIFT 0x1f

XS1_OTPA_MUXSEL_MSB_SIZE 0x1

XS1_OTPA_MUXSEL_MSB_MASK (((1 << XS1_OTPA_MUXSEL_MSB_SIZE) - 1) << XS1_OTPA_MUXSEL_MSB_SHIFT)

XS1_OTPA_MUXSEL_MSB(x) (((x) & XS1_OTPA_MUXSEL_MSB_MASK) >> XS1_OTPA_MUXSEL_MSB_SHIFT)

Extract the OTPA_MUXSEL_MSB bitfield from a packed word x and return it.

XS1_OTPA_MUXSEL_MSB_SET(x, v) (((x) & ~XS1_OTPA_MUXSEL_MSB_MASK) | (((v) << XS1_OTPA_MUXSEL_MSB_SHIFT) & XS1_OTPA_MUXSEL_MSB_MASK))

Pack the value (v) of the OTPA_MUXSEL_MSB bitfield into a packed word x and return the packed field.

OTPA_MISO_LSB

OTP arbiter MISO LSB.

XS1_OTPA_MISO_LSB_SHIFT 0x0

XS1_OTPA_MISO_LSB_SIZE 0x1

XS1_OTPA_MISO_LSB_MASK (((1 << XS1_OTPA_MISO_LSB_SIZE) - 1) << XS1_OTPA_MISO_LSB_SHIFT)

XS1_OTPA_MISO_LSB(x) (((x) & XS1_OTPA_MISO_LSB_MASK) >> XS1_OTPA_MISO_LSB_SHIFT)

Extract the OTPA_MISO_LSB bitfield from a packed word x and return it.

XS1_OTPA_MISO_LSB_SET(x, v) (((x) & ~XS1_OTPA_MISO_LSB_MASK) | (((v) << XS1_OTPA_MISO_LSB_SHIFT) & XS1_OTPA_MISO_LSB_MASK))

Pack the value (v) of the OTPA_MISO_LSB bitfield into a packed word x and return the packed field.

OTPA_MISO_MSB

OTP arbiter MISO LSB.

XS1_OTPA_MISO_MSB_SHIFT 0x7

XS1_OTPA_MISO_MSB_SIZE 0x1

XS1_OTPA_MISO_MSB_MASK (((1 << XS1_OTPA_MISO_MSB_SIZE) - 1) << XS1_OTPA_MISO_MSB_SHIFT)

XS1_OTPA_MISO_MSB(x) (((x) & XS1_OTPA_MISO_MSB_MASK) >> XS1_OTPA_MISO_MSB_SHIFT)

Extract the OTPA_MISO_MSB bitfield from a packed word x and return it.

XS1_OTPA_MISO_MSB_SET(x, v) (((x) & ~XS1_OTPA_MISO_MSB_MASK) | (((v) << XS1_OTPA_MISO_MSB_SHIFT) & XS1_OTPA_MISO_MSB_MASK))

Pack the value (v) of the OTPA_MISO_MSB bitfield into a packed word x and return the packed field.

OTPA_FLAG_IDX

OTP SBPI flag status.

XS1_OTPA_FLAG_IDX_SHIFT 0x8

XS1_OTPA_FLAG_IDX_SIZE 0x1

XS1_OTPA_FLAG_IDX_MASK (((1 << XS1_OTPA_FLAG_IDX_SIZE) - 1) << XS1_OTPA_FLAG_IDX_SHIFT)

XS1_OTPA_FLAG_IDX(x) (((x) & XS1_OTPA_FLAG_IDX_MASK) >> XS1_OTPA_FLAG_IDX_SHIFT)

Extract the OTPA_FLAG_IDX bitfield from a packed word x and return it.

XS1_OTPA_FLAG_IDX_SET(x, v) (((x) & ~XS1_OTPA_FLAG_IDX_MASK) | (((v) << XS1_OTPA_FLAG_IDX_SHIFT) & XS1_OTPA_FLAG_IDX_MASK))

Pack the value (v) of the OTPA_FLAG_IDX bitfield into a packed word x and return the packed field.

OTPA_ARB_GNT_IDX

OTP arbiter granted.

XS1_OTPA_ARB_GNT_IDX_SHIFT 0x9

XS1_OTPA_ARB_GNT_IDX_SIZE 0x1

XS1_OTPA_ARB_GNT_IDX_MASK (((1 << XS1_OTPA_ARB_GNT_IDX_SIZE) - 1) << XS1_OTPA_ARB_GNT_IDX_SHIFT)

XS1_OTPA_ARB_GNT_IDX(x) (((x) & XS1_OTPA_ARB_GNT_IDX_MASK) >> XS1_OTPA_ARB_GNT_IDX_SHIFT)

Extract the OTPA_ARB_GNT_IDX bitfield from a packed word x and return it.

XS1_OTPA_ARB_GNT_IDX_SET(x, v) (((x) & ~XS1_OTPA_ARB_GNT_IDX_MASK) | (((v) << XS1_OTPA_ARB_GNT_IDX_SHIFT) & XS1_OTPA_ARB_GNT_IDX_MASK))

Pack the value (v) of the OTPA_ARB_GNT_IDX bitfield into a packed word x and return the packed field.

OTP_DAP_RFMR_MR_4

OTP DAP RFMR register MR_4 control.

XS1_OTP_DAP_RFMR_MR_4_SHIFT 0x5

XS1_OTP_DAP_RFMR_MR_4_SIZE 0x1

XS1_OTP_DAP_RFMR_MR_4_MASK (((1 << XS1_OTP_DAP_RFMR_MR_4_SIZE) - 1) << XS1_OTP_DAP_RFMR_MR_4_SHIFT)

XS1_OTP_DAP_RFMR_MR_4(x) (((x) & XS1_OTP_DAP_RFMR_MR_4_MASK) >> XS1_OTP_DAP_RFMR_MR_4_SHIFT)

Extract the OTP_DAP_RFMR_MR_4 bitfield from a packed word x and return it.

XS1_OTP_DAP_RFMR_MR_4_SET(x, v) (((x) & ~XS1_OTP_DAP_RFMR_MR_4_MASK) | (((v) << XS1_OTP_DAP_RFMR_MR_4_SHIFT) & XS1_OTP_DAP_RFMR_MR_4_MASK))

Pack the value (v) of the OTP_DAP_RFMR_MR_4 bitfield into a packed word x and return the packed field.

OTP_DAP_RFMR_MR_5

OTP DAP RFMR register MR_5 control.

XS1_OTP_DAP_RFMR_MR_5_SHIFT 0x6

XS1_OTP_DAP_RFMR_MR_5_SIZE 0x1

XS1_OTP_DAP_RFMR_MR_5_MASK (((1 << XS1_OTP_DAP_RFMR_MR_5_SIZE) - 1) << XS1_OTP_DAP_RFMR_MR_5_SHIFT)

XS1_OTP_DAP_RFMR_MR_5(x) (((x) & XS1_OTP_DAP_RFMR_MR_5_MASK) >> XS1_OTP_DAP_RFMR_MR_5_SHIFT)

Extract the OTP_DAP_RFMR_MR_5 bitfield from a packed word x and return it.

XS1_OTP_DAP_RFMR_MR_5_SET(x, v) (((x) & ~XS1_OTP_DAP_RFMR_MR_5_MASK) | (((v) << XS1_OTP_DAP_RFMR_MR_5_SHIFT) & XS1_OTP_DAP_RFMR_MR_5_MASK))

Pack the value (v) of the OTP_DAP_RFMR_MR_5 bitfield into a packed word x and return the packed field.

SYNC_CTRL0_INUSE

1 when the synchroniser is in use.

XS1_SYNC_CTRL0_INUSE_SHIFT 0x0

XS1_SYNC_CTRL0_INUSE_SIZE 0x1

XS1_SYNC_CTRL0_INUSE_MASK (((1 << XS1_SYNC_CTRL0_INUSE_SIZE) - 1) << XS1_SYNC_CTRL0_INUSE_SHIFT)

XS1_SYNC_CTRL0_INUSE(x) (((x) & XS1_SYNC_CTRL0_INUSE_MASK) >> XS1_SYNC_CTRL0_INUSE_SHIFT)

Extract the SYNC_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_SYNC_CTRL0_INUSE_MASK) | (((v) << XS1_SYNC_CTRL0_INUSE_SHIFT) & XS1_SYNC_CTRL0_INUSE_MASK))

Pack the value (v) of the SYNC_CTRL0_INUSE bitfield into a packed word x and return the packed field.

SYNC_CTRL0_MSYNCED

1 when the master of this synchroniser has msynced on it.

XS1_SYNC_CTRL0_MSYNCED_SHIFT 0x1

XS1_SYNC_CTRL0_MSYNCED_SIZE 0x1

XS1_SYNC_CTRL0_MSYNCED_MASK (((1 << XS1_SYNC_CTRL0_MSYNCED_SIZE) - 1) << XS1_SYNC_CTRL0_MSYNCED_SHIFT)

XS1_SYNC_CTRL0_MSYNCED(x) (((x) & XS1_SYNC_CTRL0_MSYNCED_MASK) >> XS1_SYNC_CTRL0_MSYNCED_SHIFT)

Extract the SYNC_CTRL0_MSYNCED bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_MSYNCED_SET(x, v) (((x) & ~XS1_SYNC_CTRL0_MSYNCED_MASK) | (((v) << XS1_SYNC_CTRL0_MSYNCED_SHIFT) & XS1_SYNC_CTRL0_MSYNCED_MASK))

Pack the value (v) of the SYNC_CTRL0_MSYNCED bitfield into a packed word x and return the packed field.

SYNC_CTRL0_JOIN

1 when the synchroniser will free the threads after synchronisation. 0 otherwise.

XS1_SYNC_CTRL0_JOIN_SHIFT 0x2

XS1_SYNC_CTRL0_JOIN_SIZE 0x1

XS1_SYNC_CTRL0_JOIN_MASK (((1 << XS1_SYNC_CTRL0_JOIN_SIZE) - 1) << XS1_SYNC_CTRL0_JOIN_SHIFT)

XS1_SYNC_CTRL0_JOIN(x) (((x) & XS1_SYNC_CTRL0_JOIN_MASK) >> XS1_SYNC_CTRL0_JOIN_SHIFT)

Extract the SYNC_CTRL0_JOIN bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_JOIN_SET(x, v) (((x) & ~XS1_SYNC_CTRL0_JOIN_MASK) | (((v) << XS1_SYNC_CTRL0_JOIN_SHIFT) & XS1_SYNC_CTRL0_JOIN_MASK))

Pack the value (v) of the SYNC_CTRL0_JOIN bitfield into a packed word x and return the packed field.

SYNC_CTRL0_MASTER

When synchroniser is in use it is the ID of the master thread. 0 when not in use.

XS1_SYNC_CTRL0_MASTER_SHIFT 0x8

XS1_SYNC_CTRL0_MASTER_SIZE 0x8

XS1_SYNC_CTRL0_MASTER_MASK (((1 << XS1_SYNC_CTRL0_MASTER_SIZE) - 1) << XS1_SYNC_CTRL0_MASTER_SHIFT)

XS1_SYNC_CTRL0_MASTER(x) (((x) & XS1_SYNC_CTRL0_MASTER_MASK) >> XS1_SYNC_CTRL0_MASTER_SHIFT)

Extract the SYNC_CTRL0_MASTER bitfield from a packed word x and return it.

XS1_SYNC_CTRL0_MASTER_SET(x, v) (((x) & ~XS1_SYNC_CTRL0_MASTER_MASK) | (((v) << XS1_SYNC_CTRL0_MASTER_SHIFT) & XS1_SYNC_CTRL0_MASTER_MASK))

Pack the value (v) of the SYNC_CTRL0_MASTER bitfield into a packed word x and return the packed field.

SYNC_TBV0_SLAVES

1 bit for each of the threads. When 1 indicates that the corresponding thread is attached to the synchroniser.

XS1_SYNC_TBV0_SLAVES_SHIFT 0x0

XS1_SYNC_TBV0_SLAVES_SIZE 0x8

XS1_SYNC_TBV0_SLAVES_MASK (((1 << XS1_SYNC_TBV0_SLAVES_SIZE) - 1) << XS1_SYNC_TBV0_SLAVES_SHIFT)

XS1_SYNC_TBV0_SLAVES(x) (((x) & XS1_SYNC_TBV0_SLAVES_MASK) >> XS1_SYNC_TBV0_SLAVES_SHIFT)

Extract the SYNC_TBV0_SLAVES bitfield from a packed word x and return it.

XS1_SYNC_TBV0_SLAVES_SET(x, v) (((x) & ~XS1_SYNC_TBV0_SLAVES_MASK) | (((v) << XS1_SYNC_TBV0_SLAVES_SHIFT) & XS1_SYNC_TBV0_SLAVES_MASK))

Pack the value (v) of the SYNC_TBV0_SLAVES bitfield into a packed word x and return the packed field.

LOCK_CTRL0_INUSE

1 when the lock is in use.

XS1_LOCK_CTRL0_INUSE_SHIFT 0x0

XS1_LOCK_CTRL0_INUSE_SIZE 0x1

XS1_LOCK_CTRL0_INUSE_MASK (((1 << XS1_LOCK_CTRL0_INUSE_SIZE) - 1) << XS1_LOCK_CTRL0_INUSE_SHIFT)

XS1_LOCK_CTRL0_INUSE(x) (((x) & XS1_LOCK_CTRL0_INUSE_MASK) >> XS1_LOCK_CTRL0_INUSE_SHIFT)

Extract the LOCK_CTRL0_INUSE bitfield from a packed word x and return it.

XS1_LOCK_CTRL0_INUSE_SET(x, v) (((x) & ~XS1_LOCK_CTRL0_INUSE_MASK) | (((v) << XS1_LOCK_CTRL0_INUSE_SHIFT) & XS1_LOCK_CTRL0_INUSE_MASK))

Pack the value (v) of the LOCK_CTRL0_INUSE bitfield into a packed word x and return the packed field.

LOCK_CTRL0_OWNT_V

Indicates that the lock’s owner is known.

XS1_LOCK_CTRL0_OWNT_V_SHIFT 0x1

XS1_LOCK_CTRL0_OWNT_V_SIZE 0x1

XS1_LOCK_CTRL0_OWNT_V_MASK (((1 << XS1_LOCK_CTRL0_OWNT_V_SIZE) - 1) << XS1_LOCK_CTRL0_OWNT_V_SHIFT)

XS1_LOCK_CTRL0_OWNT_V(x) (((x) & XS1_LOCK_CTRL0_OWNT_V_MASK) >> XS1_LOCK_CTRL0_OWNT_V_SHIFT)

Extract the LOCK_CTRL0_OWNT_V bitfield from a packed word x and return it.

XS1_LOCK_CTRL0_OWNT_V_SET(x, v) (((x) & ~XS1_LOCK_CTRL0_OWNT_V_MASK) | (((v) << XS1_LOCK_CTRL0_OWNT_V_SHIFT) & XS1_LOCK_CTRL0_OWNT_V_MASK))

Pack the value (v) of the LOCK_CTRL0_OWNT_V bitfield into a packed word x and return the packed field.

LOCK_CTRL0_OWNT

When OWNT_V is true then this is the ID of the thread currently holding the lock.

XS1_LOCK_CTRL0_OWNT_SHIFT 0x8

XS1_LOCK_CTRL0_OWNT_SIZE 0x8

XS1_LOCK_CTRL0_OWNT_MASK (((1 << XS1_LOCK_CTRL0_OWN