XSIM trace output

XSIM trace output is produced by using xsim -t, xsim --trace or xsim --trace-to.

The following example shows an except of the trace output from a program built for an xcore.ai device. It shows 8 logical cores running on tile 0. For each logical core, indentations using . to the addess field and subsequent fields is applied based on the logical core number.

tile[0]@0- -SI A-a-a-a-p-p-p-p-.----000803a8 (iprintf             + 18) : add     r1(0x81e04), r11(0x81e04), 0x0 @307446
tile[0]@1- -DI p-A-a-a-a-p-p-p-.----.00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307447
tile[0]@2- -DI p-p-A-a-a-a-p-p-.----..00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307448
tile[0]@3- -DI p-p-p-A-a-a-a-p-.----...00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307449
tile[0]@4- -DI p-p-p-p-A-a-a-a-.----....00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307450
tile[0]@5- -DI a-p-p-p-p-A-a-a-.----.....00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307451
tile[0]@6- -DI a-a-p-p-p-p-A-a-.----......00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307452
tile[0]@7- -DI a-a-a-p-p-p-p-A-.----.......00080390 (iprintf             +  0) : entsp   0x0 S[0x81f24] @307453

Each row represents the execution of a single instruction. For the first line in the above example, the fields show the following information:

  • tile[0]: the tile executing the instruction

  • @0 : the logical core executing the instruction

  • - -SI : the I0, I1, I2, I3 and I4 fields - see below

  • A-a-a-a-p-p-p-p- : the S0 and S1 fields for the eight active logical cores

  • 000803a8: program counter address

  • (iprintf             + 18): the function name symbol and offset from it

  • add     r1(0x81e04), r11(0x81e04), 0x0 @307446: instruction and operands

  • @3261: tile clock cycle count

When an instruction makes a load or store to memory the address will be shown, for example (L[0x42000]).

Further detail on the fields and the values they may contain is shown in the table below:

Table 38 Trace output field definitions

Tile and core

Core State (single character fields)

Name from XN

I0

I1

I2

I3

I4

S0

S1

M

S

K

N
Table 39 Trace output field definitions (continued)

Address

Instruction

Mem

Cycle

PC

(sym+offset):

name

operands

access

@val

For each field, the possible values and their meanings are shown below. Note the S0 and S1 character fields are repeated for each active core.

I0: - No debug interrupt
I0: D Instruction caused debug interrupt
I1: * Instruction excepted
I1: P Instruction paused
I2: - Not in debug mode
I2: d Tile in debug mode
I3: S Logical core in single issue mode
I3: D Logical core in dual issue mode
I4: I Always shows I
S0: - Logical core not in use
S0: a Logical core active
S0: A Logical core active (the instruction being traced belongs to this core)
S0: i Logical core active with ININT bit set
S0: I Logical core active with ININT bit set (belongs to this core)
S0: p Logical core paused due to instruction fetch
S0: m Logical core paused with MSYNC bit set
S0: s Logical core paused with SSYNC bit set
S0: w Logical core paused with WAITING bit set
S1: - Interrupts and events disabled
S1: b Interrupts and events enabled
S1: i Interrupts enabled and events disabled
S1: e Interrupts disabled and events enabled
M: - MSYNC not set
M: m MSYNC set
S: - SSYNC not set
S: s SSYNC set
K: - INK not set
K: k INK set
N: - INENB not set
N: n INENB set
operands: rn(val) Value val of register n
operands: res[id] Resource identifier id
access: L/S[addr] Load from/Store to address addr
@val: tile clock cycle count