How to guides

1. Log into xmos.com and access My XMOS > Reference Designs
2. Request access to the XMOS AVB-DC Software Release by clicking the Request Access link under AVB DAISY-CHAIN KIT. An email will be sent to your registered email address when access is granted.
3. A Download link will appear where the Request Access link previously appeared. Click and download the firmware zip.

The AVB-DC software requires xTIMEcomposer version 13.0.0 or greater. It can be downloaded at the following URL
https://1m2n3b4v.xmos.com/en/support/downloads/xtimecomposer

To import and build the firmware, open xTIMEcomposer Studio and
follow these steps:

1. Choose File > Import.
2. Choose General > Existing Projects into Workspace and
   click Next.
3. Click Browse next to `Select archive file` and select
   the firmware .zip file downloaded in section 1.
4. Make sure that all projects are ticked in the
   Projects list.
5. Click Finish.
6. Select the app_daisy_chain project in the Project Explorer and click the Build icon in the main toolbar.

1. Connect the xTAG-2 debug adapter (XA-SK-XTAG2) to the first sliceKIT core board.
2. Connect the xTAG-2 to the debug adapter.
3. Plug the xTAG-2 into your development system via USB.
4. Plug in the 12V power adapter and connect it to the sliceKIT core board.
5. In xTIMEcomposer, right-click on the binary within the app_daisy_chain/bin folder of the project.
6. Choose Flash As > Flash Configurations.
7. Double click xCORE Application in the left panel.
8. Choose hardware in Device options and select the relevant xTAG-2 adapter.
9. Click on Apply if configuration has changed.
10. Click on Flash. Once completed, disconnect the power from the sliceKIT core board.
11. Repeat steps 1 through 8 for the second sliceKIT.

XK-SK-AVB-DC

Refer to Figure 1 for the correct setup of the I/O sliceCARDs to the sliceKIT core boards.

1. The Ethernet sliceCARDs (XA-SK-E100) must be inserted into the slots denoted by the Circle and Square symbols.
2. The audio sliceCARD (XA-SK-AUDIO-PLL) must be inserted into the slot denoted by the Triangle symbol.
3. Connect the two sliceKITs together using an Ethernet cable between either of the Ethernet ports.
4. Connect one of the remaining Ethernet ports to an AVB-capable Apple Mac running OS X 10.9 Mavericks.
5. Connect the provided 12V power supplies to the input power jacks of the boards and power them on.

All Apple Macs with a Thunderbolt port are AVB capable.

To enumerate and stream audio between a Mac and XMOS AVB-DC endpoints:

1. Install/upgrade to OS X Mavericks Version >=10.9
2. Connect the XMOS AVB daisy chain to the Mac via the Ethernet port or Thunderbolt Ethernet adapter.
3. Open the Audio MIDI Setup utility.
4. In the menu bar, select Window > Show Network Device Browser.
   

   

5. XMOS AVB-DC endpoints will enumerate in this list as AVB 4in/4out. Select the checkbox to the left of the entries to connect
   the devices. Pressing the Identify button will identify the particular device by lighting LED1 and LED2 on the audio sliceCARD.

   

6. On successful connection, the devices will appear as Audio Devices in the Audio MIDI Setup window.
7. The devices can be streamed to individually, aggregated as an 8in/8out device, or treated as a Multi-Output Device.
   Aggregate or Multi-Output devices can be created in the Audio MIDI Setup window by clicking on the plus in the bottom left corner.

   

8. Once created, an Aggregate or Multi-Output device can be configured to use the XMOS AVB-DC endpoints by selecting the ‘Use’ checkboxes
   beside the Audio Devices.

   

9. To enable audio streaming to/from a device, right click on the device in the left pane and select Use this device for sound input and
   Use this device for sound output.

   

10. Audio can now be played and recorded via the endpoints.

Note: Volume and sample rate control of AVB audio devices is not currently available via Audio MIDI Setup

The XMOS Audio Video Bridging Daisy Chain endpoint (AVB-DC) is a two-port Ethernet MAC relay implementation
that provides time-synchronized, low latency streaming services through IEEE 802 networks.

XMOS AVB-DC Key Features

802.1AS defines a Precision Timing Protocol based on the IEEE 1558v2 protocol. It allows every device connected to the network to share a common global clock. The protocol allows devices to have a synchronized view of this clock to within microseconds of each other, aiding media stream clock recovery to phase align audio clocks.

The IEEE 802.1AS-2011 standard document
is available to download free of charge via the IEEE Get Program.

802.1Qav defines a standard for buffering and forwarding of traffic through the network using particular flow control algorithms. It gives predictable latency control on media streams flowing through the network.

The XMOS AVB solution implements the requirements for endpoints defined by 802.1Qav. This is done by traffic flow control in the transmit arbiter of the Ethernet MAC component.

The 802.1Qav specification is available as a section in the IEEE 802.1Q-2011 standard document
and is available to download free of charge via the IEEE Get Program.

802.1Qat defines a stream reservation protocol that provides end-to-end reservation of bandwidth across an AVB network.

The 802.1Qat specification is available as a section in the IEEE 802.1Q-2011 standard document
.

IEC 61883-6 defines an audio data format that is contained in IEEE 1722 streams. The XMOS AVB solution uses IEC 61883-6 to convey audio sample streams.

The IEC 61883-6:2005 standard document
is available for purchase from the IEC website.

IEEE 1722 defines an encapsulation protocol to transport audio streams over Ethernet. It is complementary to the AVB standards and in particular allows timestamping of a stream based on the 802.1AS global clock.

The XMOS AVB solution handles both transmission and receipt of audio streams using IEEE 1722. In addition it can use the 802.1AS timestamps to accurately recover the audio master clock from an input stream.

The IEEE 1722-2011 standard document
is available for purchase from the IEEE website.

IEEE 1722.1 is a system control protocol, used for device discovery, connection management and enumeration and control of parameters exposed by the AVB endpoints.

The IEEE 1722.1-2013 standard document
is available for purchase from the IEEE website.

An endpoint consists of five main interacting components:

• The Ethernet MAC
• The Precision Timing Protocol (PTP) engine
• Audio streaming components
• The media clock server
• Configuration and other application components

The following diagram shows the overall structure of an XMOS AVB endpoint.

The MAC component provides two-port Ethernet connectivity to the AVB-DC
solution. To use the component, two Ethernet PHYs must be attached
to the xCORE ports via MII.

The XMOS Ethernet MAC component supports two features that are necessary to
implement AVB standards with precise timing and quality constraints:

• Timestamping – allows receipt and transmission of Ethernet frames to be timestamped with respect to a clock (for example a 100 MHz reference clock can provide a resolution of 10 ns).
• Time sensitive traffic shaping – allows traffic bandwidth to be reserved and shaped on egress to provide a steady and guaranteed flow of outgoing media stream packets. The implementation provides flow control to satisfy the requirements of an AVB endpoint as specified in the IEEE 802.1Qav standard.

The two-port 100 Mbps component consists of seven logcial cores, each
running at 50 MIPS or more, that must be run on the same tile. These logcial cores handle both the receipt and transmission of
Ethernet frames. The MAC component can be linked via channels to other components/logcial cores in the system. Each link can set a filter to
control which packets are conveyed to it via that channel.

All configuration of the channel is managed by a client C/XC API, which
configures and registers the filters. Details of the API used to
configure MAC channels can be found in the Ethernet MAC component documentation
. This API is used for direct (layer-2) access to the
MAC. For AVB applications it is more likely that interaction with the
Ethernet stack will be via the main AVB API (see Section
AVB API
).

1722 packet routing

The Precision Timing Protocol (PTP) component enables a system with a
notion of global time on a network. The component implements the IEEE
802.1AS protocol. It allows synchronization of the
presentation and playback rate of media streams across a network.

The timing component consists of two logcial cores. It connects to the Ethernet MAC component and provides channel ends for clients to query for timing information. The component interprets PTP packets from the MAC and maintains a notion of global time. The maintenance of global time requires no application interaction with the component.

The PTP component can be configured at runtime to be a potential PTP grandmaster or a PTP slave only. If the component is configured as a grandmaster, it supplies a clock source to the network. If the network has several grandmasters, the potential grandmasters negotiate between themselves to select a single grandmaster. Once a single grandmaster is selected, all units on the network synchronize a global time from this source and the other grandmasters stop providing timing information. Depending on the intermediate network, this synchronization can be to sub-microsecond level resolution.

Client tasks connect to the timing component via channels. The relationship between the local reference counter and global time is maintained across this channel, allowing a client to timestamp with a local timer very accurately and then convert it to global time, giving highly accurate global timestamps.

Client tasks can communicate with the server using the API described
in Section PTP client API
.

• The PTP system in the endpoint is self-configuring, it runs
  automatically and gives each endpoint an accurate notion of a global clock.
• The global clock is not the same as the audio word clock, although it can be used to derive it. An audio stream may be at a rate that is independent of the
  PTP clock but will contain timestamps that use the global PTP clock
  domain as a reference domain.

AVB streams, channels, talkers and listeners

Internal routing, media FIFOs

As described in the previous section, an IEEE 1722 audio stream may
consist of many channels. These channels need to be routed to
particular audio I/Os on the endpoint. To achieve maximum flexibility
the XMOS design uses intermediate media FIFOs to route
audio. Each FIFO contains a single channel of audio.

The above figure shows the breakdown of 1722 streams
into local FIFOs. The figure shows four points where
transitions to and from media FIFOs occur. For audio being received by
an endpoint:

1. When a 1722 stream is received, its channels are mapped to output
   media FIFOs. This mapping can be configured
   dynamically so that it can be changed at runtime by the configuration component.
2. The digital hardware interface maps media FIFOs to audio
   outputs. This mapping is fixed and is configured statically in the
   software.

For audio being transmitted by an endpoint:

1. The digital hardware interface maps digital audio inputs to
   local media FIFOs. This mapping is fixed and cannot be changed
   at runtime.
2. Several input FIFOs can be combined into a 1722 stream. This
   mapping is dynamic.

The configuration of the mappings is handled through the API describe
in AVB API
.

Media FIFOs use shared memory to move data between tasks, thus the
filling and emptying of the FIFO must be on the same tile.

Talker units

A talker unit consists of one logcial core which creates IEEE 1722 packets and passes the audio samples onto the MAC. Audio
samples are passed to this component via input media FIFOs.
Samples are pushed into this FIFO from a different task implementing the audio hardware interface. The Talker task removes the samples and combines them into IEEE 1722 Ethernet packets to be transmitted via the MAC component.

When the packets are created the timestamps are converted to the time domain of the global clock provided by the PTP component, and a fixed offset is added to the timestamps to provide the presentation time of the samples (i.e the time at which the sample should be played by a Listener).

A system may have several Talker units. However, since samples are
passed via a shared memory interface a talker can only combine input FIFOs
that are created on the same tile as the talker. The instantiating of
talker units is performed via the API described in Section
Component tasks and functions
. Once the talker unit starts, it registers
with the main control task and is controlled via the main AVB API
described in Section AVB API
.

Listener units

A Listener unit takes IEEE 1722 packets from the MAC
and converts them into a sample stream to be fed into a media FIFO.
Each audio Listener component can listen to several IEEE 1722
streams.

A system may have several Listener units. The instantiating of
Listener units is performed via the API described in Section
Component tasks and functions
. Once the Listener unit starts, it registers
with the main control task and is controlled via the main AVB API
described in Section AVB API
.

Media FIFOs to XC channels

Audio hardware interfaces

A media clock controls the rate at which information is passed to an
external media playing device. For example, an audio word clock that
governs the rate at which samples should be passed to an audio CODEC.
An XMOS AVB endpoint can keep track of several media clocks.

A media clock can be synchronized to one of two sources:

• An incoming clock signal on a port.
• The word clock of a remote endpoint, derived from an incoming IEEE 1722 audio stream.

A hardware interface can be tied to a particular media
clock, allowing the media output from the XMOS device to be
synchronized with other devices on the network.

All media clocks are maintained by the media clock server
component. This component maintains
the current state of all the media clocks in the system. It then
periodically updates other components with clock change information to
keep the system synchronized. The set of media clocks is determined by
an array passed to the server at startup.

The media clock server component also receives information from the
audio listener component to track timing information of incoming
IEEE 1722 streams. It then sends control information back to
ensure the listening component honors the presentation time of the
incoming stream.

Multiple media clocks require multiple hardware PLLs. AVB-DC hardware supports a single media clock.

Driving an external clock generator

The control task

1722.1

This document covers the hardware design of the sliceKIT Modular Development System, consisting of the xCORE-Analog Core Board, sliceCARDs and XSYS adaptor.

The Core Board contains a fully pinned out 16-core xCORE Processor, with its GPIOs connected to four expansion connectors (termed Slots) to interface with expansion cards called sliceCARDs which plug into the slots. The Core Board also contains all circuitry necessary for operating and debugging the XMOS system. Multiple sliceKIT Core Boards can be interconnected to form a multi XMOS device system with dual 5-bit xCONNECT Links being present between the boards.

Each of the four slots has a specific label – Star, Triangle, Square and Circle, printed on the Core Board silkscreen. Triangle and Circle sliceCARDs contain 24 xCORE I/Os and Star and Square sliceCARDs 20 xCORE I/Os (usable as GPIO or two 5-wire XMOS links). The label denotes which sliceCARDs are compatible with which Core Board Slots. The sliceCARDs are also marked with one or more of these labels to identify the slot type(s) they function correctly with.

In addition to the four standard sliceCARD slots there is a Mixed Signal slot, labelled A, this slot has access to the 8 ADC channels available on the XS1-A16 device, along with 4 xCORE I/Os and the wake pin. The xCORE I/Os available on the Mixed Signal slot overlap with the Star slot, meaning that if the Mixed Signal I/Os are used then a sliceCARD used in the Star slot may not function.

The final type of connector is on the bottom left of the Core Board and is marked with a hollow square symbol with an X through it. This is for connecting multiple Core Boards together to form systems of 32 logical cores or more. It is termed the chain slot.

All Slots are 36 pin PCI express style connectors in either socket or edge finger (plug) types.

Star, Triangle and Mixed Signal Slots are pinned out from Tile 0 of the XS1-A16 device and the Circle and Square Slots from Tile 1.

Additional xCORE-Analog or xCORE General Purpose sliceKIT Core Boards can be connected to the first board’s Chain slot via the second board’s Square Slot to add extra processing capability and I/O through extra Slice Cards. The first such board is termed the Master, the remaining boards as Slaves. When there is only one board, it is the Master.

For debugging, an XSYS adaptor board is connected to the Chain Connector of the Master Board to allow connection of an xTAG debug adapter to provide a debug link from a USB host.

The Core Board is powered by a 12V external power supply.

Power input to the sliceKIT Core Board is via a standard barrel jack connector. A standard 12V external power supply should be used to power the board. Each Core Board requires its own 12V supply. This input supply is used to generate the main 5V board supply via a DC-DC converter.

The 5V board supply is then fed to all the Slot connectors as well as powering the Core Board itself. A 3V3 supply is generated by DC-DC converters from the 5V main supply.

The XS1-A16 device uses integrated DC-DC converters to generate the 1V8 and 1V0 supplies required by the device.

The supplies are sequenced to ensure the power up sequence is 5V then 3V3. When the 3V3 supply is good then the system will be released from reset.

The Core Board provides 3V3 and 5V at 0.25A each for a total of approximately 2W per slice.

Debug of the system is via the XSYS adapter board connected to the Chain Connector.

The JTAG signals are connected as shown below.

Presence detect signals are present on both the Chain Connector and Square Slot connectors to allow detection of a connected board and subsequent automatic switching of the JTAG chain. In a system of multiple Core Boards, the Master is the source of the JTAG chain so the system can only be debugged from the master. Other boards will see no devices in the JTAG chain.

The use of xSCOPE is covered in the xCONNECT Links section – see Section xCONNECT Links
. The xSCOPE xCONNECT link can be either enabled or disabled via a switch on the XSYS adapter board.

Master Core Boards boot from SPI flash, while slave Core Boards boot from xCONNECT link XLB from the next connected Core Board.

To allow re-use of the SPI boot pins (ports 1A, 1B, 1C, 1D) as signal I/O pins for the Star, Triangle and A slot, a latched bus switch is used which connects the xCORE SPI pins to either the SPI Flash or to the Slice Card Slots. The switch is controlled by X0D42 and X0D43 (P8D6 and P8D7 on Tile 0: on the Triangle slot). Once the device has booted X0D43 is used to enable or disable the SPI interface, X0D42 should then transition from low to high to latch the selection. The SPI selection state is then maintained until the system is reset.

Once this sequence is completed the selection has been latched, therefore X0D42 and X0D43 return to performing their normal functions in the Triangle slot.

If the SPI is not disabled, then Slice Cards in the Star, Triangle or A slots may not function as expected. If there are no Slice Cards in the Star, Triangle or A slot, then it does not matter whether the SPI has been disabled or not. Therefore, applications which require runtime access to the SPI flash should either leave the Star, Triangle and A slots unpopulated or check to ensure that the Card which is in there will be unaffected by the operation of the Flash.

The xTAG debug system can use the boot mode select signal to force all devices in the chain (master and slave Core Boards) to boot from JTAG (don’t boot) for debug purposes.

If not in this mode, the devices will boot from SPI or xCONNECT link as appropriate.

The Chain Connector contains two 5-bit xCONNECT links, XLA and XLB, which can be used for chaining sliceKIT Core Boards together. The links from Tile 0 are connected to the Chain Connector and the Star Slot. The links from Tile 1 are connected to the Square Slot.

The only complication in this system is use of the xSCOPE 2-bit xCONNECT Link. This link overlaps a 4 bit port on the Star Slot connector so it would not be possible to use this for user I/O at the same time as xSCOPE.

To work around this, a switch is present on the XSYS adapter board to either enable or disable the xSCOPE xCONNECT Link.

When disabled, these pins are disconnected from the Chain Connector and are free for use on the Star Slot. When enabled they will work as an xCONNECT link and hence will appear on the relevant pins of the Star Slot.

It is recommended that if a sliceCARD is used in the Star Slot the xSCOPE switch is off on the XSYS Adaptor Card to ensure correct operation of the sliceCARD in the Star slot.

The whole system is held in reset until all power supplies are stable, and reset is connected to all Slice Cards so any circuitry on them can be reset.

It also indicates to the sliceCARDs that their power input is stable. The reset from the xTAG resets the whole system, if required for debugging.

There are two sources for the system clock: an on-board 25MHz oscillator or the CLK signal from the Chain Connector. The system clock source is selected automatically according to the presence signals on the Chain connector.

This means the system clock from a Master Core Board is fed automatically to all of the slave Core Boards so the whole system will operate synchronously.

The system clock is also fed to each of the sliceCARD Slots.

Each xCORE I/O signal is also available on a 0.1” header, next to the Slot that it is connected to.

These connections can be used to connect an oscilloscope or logic analyser, or for interconnection of signals for advanced development work.

The signals are identified on the silkscreen layer of the sliceKIT Core Board, the table below lists their relationship to the internal ports.

Testpoint Information

xCORE-Analog sliceKIT Hardware Manual Read More »

Anna Parlour

HR Director

Anna joined XMOS in 2022 and brings extensive experience in Human Resources having worked within rapidly expanding international organisations across a variety of sectors in pharmaceutical, communications and FMCG.

Anna is responsible for enabling XMOS to continue to be a great place to work. 

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Rohit Malhotra

Executive VP Global Sales & Business Development

Rohit is a semiconductor veteran with more than 33 years’ experience of working across applications, marketing, and sales with global companies. During this time, he has nurtured key relationships across the semiconductor industry. While passionate about work, in his spare time, Rohit enjoys cars, golf and gadgets. 

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US English commands

XS1-A16 Pin	Slot	PCIE	Function
X0D0	TRIANGLE	B2	P1A0
X0D1	STAR	A8	P1B0
	MIXED SIG	B15
	CHAIN	B10
X0D2	STAR	B6		P4A0	P8A0	P16A0	P32A20
	CHAIN	A7
X0D3	STAR	B7		P4A1	P8A1	P16A1	P32A21
	CHAIN	A6
X0D4	STAR	B9		P4B0	P8A2	P16A2	P32A22
	CHAIN	A11
X0D5	STAR	B11		P4B1	P8A3	P16A3	P32A23
	CHAIN	A9
X0D6	STAR	A9		P4B2	P8A4	P16A4	P32A24
	CHAIN	B11
X0D7	STAR	A11		P4B3	P8A5	P16A5	P32A25
	CHAIN	B9
X0D8	STAR	A6		P4A2	P8A6	P16A6	P32A26
	CHAIN	B7
X0D9	STAR	A7		P4A3	P8A7	P16A7	P32A27
	CHAIN	B6
X0D10	STAR	B10	P1C0
	MIXED SIG	B2
	CHAIN	A8
X0D11	TRIANGLE	B4	P1D0
X0D12	TRIANGLE	A3	P1E0
X0D13	STAR	A15	P1F0
	MIXED SIG	A3
	CHAIN	B15
X0D14	STAR	B12		P4C0	P8B0	P16A8

Spoken Command
Switch on the TV
Switch off the TV
Channel up
Channel down
Volume up
Volume down
Switch on the lights
Switch off the lights
Brightness up
Brightness down
Switch on the fan
Switch off the fan
Speed up the fan
Slow down the fan
Set higher temperature
Set lower temperature