28 #define XS3_VPU_VREG_WIDTH_BITS (256)
35 #define XS3_VPU_VREG_WIDTH_BYTES (XS3_VPU_VREG_WIDTH_BITS >> 3)
42 #define XS3_VPU_VREG_WIDTH_WORDS (XS3_VPU_VREG_WIDTH_BYTES >> 2)
110 VPU_INT8_ACC_SIZE = 32,
111 VPU_INT16_ACC_SIZE = 32,
112 VPU_INT32_ACC_SIZE = 40,
122 VPU_INT8_ACC_VR_BITS = 16,
123 VPU_INT16_ACC_VR_BITS = 16,
124 VPU_INT32_ACC_VR_BITS = 32,
133 VPU_INT8_ACC_VR_MASK = 0xFFFF,
134 VPU_INT16_ACC_VR_MASK = 0xFFFF,
135 VPU_INT32_ACC_VR_MASK = 0xFFFFFFFF,
180 VPU_INT8_EPV_LOG2 = 5,
181 VPU_INT16_EPV_LOG2 = 4,
182 VPU_INT32_EPV_LOG2 = 3,
194 VPU_INT8_ACC_PERIOD = 16,
195 VPU_INT16_ACC_PERIOD = 16,
196 VPU_INT32_ACC_PERIOD = 8,
205 VPU_INT8_ACC_PERIOD_LOG2 = 4,
206 VPU_INT16_ACC_PERIOD_LOG2 = 4,
207 VPU_INT32_ACC_PERIOD_LOG2 = 3,
218 VPU_INT8_VLMACC_ELMS = 16,
219 VPU_INT16_VLMACC_ELMS = 16,
220 VPU_INT32_VLMACC_ELMS = 8,
229 VPU_INT8_VLMACC_ELMS_LOG2 = 4,
230 VPU_INT16_VLMACC_ELMS_LOG2 = 4,
231 VPU_INT32_VLMACC_ELMS_LOG2 = 3,
int32_t vpu_int8_acc_t
Definition: xs3_vpu_info.h:143
int32_t vpu_int16_acc_t
Definition: xs3_vpu_info.h:150
int64_t vpu_int32_acc_t
Definition: xs3_vpu_info.h:157
@ VSETCTRL_TYPE_INT8
Definition: xs3_vpu_info.h:55
@ VSETCTRL_TYPE_INT32
Definition: xs3_vpu_info.h:51
@ VSETCTRL_TYPE_INT16
Definition: xs3_vpu_info.h:53
@ VPU_INT32_MAX
Definition: xs3_vpu_info.h:89
@ VPU_INT40_MAX
Definition: xs3_vpu_info.h:94
@ VPU_INT40_MIN
Definition: xs3_vpu_info.h:96
@ VPU_INT32_MIN
Definition: xs3_vpu_info.h:91
@ VPU_INT8_MAX
Definition: xs3_vpu_info.h:79
@ VPU_INT16_MIN
Definition: xs3_vpu_info.h:86
@ VPU_INT8_MIN
Definition: xs3_vpu_info.h:81
@ VPU_INT16_MAX
Definition: xs3_vpu_info.h:84
@ VEC_SHL
Definition: xs3_vpu_info.h:67
@ VEC_SHR
Definition: xs3_vpu_info.h:69
@ VEC_SH0
Definition: xs3_vpu_info.h:65