XCORE SDK
XCORE Software Development Kit
modules
rtos
modules
drivers
wifi
sl_wf200
thirdparty
wfx-fullMAC-driver
wfx_fmac_driver
firmware
sl_wfx_registers.h
1
/**************************************************************************/
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#ifndef SL_WFX_REGISTERS_H
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#define SL_WFX_REGISTERS_H
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#include <stdint.h>
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#define SYS_BASE_ADDR_SILICON (0)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
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#define SL_WFX_APB(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
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/* Download control area */
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#define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
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#define DOWNLOAD_FIFO_SIZE (0x00008000)
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#define DOWNLOAD_CTRL_DATA_DWORDS (32 - 6)
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#define DOWNLOAD_CTRL_OFFSET (0x0900C000)
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#define DOWNLOAD_IMAGE_SIZE_REG (DOWNLOAD_CTRL_OFFSET + 0)
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#define DOWNLOAD_PUT_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
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#define DOWNLOAD_TRACE_PC_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
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#define DOWNLOAD_GET_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
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#define DOWNLOAD_STATUS_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
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#define DOWNLOAD_DEBUG_DATA_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
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#define DOWNLOAD_DEBUG_DATA_LEN (108)
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#define DOWNLOAD_BLOCK_SIZE (1024)
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#define ADDR_DWL_CTRL_AREA 0x0900C000
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#define FW_KEYSET_SIZE 8
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#define FW_SIGNATURE_SIZE 64
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#define FW_HASH_SIZE 8
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#define ADDR_DWL_CTRL_AREA_IMAGE_SIZE (ADDR_DWL_CTRL_AREA + 0)
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#define ADDR_DWL_CTRL_AREA_PUT (ADDR_DWL_CTRL_AREA + 4)
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#define ADDR_DWL_CTRL_AREA_GET (ADDR_DWL_CTRL_AREA + 8)
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#define ADDR_DWL_CTRL_AREA_HOST_STATUS (ADDR_DWL_CTRL_AREA + 12)
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#define ADDR_DWL_CTRL_AREA_NCP_STATUS (ADDR_DWL_CTRL_AREA + 16)
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#define ADDR_DWL_CTRL_AREA_SIGNATURE (ADDR_DWL_CTRL_AREA + 20)
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#define ADDR_DWL_CTRL_AREA_FW_HASH (ADDR_DWL_CTRL_AREA_SIGNATURE + FW_SIGNATURE_SIZE)
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#define ADDR_DWL_CTRL_AREA_FW_VERSION (ADDR_DWL_CTRL_AREA_FW_HASH + FW_HASH_SIZE)
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#define HOST_STATE_UNDEF 0xFFFFFFFF
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#define HOST_STATE_NOT_READY 0x12345678
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#define HOST_STATE_READY 0x87654321
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#define HOST_STATE_HOST_INFO_READ 0xA753BD99
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#define HOST_STATE_UPLOAD_PENDING 0xABCDDCBA
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#define HOST_STATE_UPLOAD_COMPLETE 0xD4C64A99
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#define HOST_STATE_OK_TO_JUMP 0x174FC882
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#define NCP_STATE_UNDEF 0xFFFFFFFF
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#define NCP_STATE_NOT_READY 0x12345678
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#define NCP_STATE_INFO_READY 0xBD53EF99
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#define NCP_STATE_READY 0x87654321
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#define NCP_STATE_DOWNLOAD_PENDING 0xABCDDCBA
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#define NCP_STATE_DOWNLOAD_COMPLETE 0xCAFEFECA
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#define NCP_STATE_AUTH_OK 0xD4C64A99
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#define NCP_STATE_AUTH_FAIL 0x174FC882
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#define NCP_STATE_PUB_KEY_RDY 0x7AB41D19
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#define ADDR_DOWNLOAD_FIFO_BASE 0x09004000
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#define ADDR_DOWNLOAD_FIFO_END 0x0900C000
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#define ADDR_SHARED_RAM_DEBUG_AREA 0x09002000
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#define BIT(n) (1 << (n))
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/* Control register bit set */
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#define SL_WFX_CONT_REGISTER_SIZE (0x02)
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#define SL_WFX_CONT_NEXT_LEN_MASK (0x0FFF)
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#define SL_WFX_CONT_WUP_BIT (BIT(12))
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#define SL_WFX_CONT_RDY_BIT (BIT(13))
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#define SL_WFX_CONT_FRAME_TYPE_INFO (BIT(14) | BIT(15))
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#define SL_WFX_CONT_FRAME_TYPE_OFFSET (0x0E)
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/* Config register bit set */
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#define SL_WFX_CONFIG_ERROR_CSN_FRAME (BIT(0))
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#define SL_WFX_CONFIG_ERROR_READ_UNDERRUN (BIT(1))
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#define SL_WFX_CONFIG_ERROR_READ_LESS (BIT(2))
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#define SL_WFX_CONFIG_FRAME_READ_ENTRY (BIT(3))
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#define SL_WFX_CONFIG_ERROR_SEND_OVERRUN (BIT(4))
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#define SL_WFX_CONFIG_ERROR_SEND_LARGE (BIT(5))
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#define SL_WFX_CONFIG_ERROR_SEND_ENTRY (BIT(6))
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#define SL_WFX_CONFIG_CSN_FRAME_BIT (BIT(7))
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#define SL_WFX_CONFIG_ERROR_MASK (0x000F)
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/* Word mode config */
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#define SL_WFX_CONFIG_WORD_MODE_BITS (BIT(8) | BIT(9))
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#define SL_WFX_CONFIG_WORD_MODE_1 (BIT(8))
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#define SL_WFX_CONFIG_WORD_MODE_2 (BIT(9))
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/* QueueM */
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#define SL_WFX_CONFIG_ACCESS_MODE_BIT (BIT(10))
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/* AHB bus */
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#define SL_WFX_CONFIG_AHB_PRFETCH_BIT (BIT(11))
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#define SL_WFX_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
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/* APB bus */
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#define SL_WFX_CONFIG_PRFETCH_BIT (BIT(13))
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/* CPU reset */
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#define SL_WFX_CONFIG_CPU_RESET_BIT (BIT(14))
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#define SL_WFX_CONFIG_CLEAR_INT_BIT (BIT(15))
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/* For WF200 the IRQ Enable and Ready Bits are in CONFIG register */
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#define SL_WFX_CONFIG_DATA_IRQ_ENABLE (BIT(16))
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#define SL_WFX_CONFIG_WUP_IRQ_ENABLE (BIT(17))
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#define SL_WFX_CONFIG_DATA_WUP_ENABLE (BIT(16) | BIT(17))
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/* Revision and type */
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#define SL_WFX_CONFIG_REVISION_OFFSET (0x18)
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#define SL_WFX_CONFIG_REVISION_MASK (0x7)
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#define SL_WFX_CONFIG_TYPE_OFFSET (0x1F)
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#define SL_WFX_CONFIG_TYPE_MASK (0x1)
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/* SDIO CCCR register offsets */
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#define SL_WFX_SDIO_CCCR_IO_QUEUE_ENABLE (0x02)
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#define SL_WFX_SDIO_CCCR_IRQ_ENABLE (0x04)
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#define SL_WFX_SDIO_CCCR_BUS_INTERFACE_CONTROL (0x07)
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#define SL_WFX_SDIO_CCCR_HIGH_SPEED_ENABLE (0x13)
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/* SDIO FBR1 register offsets */
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#define SL_WFX_SDIO_FBR1_BLOCK_SIZE_LSB (0x110)
/* Function 1 16-bit block size LSB */
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#define SL_WFX_SDIO_FBR1_BLOCK_SIZE_MSB (0x111)
/* Function 1 16-bit block size MSB */
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#define FW_VERSION_VALUE 0x00000001
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#endif
// SL_WFX_REGISTERS_H
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