XCORE SDK
XCORE Software Development Kit
sl_wfx_registers.h
1 /**************************************************************************/
17 #ifndef SL_WFX_REGISTERS_H
18 #define SL_WFX_REGISTERS_H
19 
20 #include <stdint.h>
21 
22 #define SYS_BASE_ADDR_SILICON (0)
23 #define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
24 #define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
25 
26 #define SL_WFX_APB(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
27 
28 /* Download control area */
29 #define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
30 #define DOWNLOAD_FIFO_SIZE (0x00008000)
31 
32 #define DOWNLOAD_CTRL_DATA_DWORDS (32 - 6)
33 
34 #define DOWNLOAD_CTRL_OFFSET (0x0900C000)
35 #define DOWNLOAD_IMAGE_SIZE_REG (DOWNLOAD_CTRL_OFFSET + 0)
36 #define DOWNLOAD_PUT_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
37 #define DOWNLOAD_TRACE_PC_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
38 #define DOWNLOAD_GET_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
39 #define DOWNLOAD_STATUS_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
40 #define DOWNLOAD_DEBUG_DATA_REG (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
41 #define DOWNLOAD_DEBUG_DATA_LEN (108)
42 
43 #define DOWNLOAD_BLOCK_SIZE (1024)
44 
45 #define ADDR_DWL_CTRL_AREA 0x0900C000
46 #define FW_KEYSET_SIZE 8
47 #define FW_SIGNATURE_SIZE 64
48 #define FW_HASH_SIZE 8
49 #define ADDR_DWL_CTRL_AREA_IMAGE_SIZE (ADDR_DWL_CTRL_AREA + 0)
50 #define ADDR_DWL_CTRL_AREA_PUT (ADDR_DWL_CTRL_AREA + 4)
51 #define ADDR_DWL_CTRL_AREA_GET (ADDR_DWL_CTRL_AREA + 8)
52 #define ADDR_DWL_CTRL_AREA_HOST_STATUS (ADDR_DWL_CTRL_AREA + 12)
53 #define ADDR_DWL_CTRL_AREA_NCP_STATUS (ADDR_DWL_CTRL_AREA + 16)
54 #define ADDR_DWL_CTRL_AREA_SIGNATURE (ADDR_DWL_CTRL_AREA + 20)
55 #define ADDR_DWL_CTRL_AREA_FW_HASH (ADDR_DWL_CTRL_AREA_SIGNATURE + FW_SIGNATURE_SIZE)
56 #define ADDR_DWL_CTRL_AREA_FW_VERSION (ADDR_DWL_CTRL_AREA_FW_HASH + FW_HASH_SIZE)
57 
58 #define HOST_STATE_UNDEF 0xFFFFFFFF
59 #define HOST_STATE_NOT_READY 0x12345678
60 #define HOST_STATE_READY 0x87654321
61 #define HOST_STATE_HOST_INFO_READ 0xA753BD99
62 #define HOST_STATE_UPLOAD_PENDING 0xABCDDCBA
63 #define HOST_STATE_UPLOAD_COMPLETE 0xD4C64A99
64 #define HOST_STATE_OK_TO_JUMP 0x174FC882
65 
66 #define NCP_STATE_UNDEF 0xFFFFFFFF
67 #define NCP_STATE_NOT_READY 0x12345678
68 #define NCP_STATE_INFO_READY 0xBD53EF99
69 #define NCP_STATE_READY 0x87654321
70 #define NCP_STATE_DOWNLOAD_PENDING 0xABCDDCBA
71 #define NCP_STATE_DOWNLOAD_COMPLETE 0xCAFEFECA
72 #define NCP_STATE_AUTH_OK 0xD4C64A99
73 #define NCP_STATE_AUTH_FAIL 0x174FC882
74 #define NCP_STATE_PUB_KEY_RDY 0x7AB41D19
75 
76 #define ADDR_DOWNLOAD_FIFO_BASE 0x09004000
77 #define ADDR_DOWNLOAD_FIFO_END 0x0900C000
78 #define ADDR_SHARED_RAM_DEBUG_AREA 0x09002000
79 
80 #define BIT(n) (1 << (n))
81 
82 /* Control register bit set */
83 #define SL_WFX_CONT_REGISTER_SIZE (0x02)
84 #define SL_WFX_CONT_NEXT_LEN_MASK (0x0FFF)
85 #define SL_WFX_CONT_WUP_BIT (BIT(12))
86 #define SL_WFX_CONT_RDY_BIT (BIT(13))
87 #define SL_WFX_CONT_FRAME_TYPE_INFO (BIT(14) | BIT(15))
88 #define SL_WFX_CONT_FRAME_TYPE_OFFSET (0x0E)
89 
90 /* Config register bit set */
91 #define SL_WFX_CONFIG_ERROR_CSN_FRAME (BIT(0))
92 #define SL_WFX_CONFIG_ERROR_READ_UNDERRUN (BIT(1))
93 #define SL_WFX_CONFIG_ERROR_READ_LESS (BIT(2))
94 #define SL_WFX_CONFIG_FRAME_READ_ENTRY (BIT(3))
95 #define SL_WFX_CONFIG_ERROR_SEND_OVERRUN (BIT(4))
96 #define SL_WFX_CONFIG_ERROR_SEND_LARGE (BIT(5))
97 #define SL_WFX_CONFIG_ERROR_SEND_ENTRY (BIT(6))
98 #define SL_WFX_CONFIG_CSN_FRAME_BIT (BIT(7))
99 #define SL_WFX_CONFIG_ERROR_MASK (0x000F)
100 /* Word mode config */
101 #define SL_WFX_CONFIG_WORD_MODE_BITS (BIT(8) | BIT(9))
102 #define SL_WFX_CONFIG_WORD_MODE_1 (BIT(8))
103 #define SL_WFX_CONFIG_WORD_MODE_2 (BIT(9))
104 /* QueueM */
105 #define SL_WFX_CONFIG_ACCESS_MODE_BIT (BIT(10))
106 /* AHB bus */
107 #define SL_WFX_CONFIG_AHB_PRFETCH_BIT (BIT(11))
108 #define SL_WFX_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
109 /* APB bus */
110 #define SL_WFX_CONFIG_PRFETCH_BIT (BIT(13))
111 /* CPU reset */
112 #define SL_WFX_CONFIG_CPU_RESET_BIT (BIT(14))
113 #define SL_WFX_CONFIG_CLEAR_INT_BIT (BIT(15))
114 /* For WF200 the IRQ Enable and Ready Bits are in CONFIG register */
115 #define SL_WFX_CONFIG_DATA_IRQ_ENABLE (BIT(16))
116 #define SL_WFX_CONFIG_WUP_IRQ_ENABLE (BIT(17))
117 #define SL_WFX_CONFIG_DATA_WUP_ENABLE (BIT(16) | BIT(17))
118 /* Revision and type */
119 #define SL_WFX_CONFIG_REVISION_OFFSET (0x18)
120 #define SL_WFX_CONFIG_REVISION_MASK (0x7)
121 #define SL_WFX_CONFIG_TYPE_OFFSET (0x1F)
122 #define SL_WFX_CONFIG_TYPE_MASK (0x1)
123 
124 /* SDIO CCCR register offsets */
125 #define SL_WFX_SDIO_CCCR_IO_QUEUE_ENABLE (0x02)
126 #define SL_WFX_SDIO_CCCR_IRQ_ENABLE (0x04)
127 #define SL_WFX_SDIO_CCCR_BUS_INTERFACE_CONTROL (0x07)
128 #define SL_WFX_SDIO_CCCR_HIGH_SPEED_ENABLE (0x13)
129 
130 /* SDIO FBR1 register offsets */
131 #define SL_WFX_SDIO_FBR1_BLOCK_SIZE_LSB (0x110) /* Function 1 16-bit block size LSB */
132 #define SL_WFX_SDIO_FBR1_BLOCK_SIZE_MSB (0x111) /* Function 1 16-bit block size MSB */
133 
134 #define FW_VERSION_VALUE 0x00000001
135 
136 #endif // SL_WFX_REGISTERS_H