XCORE SDK
XCORE Software Development Kit
Public Attributes | List of all members
qspi_io_ctx_t Struct Reference

#include <qspi_io.h>

Public Attributes

xclock_t clock_block
 
port_t cs_port
 
port_t sclk_port
 
port_t sio_port
 
int full_speed_clk_divisor
 
int spi_read_clk_divisor
 
uint32_t full_speed_sclk_sample_delay
 
uint32_t spi_read_sclk_sample_delay
 
qspi_io_sample_edge_t full_speed_sclk_sample_edge
 
qspi_io_sample_edge_t spi_read_sclk_sample_edge
 
uint32_t full_speed_sio_pad_delay
 
uint32_t spi_read_sio_pad_delay
 
size_t transaction_length
 
uint32_t transaction_start
 
uint32_t sample_delay
 
uint32_t sample_edge
 
uint32_t sio_pad_delay
 
uint32_t sio_drive
 

Detailed Description

The context structure that must be passed to each of the qspi_io functions. Several of the members in this structure must be set by the application prior to calling either qspi_io_init() or qspi_io_start_transaction().

Member Data Documentation

◆ clock_block

xclock_t qspi_io_ctx_t::clock_block

The clock block to use for the qspi_io interface.

This must be set prior to calling qspi_io_init() and must not change.

◆ cs_port

port_t qspi_io_ctx_t::cs_port

The chip select port. MUST be a 1-bit port.

This must be set prior to calling qspi_io_init() and must not change.

◆ full_speed_clk_divisor

int qspi_io_ctx_t::full_speed_clk_divisor

The divisor to use for QSPI reads and writes as well as SPI writes.

The frequency of SCLK will be set to: (F_src) / (2 * full_speed_clk_divisor) Where F_src is the frequency of the source clock specified by the source_clock parameter of qspi_io_init().

This must be set prior to the beginning of a transaction and may change between transactions.

◆ full_speed_sclk_sample_delay

uint32_t qspi_io_ctx_t::full_speed_sclk_sample_delay

Number of SCLK cycles to delay the sampling of SIO on input during a full speed transaction.

Usually either 0 or 1 depending on the SCLK frequency.

This must be set prior to the beginning of a transaction and may change between transactions.

◆ full_speed_sclk_sample_edge

qspi_io_sample_edge_t qspi_io_ctx_t::full_speed_sclk_sample_edge

The SCLK edge to sample the SIO input on during a full speed transaction. May be either qspi_io_sample_edge_rising or qspi_io_sample_edge_falling.

This must be set prior to the beginning of a transaction and may change between transactions.

◆ full_speed_sio_pad_delay

uint32_t qspi_io_ctx_t::full_speed_sio_pad_delay

Number of core clock cycles to delay sampling the SIO pads during a full speed transaction. This allows for more fine grained adjustment of sampling time. The value may be between 0 and 5.

This must be set prior to the beginning of a transaction and may change between transactions.

◆ sclk_port

port_t qspi_io_ctx_t::sclk_port

The SCLK port. MUST be a 1-bit port.

This must be set prior to calling qspi_io_init() and must not change.

◆ sio_port

port_t qspi_io_ctx_t::sio_port

The SIO port. MUST be a 4-bit port.

This must be set prior to calling qspi_io_init() and must not change.

◆ spi_read_clk_divisor

int qspi_io_ctx_t::spi_read_clk_divisor

The divisor to use for the clock when performing a SPI read. This may need to be slower than the clock used for writes and QSPI reads. This is because a small handful of instructions must execute to turn the SIO port around from output to input and they must execute within a single SCLK period during a SPI read. QSPI reads have dummy cycles where these instructions may execute which allows for a higher clock frequency.

The frequency of SCLK will be set to: (F_src) / (2 * spi_read_clk_divisor) Where F_src is the frequency of the source clock specified by the source_clock parameter of qspi_io_init().

This must be set prior to the beginning of a transaction and may change between transactions.

◆ spi_read_sclk_sample_delay

uint32_t qspi_io_ctx_t::spi_read_sclk_sample_delay

Number of SCLK cycles to delay the sampling of SIO on input during a SPI read transaction.

Usually either 0 or 1 depending on the SCLK frequency.

This must be set prior to the beginning of a transaction and may change between transactions.

◆ spi_read_sclk_sample_edge

qspi_io_sample_edge_t qspi_io_ctx_t::spi_read_sclk_sample_edge

The SCLK edge to sample the SIO input on during a SPI read transaction. May be either qspi_io_sample_edge_rising or qspi_io_sample_edge_falling.

This must be set prior to the beginning of a transaction and may change between transactions.

◆ spi_read_sio_pad_delay

uint32_t qspi_io_ctx_t::spi_read_sio_pad_delay

Number of core clock cycles to delay sampling the SIO pads during a SPI read transaction. This allows for more fine grained adjustment of sampling time. The value may be between 0 and 5.

This must be set prior to the beginning of a transaction and may change between transactions.


The documentation for this struct was generated from the following file: