XCORE SDK
XCORE Software Development Kit
Macros | Typedefs | Enumerations
XS3 VPU Info

Macros

#define XS3_VPU_VREG_WIDTH_BITS   (256)
 
#define XS3_VPU_VREG_WIDTH_BYTES   (XS3_VPU_VREG_WIDTH_BITS >> 3)
 
#define XS3_VPU_VREG_WIDTH_WORDS   (XS3_VPU_VREG_WIDTH_BYTES >> 2)
 

Typedefs

typedef int32_t vpu_int8_acc_t
 
typedef int32_t vpu_int16_acc_t
 
typedef int64_t vpu_int32_acc_t
 

Enumerations

enum  { VSETCTRL_TYPE_INT32 = 0 , VSETCTRL_TYPE_INT16 = 1 , VSETCTRL_TYPE_INT8 = 2 }
 
enum  { VEC_SH0 = 0 , VEC_SHL = 1 , VEC_SHR = 2 }
 
enum  {
  VPU_INT8_MAX = 0x7F , VPU_INT8_MIN = -0x7F , VPU_INT16_MAX = 0x7FFF , VPU_INT16_MIN = -0x7FFF ,
  VPU_INT32_MAX = 0x7FFFFFFF , VPU_INT32_MIN = -0x7FFFFFFF , VPU_INT40_MAX = 0x7FFFFFFFFFLL , VPU_INT40_MIN = -0x7FFFFFFFFFLL
}
 
enum  { VPU_INT8_ACC_SIZE = 32 , VPU_INT16_ACC_SIZE = 32 , VPU_INT32_ACC_SIZE = 40 }
 
enum  { VPU_INT8_ACC_VR_BITS = 16 , VPU_INT16_ACC_VR_BITS = 16 , VPU_INT32_ACC_VR_BITS = 32 }
 
enum  { VPU_INT8_ACC_VR_MASK = 0xFFFF , VPU_INT16_ACC_VR_MASK = 0xFFFF , VPU_INT32_ACC_VR_MASK = 0xFFFFFFFF }
 
enum  { VPU_INT8_EPV = 32 , VPU_INT16_EPV = 16 , VPU_INT32_EPV = 8 }
 
enum  { VPU_INT8_EPV_LOG2 = 5 , VPU_INT16_EPV_LOG2 = 4 , VPU_INT32_EPV_LOG2 = 3 }
 
enum  { VPU_INT8_ACC_PERIOD = 16 , VPU_INT16_ACC_PERIOD = 16 , VPU_INT32_ACC_PERIOD = 8 }
 
enum  { VPU_INT8_ACC_PERIOD_LOG2 = 4 , VPU_INT16_ACC_PERIOD_LOG2 = 4 , VPU_INT32_ACC_PERIOD_LOG2 = 3 }
 
enum  { VPU_INT8_VLMACC_ELMS = 16 , VPU_INT16_VLMACC_ELMS = 16 , VPU_INT32_VLMACC_ELMS = 8 }
 
enum  { VPU_INT8_VLMACC_ELMS_LOG2 = 4 , VPU_INT16_VLMACC_ELMS_LOG2 = 4 , VPU_INT32_VLMACC_ELMS_LOG2 = 3 }
 

Detailed Description

Macro Definition Documentation

◆ XS3_VPU_VREG_WIDTH_BITS

#define XS3_VPU_VREG_WIDTH_BITS   (256)

Width of the VPU vector registers in bits.

◆ XS3_VPU_VREG_WIDTH_BYTES

#define XS3_VPU_VREG_WIDTH_BYTES   (XS3_VPU_VREG_WIDTH_BITS >> 3)

Width of the VPU vector registers in bytes.

◆ XS3_VPU_VREG_WIDTH_WORDS

#define XS3_VPU_VREG_WIDTH_WORDS   (XS3_VPU_VREG_WIDTH_BYTES >> 2)

Width of the VPU vector registers in words.

Typedef Documentation

◆ vpu_int16_acc_t

typedef int32_t vpu_int16_acc_t

Integer type which fits a single accumulator (32-bits) corresponding to the 16-bit VPU mode.

◆ vpu_int32_acc_t

typedef int64_t vpu_int32_acc_t

Integer type which fits a single accumulator (40-bits) corresponding to the 32-bit VPU mode.

◆ vpu_int8_acc_t

typedef int32_t vpu_int8_acc_t

Integer type which fits a single accumulator (32-bits) corresponding to the 8-bit VPU mode.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Data type (bits 11..8) values of vCTRL, the control register for the VPU.

Enumerator
VSETCTRL_TYPE_INT32 

Signed 32-bit Integers

VSETCTRL_TYPE_INT16 

Signed 16-bit Integers

VSETCTRL_TYPE_INT8 

Signed 8-bit Integers

◆ anonymous enum

anonymous enum

Shift type (bits 7..6) values of vCTRL, the control register for the VPU.

Enumerator
VEC_SH0 

Do not shift on VLADSB and VFT*

VEC_SHL 

Shift left on VLADSB and VFT*

VEC_SHR 

Shift right on VLADSB and VFT*

◆ anonymous enum

anonymous enum

The number of elements consumed by a VLMACC instruction in each operating mode. In other words, the number of simultaneous multiply-accumulates performed by the VLMACC instruction.

◆ anonymous enum

anonymous enum

log-base-2 of the corresponding VPU_INT*_VLMACC_ELMS values.

◆ anonymous enum

anonymous enum

The saturation bounds for signed integers in each VPU operating mode.

Enumerator
VPU_INT8_MAX 

The upper saturation bound for 8-bit elements

VPU_INT8_MIN 

The lower saturation bound for 8-bit elements

VPU_INT16_MAX 

The upper saturation bound for 16-bit elements

VPU_INT16_MIN 

The lower saturation bound for 16-bit elements

VPU_INT32_MAX 

The upper saturation bound for 32-bit elements and 32-bit accumulators

VPU_INT32_MIN 

The lower saturation bound for 32-bit elements and 32-bit accumulators

VPU_INT40_MAX 

The upper saturation bound for 40-bit accumulators

VPU_INT40_MIN 

The lower saturation bound for 40-bit accumulators

◆ anonymous enum

anonymous enum

Number of accumulator bits in each operating mode.

In each operating mode, the VLMACC, VLMACCR and VLSAT instructions operate on an array of accumulators in the vector registers vR and vD. In each case, the most significant bits are stored in vD, and the least significant bits are stored in vR.

◆ anonymous enum

anonymous enum

When vD and vR contain accumulators, the values in this enum indicate how many least significant bits are stored in vR, with the remaining bits stored in vD.

◆ anonymous enum

anonymous enum

When vD and vR contain accumulators, the values in this enum can be used to mask off the bits of the accumulator value which correspond to the portion in vR.

◆ anonymous enum

anonymous enum

The number of elements which fit into a vector register for each operating mode.

This is also the number of elements which are operated on in the following instructions: VDEPTH1, VDEPTH16, VDEPTH8, VLADD, VLADDD, VLASHR, VLMACCR, VLMUL, VLSUB, VPOS, VSIGN

◆ anonymous enum

anonymous enum

log-base-2 of the corresponding VPU_INT*_EPV values.

◆ anonymous enum

anonymous enum

The number of accumulators, spread across vR and vD, in each operating mode.

This is also the number of elements consumed (number of multiplies) by the VLMACC instruction.

◆ anonymous enum

anonymous enum

log-base-2 of the corresponding VPU_INT*_ACC_PERIOD values.