I²S/TDM¶

I²S/TDM is typically fundamental to most products and is built into the XUA_AudioHub() thread.

Table 14 lists the defines that affect the I²S implementation.

Table 14 I²S defines¶
Define	Description	Default
`I2S_CHANS_DAC`	The desired number of output channels via I2S (0 for disabled)	N/A (Must be defined)
`I2S_CHANS_ADC`	The desired number of input channels via I2S (0 for disabled)	N/A (Must be defined)
`XUA_PCM_FORMAT`	Enables either TDM or I2S mode	`XUA_PCM_FORMAT_I2S`
`CODEC_MASTER`	Sets if xcore is I2S master or slave	`0` (xcore is master)
`XUA_I2S_N_BITS`	I2S/TDM word length (16, 32-bit supported)	`32`

The I²S code expects that the ports required for I²S (master clock, LR-clock, bit-clock and data lines) are defined in the application XN file on the relevant Tile. For example:

<Tile Number="0" Reference="tile[0]">
    <Port Location="XS1_PORT_1A"  Name="PORT_MCLK_IN"/>
    <Port Location="XS1_PORT_1B"  Name="PORT_I2S_LRCLK"/>
    <Port Location="XS1_PORT_1C"  Name="PORT_I2S_BCLK"/>
    <Port Location="XS1_PORT_1D"  Name="PORT_I2S_DAC0"/>
    <port Location="XS1_PORT_1E"  Name="PORT_I2S_DAC1"/>
    <Port Location="XS1_PORT_1F"  Name="PORT_I2S_ADC0"/>
    <Port Location="XS1_PORT_1G"  Name="PORT_I2S_ADC1"/>
</Tile>

All of the I²S/TDM related ports must be 1-bit ports.

Note

TDM mode allows 8 channels (rather than 2) to be supplied on each data-line.

Note

Data output/input is in “I²S” format, rather than, say “left-justified” or “right-justified” formats. I²S format specifies a single bit-clock delay after the LR-clock transition before sample-data is driven/received. This also applies to TDM mode. TDM support in ADC/DAC hardware is quite varied, an “offset” value may need to be programmed into the external device for compatible operation.