spi.h

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// Copyright 2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#pragma once
 
#define SPI_MASTER_MINIMUM_DELAY 10
 
#include <stdlib.h> /* for size_t */
#include <stdint.h>
#include <xclib.h> /* for byterev() */
#include <xcore/assert.h>
#include <xcore/port.h>
#include <xcore/clock.h>
 
/* The SETC constant for pad delay is missing from xs2a_user.h */
#define SPI_IO_SETC_PAD_DELAY(n) (0x7007 | ((n) << 3))
 
/* These appear to be missing from the public API of lib_xcore */
#define SPI_IO_RESOURCE_SETCI(res, c) asm volatile( "setc res[%0], %1" :: "r" (res), "n" (c))
#define SPI_IO_RESOURCE_SETC(res, r) asm volatile( "setc res[%0], %1" :: "r" (res), "r" (r))
#define SPI_IO_SETSR(c) asm volatile("setsr %0" : : "n"(c));
#define SPI_IO_CLRSR(c) asm volatile("clrsr %0" : : "n"(c));
 
/* is setpsc available in lib_xcore or anywhere else..??? */
__attribute__((always_inline))
inline void spi_io_port_outpw(
        resource_t __p,
        uint32_t __w,
        uint32_t __bpw)
{
    asm volatile("outpw res[%0], %1, %2" : : "r" (__p), "r" (__w), "r" (__bpw));
}
 
typedef enum {
    spi_master_sample_delay_0 = 0, 
    spi_master_sample_delay_1 = 1, 
    spi_master_sample_delay_2 = 2, 
    spi_master_sample_delay_3 = 3, 
    spi_master_sample_delay_4 = 4, 
} spi_master_sample_delay_t;
 
typedef enum {
    spi_master_source_clock_ref = 0, 
    spi_master_source_clock_xcore    
} spi_master_source_clock_t;
 
#define SPI_MODE_0 0,0
 
#define SPI_MODE_1 0,1
 
#define SPI_MODE_2 1,0
 
#define SPI_MODE_3 1,1
 
typedef struct {
    xclock_t clock_block;
    port_t cs_port;
    port_t sclk_port;
    port_t mosi_port;
    port_t miso_port;
    uint32_t current_device;
    int delay_before_transfer;
} spi_master_t;
 
typedef struct {
    spi_master_t *spi_master_ctx;
    spi_master_source_clock_t source_clock;
    int clock_divisor;
    spi_master_sample_delay_t miso_sample_delay;
    uint32_t miso_pad_delay;
    uint32_t miso_initial_trigger_delay;
    uint32_t cs_assert_val;
    uint32_t clock_delay;
    uint32_t clock_bits;
    uint32_t cs_to_clk_delay_ticks;
    uint32_t clk_to_cs_delay_ticks;
    uint32_t cs_to_cs_delay_ticks;
} spi_master_device_t;
 
void spi_master_init(
        spi_master_t *spi,
        xclock_t clock_block,
        port_t cs_port,
        port_t sclk_port,
        port_t mosi_port,
        port_t miso_port);
 
void spi_master_device_init(
        spi_master_device_t *dev,
        spi_master_t *spi,
        uint32_t cs_pin,
        int cpol,
        int cpha,
        spi_master_source_clock_t source_clock,
        uint32_t clock_divisor,
        spi_master_sample_delay_t miso_sample_delay,
        uint32_t miso_pad_delay,
        uint32_t cs_to_clk_delay_ticks,
        uint32_t clk_to_cs_delay_ticks,
        uint32_t cs_to_cs_delay_ticks);
 
void spi_master_start_transaction(
        spi_master_device_t *dev);
 
void spi_master_transfer(
        spi_master_device_t *dev,
        uint8_t *data_out,
        uint8_t *data_in,
        size_t len);
 
inline void spi_master_delay_before_next_transfer(
        spi_master_device_t *dev,
        uint32_t delay_ticks)
{
    spi_master_t *spi = dev->spi_master_ctx;
 
    spi->delay_before_transfer = 1;
 
    port_clear_trigger_time(spi->cs_port);
 
    /* Assert CS now */
    port_out(spi->cs_port, dev->cs_assert_val);
    port_sync(spi->cs_port);
 
    /*
     * Assert CS again, scheduled for earliest time the
     * next transfer is allowed to start.
     */
    if (delay_ticks >= SPI_MASTER_MINIMUM_DELAY) {
        port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + delay_ticks, dev->cs_assert_val);
    }
}
 
void spi_master_end_transaction(
        spi_master_device_t *dev);
 
void spi_master_deinit(
        spi_master_t *spi);
 
typedef void (*slave_transaction_started_t)(void *app_data, uint8_t **out_buf, size_t *outbuf_len, uint8_t **in_buf, size_t *inbuf_len);
 
typedef void (*slave_transaction_ended_t)(void *app_data, uint8_t **out_buf, size_t bytes_written, uint8_t **in_buf, size_t bytes_read, size_t read_bits);
 
#define SPI_CALLBACK_ATTR __attribute__((fptrgroup("spi_callback")))
 // END: addtogroup hil_spi_master
 
typedef struct {
    SPI_CALLBACK_ATTR slave_transaction_started_t slave_transaction_started;
 
    SPI_CALLBACK_ATTR slave_transaction_ended_t slave_transaction_ended;
 
    void *app_data;
} spi_slave_callback_group_t;
 
void spi_slave(
        const spi_slave_callback_group_t *spi_cbg,
        port_t p_sclk,
        port_t p_mosi,
        port_t p_miso,
        port_t p_cs,
        xclock_t clk,
        int cpol,
        int cpha);
 // END: addtogroup hil_spi_slave