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XS1 port-to-pin mapping

Version: X7438A Date: November 14, 2013Download PDF
X7438ANov 14, 2013 download view

On XS1 devices, pins are used to interface with external components via ports and to construct links to other devices over which channels are established. The ports are multiplexed, allowing the pins to be configured for use by ports of different widths. Available ports and links for each pingives the XS1 port-to-pin mapping, which is interpreted as follows:

  • The name of each pin is given in the format XnDpq where n is a valid xCORE Tile number for the device and pq exists in the table. The physical position of the pin depends on the packaging and is given in the device datasheet.
  • Each link is identified by a letter A-D. The wires of a link are identified by means of a superscripted digit 0-4.
  • Each port is identified by its width (the first number 1, 4, 8, 16 or 32) and a letter that distinguishes multiple ports of the same width (A-P). These names correspond to port identifiers in the header file<xs1.h> (for example port 1A corresponds to the identifierXS1_PORT_1A). The individual bits of the port are identified by means of a superscripted digit 0-31.
  • The table is divided into six rows (or banks). The first four banks provide a selection of 1, 4 and 8-bit ports, with the last two banks enabling the single 32-bit port. Different packaging options may export different numbers of banks; the 16-bit and 32-bit ports are not available on small devices.

The ports used by a program are determined by the set of XC port declarations. For example, the declaration

on tile [0] : in port p = XS1_PORT_1A

uses the 1-bit port 1A on xCORE Tile 0, which is connected to pin X0D00.

Usually the designer should ensure that there is no overlap between the pins of the declared ports, but the precedence has been designed so that, if required, portions of the wider ports can be used when overlapping narrower ports are used. The ports to the left of the table have precedence over ports to the right. If two ports are declared that share the same pin, the narrower port takes priority. For example:

on tile[2] : out port p1 = XS1_PORT_32A;
on tile[2] : out port p2 = XS1_PORT_8B;
on tile[2] : out port p3 = XS1_PORT_4C;

In this example:

  • I/O on port p1 uses pins X2D02 to X2D09 and X2D49 to X2D70.
  • I/O on port p2 uses pins X2D16 to X2D19; inputting from p2results in undefined values in bits 0, 1, 6 and 7.
  • I/O on port p3 uses pins X2D14, X2D15, X2D20 and X2D21; inputting from p1 results in undefined values in bits 28-31, and when outputting these bits are not driven.

Available ports and links for each pin

 ⇐ highestprecedencelowest ⇒

Pin link 1-bit ports 4-bit ports 8-bit ports 16-bit ports 32-bit port

XnD01 A4 out1B
XnD02 A3 out 4A08A016A032A20
XnD03 A2 out 4A18A116A132A21
XnD04 A1 out 4B08A216A232A22
XnD05 A0 out 4B18A316A332A23
XnD06 A0 in 4B28A416A432A24
XnD07 A1 in 4B38A516A532A25
XnD08 A2 in 4A28A616A632A26
XnD09 A3 in 4A38A716A732A27
XnD10 A4 in1C

XnD13 B4 out1F
XnD14 B3 out 4C08B016A832A28
XnD15 B2 out 4C18B116A932A29
XnD16 B1 out 4D08B216A10 
XnD17 B0 out 4D18B316A11 
XnD18 B0 in 4D28B416A12 
XnD19 B1 in 4D38B516A13 
XnD20 B2 in 4C28B616A1432A30
XnD21 B3 in 4C38B716A1532A31
XnD22 B4 in1G

XnD26 4E08C0$16B0
XnD27 4E18C1$16B1
XnD28 4F08C2$16B2
XnD29 4F18C3$16B3
XnD30 4F28C4$16B4
XnD31 4F38C5$16B5
XnD32 4E28C6$16B6
XnD33 4E38C7$16B7

XnD361M8D0 16B8
XnD371N8D1 16B9
XnD381O8D2 16B10
XnD391P8D3 16B11
XnD408D4 16B12
XnD418D5 16B13
XnD428D6 16B14
XnD438D7 16B15

XnD49 C4 out$32A0
XnD50 C3 out$32A1
XnD51 C2 out$32A2
XnD52 C1 out$32A3
XnD53 C0 out$32A4
XnD54 C0 in$32A5
XnD55 C1 in$32A6
XnD56 C2 in$32A7
XnD57 C3 in$32A8
XnD58 C4 in$32A9

XnD61 D4 out$32A10
XnD62 D3 out$32A11
XnD63 D2 out$32A12
XnD64 D1 out$32A13
XnD65 D0 out$32A14
XnD66 D0 in$32A15
XnD67 D1 in$32A16
XnD68 D2 in$32A17
XnD69 D3 in$32A18
XnD70 D4 in$32A19