The XMOS architecture enables systems to be constructed from multiple XCore processors connected by communication links. Every XMOS device includes one or more XCores and a high-speed low-latency switch. The switch is used to route messages between the XCores on the chip, and to route messages between chips via the links.
The architecture is scalable and any number of XCores can be connected together. As XCores are added, computational performance increases, memory increases, communication throughput increases and event-handling throughput increases. XCores can be combined on chips, substrates, boards or in distributed systems.
The switches and links allow channels to be established between threads anywhere in a system of connected XCores. The same instructions can be used to communicate between threads whether the threads are executed by the same XCore or by different XCores. As the control of the communications is performed by software, protocols can be optimized for specific applications.
The architecture is event-driven and is designed to minimize energy. XCores and threads do not consume processing resources when waiting for events. The XCore instruction encoding gives rise to very compact programs, optimizing use of memory and minimizing power to access instructions. Direct transfer of data between thread registers and channels or ports avoids transferring data via memory.
The protocol used on the inter-chip links allows very short messages to be sent with negligible protocol overhead. The data is transferred using a transition-based encoding to further reduce energy consumption and the links only use energy when they are actually transferring data.
XS1 Architecture Features
- Deterministic architecture that guarantees each thread a slice of the processing.
- The threads can execute computations, handle real-time I/O operations and respond to multiple events.
- I/O pins can be sampled or driven using a single instruction.
- Data rates can be controlled using timers or clocks.
- A high-performance switch enables communication between processors.
- Complete systems constructed from multiple devices.
- Communication between threads on a processor incurs no latency.
- Latency between processors can be determined for a known communication pattern.
