What is the PDM to PCM latency value for output sample rates?


What is the PDM to PCM latency value for output sample rates?

The group delay of the default filters is 18 output clock cycles.

This can be shortened by either using a minimum phase FIR as the final stage decimation FIR and/or by reducing the number of taps on the final stage decimation FIR.

This is true across all supported sample rates.