FAQs

A fully loaded XS1-G4 (the largest device in the XS1-G family) with 32 threads running consumes about 1W, of which about 100mW is static power. Each core (of which there are 4) can be clock geared to a lower frequency whilst still retaining real time operation, so that a real application can consume just a fraction of that. More accurate numbers will be available as we further characterise our silicon. Forthcoming family members include further power reduction techniques to further reduce dynamic and static power.

XMOS Links on chip can consume data as fast as the ISA can input and output; over 1Gbps. The fabric is non-blocking so multiple streams can exist concurrently. Off chip XMOS Links support either 160Mbps or 400Mbps of bandwidth depending on the chosen link width. Latency is deterministic and depends on the locality of the two communicating threads. On the same core it is one thread cycle, on the same chip but different core latency is three thread cycles and off chip it is 20 thread cycles. (Assumes 8 active threads per XCore.)

The XS1-G family can be booted from SPI flash, an XMOS Link channel end (for multiple chips/cores) or OTP. OTP allows you to store small applications on-chip or define a secondary boot-loader and interface which effectively allows you to ‘boot from anywhere’. OTP boot also supports options such as storing the program externally with encryption to help you protect your IP.

XMOS’s silicon product offerings today are based on mature manufacturing processes offered by the industry’s leading suppliers, all of whom have extensive Quality Systems in place to support their customers. XMOS uses Taiwan-based TSMC’s 90nm Logic Process technology to manufacture the wafers. The product wafers are subsequently packaged using main-stream BGA assembly/packaging technologies and tested using mature ATE platforms at manufacturing sites of Unisem (headquartered in Malaysia). Backed up by design-for-test and exhaustive ATE-based testing methodologies, the products are geared for customer adoption targeting large-volume applications.

Today, the process used to fabricate our devices (TSMC 90G) is not compatible with re-writeable non-volatile technologies such as flash memory. We include OTP memory and boot modes supporting inexpensive and compact serial SPI flashes. We have the capability to integrate flash into our packages so please contact us with your requirements.

Thread scheduling is simple round robin with each active thread being executed in the next system clock cycle. This gives the appearance of up to eight concurrent threads per XCore. All threads are independent and have equal priority meaning that each task always receives a guaranteed minimum number of MIPS; this is central to building deterministic and responsive systems.

We see strong market demand for the four, two and one XCore devices. We chose the four XCore XS1-G4 first since it allowed us to confirm the operation of the switch fabric that allows our cores to communicate. In addition, there is footprint compatibility between devices which means that smaller designs can be prototyped with the XS1-G4 before moving to smaller devices for production.

A port setup to drive the clock output from a clockBlock fails if the clock uses the undivided reference clock, even if the reference clock is divided down from 100MHz to a slower frequency.
To run a slow reference frequency and drive it out of port, set the reference frequency to twice of the desired frequency and divide it by two in the clockBlock before driving the port. Timers must use the 2x frequency.