XS1-G Link Performance and Design Guidelines
Version 1.1
Publication Date: 2010/03/16
Copyright © 2010 XMOS Ltd. All Rights Reserved.

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XS1-G Link Performance and Design Guidelines (1.1)
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1
Overview
This document is intended to assist designers of systems incorporating multiple
XMOS XS1-G family devices, using the propitiatory XMOS Link architecture to connect
the devices together. The following aspects of the system design are covered in this
document:
· What size parts do you need (G4-512/G4-144/G2-144)?
· How many links and what type (2w/5w) do you need?
· What will the topology be like?
· Which links to choose so that the whole system boots from one SPI flash?
XMOS Links have two operating modes, 2 wire (serial mode) and 5 wire (fast mode).
A 2 wire (2w) link has 2 signal wires in each direction (RX/TX); a 5 wire (5w) link has
5 signal wires in each direction. A single transition on one link wire transmits one
symbol in that direction in 2w mode, and two symbols in 5w mode. Connection is
required in both directions, because the protocol is handshaked.
Groups of symbols are routed through the interconnect system as packets comprising
a whole number of bytes with some additional control information and a small amount
of control overhead, such as headers with routing information, and 'end of packet'
(EOP) markers. A byte of data is transferred as 10 symbols (serial mode) or 4 symbols
(fast mode).
2
Inter-Symbol Delay
The time between transmitting symbols (the inter-symbol delay) must be set to ensure
signal transitions are sufficiently spaced out to be safely acquired at the receiver.
The maximum speed of a link is determined mainly by the variability in transition
timing between the wires of the link. Variations in the position of transitions are
affected by:
· Process, temperature and dynamic voltage variability on the XS1 device.
· Pad delay variability, especially the difference in propagation delays of rising
and falling transitions through the XS1 pads.
· Line delay variability arising from PCB design and re-buffering.
The inter-symbol delay or symbol time (Tsymbol) is a multiple of the transmitter's
switch clock cycle time. Lab testing has indicated that a symbol time of 7.5ns should
be achievable under all the scenarios described in Deployment Scenarios Section 8.
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XS1-G Link Performance and Design Guidelines (1.1)
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3
Data Rates
The serial (2w) link uses 10 symbols per byte, and the fast (5w) link uses 4 symbols
per byte.
The raw data rate can the be calculated based on the symbol time as follows:
XMOS serial link bandwidth (bytes/second) = 1/10 Tsymbol
XMOS fast link bandwidth (bytes/second) = 1/4 Tsymbol
Each packet sent over an XMOS Link includes a 3 byte or 1 byte header, which is
user configurable depending on the size of the network. For small networks of a few
chips, 1 byte headers should suffice1. The end of each packet has an EOP marker.
Finally, hardware generated credit messages are employed to manage throughput.
Taking into account all these overheads and assuming an average packet size of 32
bytes with a symbol time of 7.5ns yields the following effective data rates per link:
Link Mode
Header
Data Rate
2w
1 byte
11.4 MBytes/sec
5w
1 byte
30.5 MBytes/sec
4
Link Resources
XS1-G parts have the following link resources available, each of which can be em-
ployed in 5 wire or 2 wire mode. Pins of the package are shared between links
and I/Os--when a link is enabled, I/Os that use these pins are disabled. The links
are called XnLA, XnLB, XnLC, XnLD, where n is in the range 0-3, and represents the
XCore with whose I/O that particular link is multiplexed. Note that a link which
is multiplexed with the general purpose I/O of a given XCore is not restricted to
communicating with that XCore alone, since the XS1-G system switch can route from
any link on the XS1-G to any XCore on the XS1-G.
13 byte headers can be used to provide a slightly faster data rate compared to 1 byte headers,
but this is generally only an issue for large multiple-chip networks. Information on developing such
networks is beyond the scope of this document, please contact XMOS for further details.
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XS1-G Link Performance and Design Guidelines (1.1)
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Device
XMOS Links
X0LA
X0LB
X0LC
X0LD
X1LA
X1LB
X1LC
X1LD
XS1-G4-512BGA
X2LA
X2LB
X2LC
X2LD
X3LA
X3LB
X3LC
X3LD
X0LA
X0LB
X0LC
X0LD
X1LA
X1LB
XS1-G4-144BGA
X2LA
X2LB
X3LA
X3LB
X0LA
X0LB
X0LC
X0LD
X1LA
X1LB
XS1-G2-144BGA
X2LA
X2LB
X3LA
X3LB
Please refer to product datasheets for a complete map of I/Os and links.
5
Booting over XMOS Links
The XS1-G family does not have a built in mode by which these devices may be
booted over their XMOS Links. The XS1-G OTP can be programmed to facilitate boot
over XMOS Links, however the details of this are beyond the scope of this document.
If your application requires the ability to boot a system over XMOS Links, please also
consider the XS1-L family.
6
XS1-G System Topologies
XS1-G multi-chip networks must be connected in a hypercube topology. Three node
XS1-G networks are not supported by the XMOS toolchain.
6.1
Two Node Network
An XS1-G network may be constructed using XMOS Links. This will form a network of
nodes in which each node is an XS1-G system switch with four or two cores hanging
off it. The four XCores local to a node communicate using the on-chip routing
resources of the system switch. Each XCore local to the node may also communicate
with XCores on other chips (nodes) in the network via XMOS Links.
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XS1-G Link Performance and Design Guidelines (1.1)
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Figure 1 shows the connection of two XS1-G4 devices such that both devices inde-
pendently boot from SPI Flash, after which they communicate using XMOS Links. The
diagram, shows that the minimum configuration is one full XMOS Link.
SPI
SPI
FLASH
FLASH
NC
X0LA
X0LB
Mandatory
X0LB
X0LA
NC
[2w]
[2w]
X0LC
X0LC
...
Optional
...
X3LD
X3LD
Figure 1: XS1-G two chip network
Once this minimum configuration is met, connection of the remaining links between
the two nodes is optional, and need not be symmetric. For example, all links except
one could carry traffic from left to right, or N links can carry traffic left and n links
can carry traffic right.
Note that:
· The links used for mandatory connections in Figure 1 can be any available links
(they need not be X0LB as shown in the diagram).
· Devices that boot from SPI cannot use X0LA in 5 wire mode (because some pins
are used for the SPI I/O pins).
· Links marked NC in Figure 1 are not required by the system topology. The I/O
pins that overlap these XMOS Link can be used for other purposes.
6.2
Four Node Network
The next size of network that can be supported is a four node system, shown in
Figure 2.
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XS1-G Link Performance and Design Guidelines (1.1)
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Mandatory
X0LA
X3LB
XnLn
Optional
XnLn
X3LB
XnLn
XnLn
X0LA
Illegal
Links
Optional
Optional
Mandatory
Mandatory
X0LA
XnLn
XnLn
X3LB
XnLn
Optional
XnLn
Mandatory
X3LB
X0LA
Figure 2: XS1-G four chip network
In this network there are two directions of traffic--clockwise and anticlockwise. Each
node must have at least one link connected for each direction of traffic. In this
example X0LA carries traffic clockwise and X3LB carries traffic anticlockwise.
Diagonal connections between the nodes in this configuration are illegal, however any
number of links may be added to augment the minimum mandatory link configuration
to increase bandwidth between any two adjacent nodes in this system.
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XS1-G Link Performance and Design Guidelines (1.1)
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6.3
Large Hypercube Networks
All XS1-G link networks must be N-dimensional hypercubes. Details of constructing
networks with more than four nodes, and why the diagonal links in Figure 2 are
illegal, are beyond the scope of this document. Please refer to the XS1-G System
Specification (xmos.com/published/xsystem) or contact XMOS support for details of
more complicated XS1-G networks.
Note that the XMP-64 Multi-Processor Board (available from XMOS) is a 16-node
hypercube network. Information on the board, including schematics and design files,
are available from xmos.com/xmp64.
7
Layout Guidelines
7.1
Link Compatability
The XMOS Links between the XS1-G and XS1-L family are not compatible and cannot
be connected together.
7.2
Crosstalk and Noise
Because XMOS Links are a transition-based protocol rather than a level-based protocol,
they are vulnerable to noise via crosstalk or EMI. Accordingly XMOS Links should be
designed to minimize noise:
· Do not route the signals closely in parallel for large distances. The traces need
separating out to minimize cross-talk between the lines.
· Do not route the signals close to noisey items on the PCB (such as switch-mode
power supplies and clocks).
· Try not to route the XMOS Link over splits in the ground plane, as the return
ground currents can cause cross-talk.
· If the traces are going over long distances, use low voltage differential signalling
transceivers (LVDS) at each of the link to make the links immune to common-
mode interference (for example DS90LV049 as used in the XDK) and improve
the achievable symbol rate be utilized.
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XS1-G Link Performance and Design Guidelines (1.1)
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7.3
Pulldown Resistors
When XMOS Links are enabled, the wires should be logic low. Weak internal pull
downs are active on the XMOS Link pins before they are enabled. These pull downs
cannot be relied upon to pull down long traces with high capacitance. Circuit
designers should apply external pull down resistors on such tracks.
8
Deployment Scenarios
The following XMOS Link examples all operate error free with an inter symbol delay
of 7.5ns.
2w link with 150mm FPC Flexible Ribbon Cable ­ Serial (2w) Link utilizing 4 sig-
nal (2 per link direction) and 2 ground wires, with single ended drivers (for
example 74AUP2G17) located at driving (TX) pins.
2w link with 150mm FPC Flexible Ribbon Cable and LVDS Transceivers ­ Serial
(2w) Link utilizing 8 signal (2 differential pairs per link direction) and 6 ground
wires, with LVDS transceivers (for example DS90LV049) located at each end of
each link wire.
2w link with 1000mm RJ45 double shielded cables and LVDS Transceivers ­ Se-
rial (2w) Link utilizing 8 signal (2 differential pairs per link direction) and 2
ground wires, with LVDS transceivers (for example DS90LV049) located at each
end of each link wire.
5w and 2w Link with up to 100mm of PCB Track ­ Link with 33R series terminat-
ing resistors close to the TX sides of each wire, using no driver chips.
9
EMI
XMOS Links are awaiting EMI qualification. Please contact XMOS if further discussion
of noise immunity is required.
XMOS also advises customers to have the noise immunity of their own particular
design employing XMOS Links tested in the appropriate laboratory environment.
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Document History
Date
Release
Comment
2010-02-22
1.0
First release
2010-03-16
1.1
Amended Layout Guidelines section
Clarified use of NC links
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively,
the "Information") and is providing it to you "AS IS" with no warranty of any kind,
express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the Information, or any particular implementation thereof, is
or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
Copyright ©2009-10 XMOS Ltd. All Rights Reserved. XMOS and the XMOS logo
are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names
mentioned in this document are the trademarks or registered trademarks of their
respective owners. Where those designations appear in this document, and XMOS
was aware of a trademark claim, the designations have been printed with initial
capital letters or in all capitals.
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Document Outline

• Overview
• Inter-Symbol Delay
• Data Rates
• Link Resources
• Booting over XMOS Links
• XS1-G System Topologies