XS1-G Clock Frequency Control
Version 1.0
Publication Date: 2010/02/22
Copyright © 2010 XMOS Ltd. All Rights Reserved.

---

XS1-G Clock Frequency Control (1.0)
2/11
1
PLL and Clock Divider Overview
A low frequency external clock is used to drive the internal phase locked loop (PLL)
of XS1-G devices and obtain the system clock. A number of system clock dividers are
then used on the system clock to derive the clocks for the XCores, the switch and
the reference clock (Figure 1).
Divider
SS_CLK
Multiplier
Divider
÷2
Switch
Switch
÷N
* M
÷P
Divider
Clk
Reference
Ref
Divider
Clk
Comparator
VCO
System
XCore0
XCore0
Freq
Freq
Freq
Divider
Clk
XCore1
XCore1
Divider
Clk
System Clock Dividers
XCore2
XCore2
Divider
Clk
XCore3
XCore3
Divider
Clk
Figure 1: PLL and Clock Dividers
The PLL's initial settings are determined by the state of mode pins on the XS1-G
device. The standard configuration allows a 20MHz external clock to be used to
operate the XCores and the switch at 400MHz, and the reference clock at 100MHz.
In many applications this configuration will be selected, requiring no reprogramming
of the PLL or dividers. If the application requires a different input frequency or
system frequency then the PLL must be reprogrammed. This results in the XS1-G
device being reset to use the new PLL configuration. The XMOS Tools can be used to
reprogram the PLL automatically by specifying the application's configuration in the
XN file.
When the system clock dividers are reprogrammed to change the frequency to the
XCores, the switch or the reference clock, no reset will occur.
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
3/11
2
Constraints
There are a number of constraints on the frequencies of clocks at different points on
the XS1-G devices. These constraints must be met for the initial boot sequence, and
if the PLL is reprogrammed, for the reprogrammed values too.
Clock
Constraint
SS_CLK
12.5­20.0 MHz
25.0­100.0 MHz
Comparator frequency 4.0­100.0 MHz
VCO frequency
250­500 MHz (VCORANGE=0)
500­1000 MHz (VCORANGE = 1)
System clock
Maximum operating frequency--see the XS1-G device datasheet
XCore clock
System clock maximum
Switch clock
System clock maximum
Reference clock
System clock maximum
Table 1: Clock Frequency Constraints
3
PLL Settings
There are three dividers within the PLL. N divides the input clock down. The next
divider divides the output of the voltage controlled oscillator (VCO) stage down to
the same frequency as the output of the N divider. Therefore this divider sets the
multiplication factor (M) of the PLL. The P divider divides the output clock of the VCO.
There is a constraint on the frequency of the clock at the comparator, i.e. the output
of N. There is another constraint placed on the output of the VCO which depends on
what value VCORANGE is set to. On reset this is determined by the mode pins as per
Table 2, but VCORANGE can be changed when reprogramming the PLL by writing to
the PLL_CTRL register.
4
Configuring the XS1-G Device
The mode pins are used to determine the initial PLL settings used after reset. This
configuration must be such that all of the constraints are met for the input clock
driven onto SS_CLK.
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
4/11
Mode
SS_PLL SS_EXT
SS_EXT
SS_CLK
XCore
N M P
VCO
System
BYPASS
OSC
HS_MODE
Range
Clock
RANGE Clock =
CONFIG
(MHz)
(MHz)
SS_CLK*
Default
0
0
X
12.5­20.0 250­400 1 79 0
1
*20
LSOSC
0
1
0
25­50
125­250 1 19 0
0
*5
HSOSC
0
1
1
50­100
125­250 1 9 0
0
*2.5
Bypass
1
X
X
<100
<50
X X X
X
*0.5
Table 2: Mode Pins and Boot Configuration
IMPORTANT: If the XS1-G device is booted in Bypass mode, the application must
remain in Bypass mode. Any changes to the PLL will have no effect on the system
frequency.
If a different PLL configuration is required from that used to boot the application, the
new settings should be written to the PLL_CTRL register. This will cause the XS1-G
device to reset using the new PLL settings, and the same boot code will execute
again. It is important, therefore, that the boot code should read the value of the
PLL_CTRL register and compare it to the reconfigured value. If there is a difference,
then this is the first time the boot code has executed and the new PLL settings should
be written to PLL_CTRL, causing a reset. The second time the boot code executes,
the value read back from the PLL_CTRL register will be the reconfigured value and
the boot process can continue.
The easiest way to reprogram the PLL is to specify the application's frequency
requirements in the XN file and use the XMOS Tools to reprogram the PLL--see
Section 8.
The application may require the reprogramming of the system clock dividers. These
can be programmed without causing a reset.
5
Frequency Control Registers
To access these registers on the SSwitch and PSwitch, packets of data must be
constructed and communicated to the switches through a channel end.
Global PLL settings are controlled through registers in the System Switch Control
(SSCTRL). From C or XC, use the write_sswitch_reg() and read_sswitch_reg() functions
defined in xs1.h.
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
5/11
Field
Register
Bitfield
Reset
Description
N
SSCTRL
[4:0]
See Table 2 PLL input divider stage = N+1
PLL_CTRL
(0x6)
M
SSCTRL
[15:8] See Table 2 Multiplier stage of the PLL = M+1
PLL_CTRL
(0x6)
VCORANGE
SSCTRL
[24]
See Table 2 0:VCORANGE = 250-500 MHz
PLL_CTRL
1:VCORANGE = 500-1000 MHz
(0x6)
P
SSCTRL
[23:16] See Table 2 PLL output divider stage = P+1
PLL_CTRL
(0x6)
SSDIV
SSCTRL
[7:0]
0
System switch clock divider = SSDIV+1
SSWITCH_
Reset value produces 400MHz for a 400MHz
CLK_DIVIDER
system clock
(0x7)
.REFDIV
SSCTRL
[7:0]
3
Reference clock divider = REFDIV+1
SW_REF_
Reset value produces 400MHz for a 400MHz
CLK_DIVIDER
system clock. Note that REFDIV should not
be programmed with a value of 0.
(0x8)
Table 3: SSCTRL Registers
IMPORTANT: Writing to the PLL_CTRL register (0x6) will cause an internal chip reset.
Settings on an individual XCore basis are controlled through registers in the Pro-
cessor Switch Control (PSCTRL). From C or XC, use the write_pswitch_reg() and
read_pswitch_reg() functions defined in xs1.h.
Field
Register
Bitfield Reset Description
XCDIV
PSCTRL
[7:0]
0
XCore clock divider = XCDIV+1
PROC_CONTROL
Reset value produces 400MHz for a 400MHz
(0x6)
system clock
Table 4: PSCTRL Registers
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
6/11
6
Example PLL Configurations
6.1
Standard Configuration: 20MHz Oscillator
Use SS_PLL_BYPASS = 0, SS_EXT_OSC_CONFIG = 0, the PLL will configure to the
standard 800MHz, with the XCores and SSwitch running at 400MHz, with a 100MHz
reference clock.
6.2
25MHz Oscillator
Use SS_PLL_BYPASS = 0, SS_EXT_OSC_CONFIG=1, SS_EXT_HS_MODE = 0. For the
initial boot, the system clock will be 250MHz, with the XCores running at 125MHz.
The following values are required: N = 1, M = 64, P = 0, VCORANGE = 1. You can
write 0x01003F01 to SSCTRL, PLL_CTRL (0x6) register to bring the PLL output up to
800MHz, with code similar to the following:
#define PLL_CTRL_REGNUM 6
#define PLL_CTRL_25MHz 0x01003F01
{
unsigned pllCtrlReadData;
read_sswitch_reg(get_core_id(), PLL_CTRL_REGNUM, pllCtrlReadData);
if (pllCtrlReadData != PLL_CTRL_25MHz)
{
write_sswitch_reg(get_core_id(), PLL_CTRL_REGNUM, PLL_CTRL_25MHz);
}
}
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
7/11
6.3
12.5MHz Oscillator
Use SS_PLL_BYPASS = 0, SS_EXT_OSC_CONFIG=0. For the initial boot, the system
clock will be 500MHz, with the XCores running at 250MHz. The following values
are required: N = 0, M = 64, P = 0, VCORANGE = 1. You can write 0x01003F00 to
SSCTRL, PLL_CTRL (0x6) register to bring the PLL output up to 800MHz, with code
similar to the following:
#define PLL_CTRL_REGNUM 6
#define PLL_CTRL_12p5MHz 0x01003F00
{
unsigned pllCtrlReadData;
read_sswitch_reg(get_core_id(), PLL_CTRL_REGNUM, pllCtrlReadData);
if (pllCtrlReadData != PLL_CTRL_12p5MHz)
{
write_sswitch_reg(get_core_id(), PLL_CTRL_REGNUM, PLL_CTRL_12p5MHz);
}
}
}
7
Example System Clock Divider Configurations
7.1
133MHz Reference Clock
To adjust the Reference Clock to 133MHz with a 400MHz System Clock, set REFDIV
to 2 using the following code:
#define REFDIV_REGNUM 8
write_sswitch_reg(get_core_id(), REFDIV_REGNUM, 0x02);
The code adjusts all timers and clock-blocks to run at 133.3MHz, and allows ports to
be configured at 66MHz, 33MHz and so on.
7.2
Slow Switch Clock
Dynamic power can be reduced on the SSwitch by reducing its clock rate when
communications between XCores is not required. This can be reversed when commu-
nications need to be resumed.
To reduce the switch clock to 10MHz with a system clock of 400MHz, set SSDIV to
39 using the following code:
#define SSDIV_REGNUM 8
write_sswitch_reg(get_core_id(), SSDIV_REGNUM, 39);
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
8/11
7.3
Slow XCore Clock
If your application does not need to run the XCore at full speed to work, dynamic
power can be saved by running the XCore at a slower rate. Power can also be saved
by reducing the clock rate of an XCore when it is not required to do any processing,
and increased when it is needed.
To run an XCore at 200MHz from a system frequency of 400MHz, set XCDIV to 1
using the following code:
#define XCDIV_REGNUM 6
write_pswitch_reg(get_core_id(), XCDIV_REGNUM, 1);
7.4
Minimum XCore Clock
If an application is not using all the XCores on a device, power can be saved by
clocking unused XCores at the minimum rate using the maximum system clock divide
ratio.
To run an XCore at its minimum clock rate, set XCDIV to 255 using the following
code:
#define XCDIV_REGNUM 6
write_pswitch_reg(get_core_id(), XCDIV_REGNUM, 255);
8
Configuring the Clock System Through the XN File
The PLL and the reference clock frequency can be programmed automatically for an
application by using the XMOS Tools. The application's input oscillator frequency,
system frequency and reference frequency can be specified in the XN file. When the
application code is written to a flash device with XFLASH, the code to reprogram the
PLL to the desired system and reference frequencies will be added. When run with
XRUN or XGDB the PLL is reprogrammed via JTAG.
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
9/11
Attribute
Description
Default Value
Oscillator
Input frequency on the SS_CLK pin. If Uses boot configura-
this attribute is specified, the system fre- tion
quency and the reference frequency are
programmed using their specified (or de-
fault) values. If this attribute is not spec-
ified, the boot configuration for the sys-
tem and reference frequencies are used
for the application.
SystemFrequency
The desired system frequency. The Os- 400MHz
cillator attribute must be specified if this
attribute is specified.
ReferenceFrequency
The desired reference frequency. The Os- 100MHz
cillator attribute must be specified if this
attribute is specified.
Table 5: XN File Frequency Control Attributes
The frequency control attributes should be added to the Node node within the XN
file. Frequencies should be specified with their unit of MHz, kHz or Hz, (for example
500MHz, 24576kHz or 6745800Hz). If the frequency control attributes are not
specified in the XN file, then the XMOS Tools will not modify the frequency control
registers.
If the target frequency specified in the XN file for either the system or reference
frequency cannot be met exactly for the application's input frequency, a frequency
close to the target frequency will be selected by the tools and a warning will be
issued. XFLASH always issues the warning when it occurs, as does XGDB. XRUN
only issues the warning if it has been run with the --verbose switch. XGDB issues
the warning when the connect command is issued. Within the XMOS Development
Environment, the XFLASH warning is issued to the Console view, but the XGDB or
XRUN warning is not available to the user.
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
10/11
8.1
Example XN file using Frequency Control Attributes
<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
<Type>Board</Type>
<Declarations>
<Declaration>core stdcore[1]</Declaration>
</Declarations>
<Nodes>
<Node Id="0" Type="XS1-G4B-FB512" Oscillator="20MHz"
SystemFrequency="300MHz" ReferenceFrequency="60MHz">
<Core Number="0" Reference="stdcore[0]">
<Port Location="XS1_PORT_1I" Name="PORT_UART_RX"/>
<Port Location="XS1_PORT_1J" Name="PORT_UART_TX"/>
</Core>
</Node>
</Nodes>
<JTAGChain>
<JTAGDevice NodeId="0"/>
</JTAGChain>
</Network>
9
Document History
Date
Release
Comment
2010-02-22
1.0
First release
www.xmos.com

---

XS1-G Clock Frequency Control (1.0)
11/11
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively,
the "Information") and is providing it to you "AS IS" with no warranty of any kind,
express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the Information, or any particular implementation thereof, is
or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
Copyright ©2009-10 XMOS Ltd. All Rights Reserved. XMOS and the XMOS logo
are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names
mentioned in this document are the trademarks or registered trademarks of their
respective owners. Where those designations appear in this document, and XMOS
was aware of a trademark claim, the designations have been printed with initial
capital letters or in all capitals.
www.xmos.com

---

Document Outline

• PLL and Clock Divider Overview
• Constraints
• PLL Settings
• Configuring the XS1-G Device
• Frequency Control Registers
• Example PLL Configurations
• Example System Clock Divider Configurations