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XS1-G04B-FB144 Datasheet
XS1-G04B-FB144 Datasheet
Document Number: 1087C
Publication Date: 2011/05/16
Copyright © 2010 XMOS Limited, All Rights Reserved.
XS1-G04B-FB144 Datasheet
1
Table of Contents
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
5
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
6
DC and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
Addendum: XMOS USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Associated Design Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TO OUR VALUED CUSTOMERS
It is our intention to provide you with accurate and comprehensive documentation for the hardware and
software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/.
XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you "AS IS" with
no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names mentioned in this document
are the trademarks or registered trademarks of their respective owners.
Document Number: 1087C
XS1-G04B-FB144 Datasheet
2
1
Features
· Quad-Core Device with Advanced Multi-Threaded RISC Architecture
· Up to 1600 MIPS shared between up to 32 real-time threads
· Each thread has:
-- Guaranteed throughput of between 1/4 and 1/8 of core MIPS
-- 16x32bit dedicated registers
· 159 high-density 16/32-bit instructions
-- All have single clock-cycle execution (except for divide)
-- High-performance DSP (32x3264-bit MAC) and cryptographic instructions
· Programmable I/O
· 88 general-purpose I/O pins, configurable as input, output or bi-directional ports
· Port sampling rates of up to 60 MHz with respect to an external clock
· 128 channel ends for communication with other threads, on or off-chip
· Non-Volatile Memory
· 256KB internal single-cycle SRAM (max 64KB per core) for code and data storage
· 32KB internal OTP (max 8KB per core) for application boot code
· JTAG Module for On-Chip Debug
· Security Features
· Programming lock disables debug and prevents read-back of memory contents
· AES bootloader ensures secrecy of IP held on external flash memory
· Ambient Temperature Range
· Commercial qualification: 0 °C to 70 °C
· Industrial qualification: -40 °C to 85 °C
· Speed Grade
· 400 MHz part: 400 MIPS
· 144-pin FBGA package 0.8 mm pitch
Document Number: 1087C
XS1-G04B-FB144 Datasheet
3
2
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
A
IO VDD
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
VSS
B
X0D33
VSS
X0D18
X0D19
X0D20
IO VDD
VSS
X0D21
X0D22
X0D23
IO VDD
X2D24
C
X0D32
X0D17
VDD
X0D06
X0D07
X0D08
X0D09
X0D10
X0D11
VDD
X2D12
X2D25
SS_PLL_
SS_
OTP_
SS_XC0_ SS_XC_
D
X0D31
X0D16
X0D05
BYPASS
RESET
VDD
VPP
BS[0]
CFG[0]
X2D00
X2D13
X2D26
E
X0D30
X0D15
X0D04
SS_CLK
SS_
VSS
VSS
VSS
VSS
DEBUG
X2D01
X2D14
X2D27
F
X0D29
IO VDD
SS_PLL_
X0D03
AGND
VSS
VSS
VSS
VSS
VDD
X2D02
VSS
X2D28
SS_
G
X0D28
VSS
X0D02
VDD
VSS
VSS
VSS
VSS
TEST_
X2D03
IO VDD
X2D29
ENA
SS_PLL_
H
X0D27
X0D14
X0D01
AVDD
VSS
VSS
VSS
VSS
SS_TCK
X2D04
X2D15
X2D30
SS_PLL_
J
X0D26
X0D13
X0D00
LOCK
SS_TMS
SS_TDO
VDD
SS_TDI
SS_TRST
X2D05
X2D16
X2D31
K
X0D25
X0D12
VDD
X2D11
X2D10
X2D09
X2D08
X2D07
X2D06
VDD
X2D17
X2D32
L
X0D24
IO VDD
X2D23
X2D22
X2D21
VSS
IO VDD
X2D20
X2D19
X2D18
VSS
X2D33
M
VSS
X2D43
X2D42
X2D41
X2D40
X2D39
X2D38
X2D37
X2D36
X2D35
X2D34
IO VDD
Document Number: 1087C
XS1-G04B-FB144 Datasheet
4
3
Signal Description
Module
Signal
Function
Type
Active
Properties
PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger, OT=Output Tristate, S=Switchable
RS=Required for SPI boot (§5.8), RU=Required for USB-enabled devices (§10)
VDD
Digital core power
PWR
--
VSS
Digital ground
GND
--
IO VDD
Digital I/O power
PWR
--
Power
SS_PLL_AGND
Analog ground for PLL
GND
--
SS_PLL_AVDD
Analog PLL power
PWR
--
OTP_VPP
OTP programming voltage
PWR
--
SS_RESET
Global reset input
Input
--
PU, ST
SS_CLK
PLL reference clock
Input
--
PD, ST
PLL
SS_PLL_BYPASS
PLL bypass
Input
--
PD
SS_XC0_BS[0:0]
Boot status (core 0)
I/O
--
PU
SS_TDI
Test data input
Input
--
PU, ST
SS_TDO
Test data output
Output
--
PD
SS_TMS
Test mode select
Input
--
PU, ST
JTAG
SS_TRST
Test reset input
Input
--
PU, ST
SS_TCK
Test clock
Input
--
PU, ST
SS_DEBUG
Multi-chip debug
I/O
--
PU
X0D00
P1A0
I/O
--
RS
X0D01
X0LA4i
5b
P1B0
I/O
--
RS
X0D02
X0LA3i
5b
P4A0 P8A0 P16A0 P32A20
I/O
--
RU
X0D03
X0LA2i
5b
P4A1 P8A1 P16A1 P32A21
I/O
--
RU
X0D04
X0LA1i
2b/5b
P4B0 P8A2 P16A2 P32A22
I/O
--
RU
X0D05
X0LA0i
2b/5b
P4B1 P8A3 P16A3 P32A23
I/O
--
RU
X0D06
X0LA0o
2b/5b
P4B2 P8A4 P16A4 P32A24
I/O
--
RU
X0D07
X0LA1o
2b/5b
P4B3 P8A5 P16A5 P32A25
I/O
--
RU
X0D08
X0LA2o
5b
P4A2 P8A6 P16A6 P32A26
I/O
--
RU
X0D09
X0LA3o
5b
P4A3 P8A7 P16A7 P32A27
I/O
--
RU
X0D10
X0LA4o
XCore 0 I/O
5b
P1C0
I/O
--
RS
X0D11
P1D0
I/O
--
RS
X0D12
P1E0
I/O
--
RU
X0D13
X0LB4i
5b
P1F0
I/O
--
RU
X0D14
X0LB3i
5b
P4C0 P8B0 P16A8 P32A28
I/O
--
RU
X0D15
X0LB2i
5b
P4C1 P8B1 P16A9 P32A29
I/O
--
RU
X0D16
X0LB1i
2b/5b
P4D0 P8B2 P16A10
I/O
--
RU
X0D17
X0LB0i
2b/5b
P4D1 P8B3 P16A11
I/O
--
RU
X0D18
X0LB0o
2b/5b
P4D2 P8B4 P16A12
I/O
--
RU
X0D19
X0LB1o
2b/5b
P4D3 P8B5 P16A13
I/O
--
RU
X0D20
X0LB2o
5b
P4C2 P8B6 P16A14 P32A30
I/O
--
RU
X0D21
X0LB3o
5b
P4C3 P8B7 P16A15 P32A31
I/O
--
RU
(continued)
Document Number: 1087C
XS1-G04B-FB144 Datasheet
5
Module
Name
Function
Type
Active
Properties
X0D22
X0LB4o
5b
P1G0
I/O
--
RU
X0D23
P1H0
I/O
--
RU
X0D24
P1I0
I/O
--
X0D25
P1J0
I/O
--
X0D26
P4E0 P8C0 P16B0
I/O
--
RU
X0D27
P4E1 P8C1 P16B1
I/O
--
RU
X0D28
P4F0 P8C2 P16B2
I/O
--
RU
X0D29
P4F1 P8C3 P16B3
I/O
--
RU
X0D30
P4F2 P8C4 P16B4
I/O
--
RU
X0D31
P4F3 P8C5 P16B5
I/O
--
RU
X0D32
P4E2 P8C6 P16B6
I/O
--
R
XCore 0 I/O
U
X0D33
P4E3 P8C7 P16B7
I/O
--
RU
X0D34
P1K0
I/O
--
X0D35
P1L0
I/O
--
X0D36
P1M0
P8D0 P16B8
I/O
--
X0D37
P1N0
P8D1 P16B9
I/O
--
RU
X0D38
P1O0
P8D2 P16B10
I/O
--
RU
X0D39
P1P0
P8D3 P16B11
I/O
--
RU
X0D40
P8D4 P16B12
I/O
--
RU
X0D41
P8D5 P16B13
I/O
--
RU
X0D42
P8D6 P16B14
I/O
--
RU
X0D43
P8D7 P16B15
I/O
--
RU
X2D00
P1A0
I/O
--
X2D01
X2LA4i
5b
P1B0
I/O
--
X2D02
X2LA3i
5b
P4A0 P8A0 P16A0 P32A20
I/O
--
RU
X2D03
X2LA2i
5b
P4A1 P8A1 P16A1 P32A21
I/O
--
RU
X2D04
X2LA1i
2b/5b
P4B0 P8A2 P16A2 P32A22
I/O
--
RU
X2D05
X2LA0i
2b/5b
P4B1 P8A3 P16A3 P32A23
I/O
--
RU
X2D06
X2LA0o
2b/5b
P4B2 P8A4 P16A4 P32A24
I/O
--
RU
X2D07
X2LA1o
2b/5b
P4B3 P8A5 P16A5 P32A25
I/O
--
RU
X2D08
X2LA2o
5b
P4A2 P8A6 P16A6 P32A26
I/O
--
RU
X2D09
X2LA3o
5b
P4A3 P8A7 P16A7 P32A27
I/O
--
RU
XCore 2 I/O
X2D10
X2LA4o
5b
P1C0
I/O
--
X2D11
P1D0
I/O
--
X2D12
P1E0
I/O
--
RU
X2D13
X2LB4i
5b
P1F0
I/O
--
RU
X2D14
X2LB3i
5b
P4C0 P8B0 P16A8 P32A28
I/O
--
RU
X2D15
X2LB2i
5b
P4C1 P8B1 P16A9 P32A29
I/O
--
RU
X2D16
X2LB1i
2b/5b
P4D0 P8B2 P16A10
I/O
--
RU
X2D17
X2LB0i
2b/5b
P4D1 P8B3 P16A11
I/O
--
RU
X2D18
X2LB0o
2b/5b
P4D2 P8B4 P16A12
I/O
--
RU
X2D19
X2LB1o
2b/5b
P4D3 P8B5 P16A13
I/O
--
RU
X2D20
X2LB2o
5b
P4C2 P8B6 P16A14 P32A30
I/O
--
RU
(continued)
Document Number: 1087C
XS1-G04B-FB144 Datasheet
6
Module
Name
Function
Type
Active
Properties
X2D21
X2LB3o
5b
P4C3 P8B7 P16A15 P32A31
I/O
--
RU
X2D22
X2LB4o
5b
P1G0
I/O
--
RU
X2D23
P1H0
I/O
--
RU
X2D24
P1I0
I/O
--
X2D25
P1J0
I/O
--
X2D26
P4E0 P8C0 P16B0
I/O
--
RU
X2D27
P4E1 P8C1 P16B1
I/O
--
RU
X2D28
P4F0 P8C2 P16B2
I/O
--
RU
X2D29
P4F1 P8C3 P16B3
I/O
--
RU
X2D30
P4F2 P8C4 P16B4
I/O
--
RU
X2D31
P4F3 P8C5 P16B5
I/O
--
RU
XCore 2 I/O
X2D32
P4E2 P8C6 P16B6
I/O
--
RU
X2D33
P4E3 P8C7 P16B7
I/O
--
RU
X2D34
P1K0
I/O
--
X2D35
P1L0
I/O
--
X2D36
P1M0
P8D0 P16B8
I/O
--
X2D37
P1N0
P8D1 P16B9
I/O
--
RU
X2D38
P1O0
P8D2 P16B10
I/O
--
RU
X2D39
P1P0
P8D3 P16B11
I/O
--
RU
X2D40
P8D4 P16B12
I/O
--
RU
X2D41
P8D5 P16B13
I/O
--
RU
X2D42
P8D6 P16B14
I/O
--
RU
X2D43
P8D7 P16B15
I/O
--
RU
SS_PLL_LOCK
Reserved (do not connect)
Output
--
PD
Reserved
SS_TEST_ENA
Reserved (tie to VSS)
Input
--
PD
SS_XC_CFG[0:0]
Reserved (tie to IO VDD)
Input
--
PD
Document Number: 1087C
XS1-G04B-FB144 Datasheet
7
4
Block Diagram
X0D00 ¶
· 1A
X0D01 ¶ ·
1B
Thread 0
64KB SRAM
X0D02 ¶ ·
64KB SRAM
Thread 0
A
X0D03 ¶ ·
4
X0D08 ¶ ·
rt
Thread 1
Boot ROM
X0D09 ¶ ·
A
Po
8
LA
X0D04 ¶ · 0
rt
X
X0D05 ¶ ·
B
Po
4
Thread 2
8KB OTP
X0D06 ¶ ·
rt
Boot ROM
Thread 1
s
X0D07 ¶ ·
Po
d
En
X0D10 ¶ ·
Security Register
1C
Thread 3
el
X0D11 ¶
·
A
1D
6
itch
n
X0D12 ¶
·
1
1E
an
rt
Sw
h
X0D13 ¶ ·
Thread 4
6 Clock Blocks
1F
Po
8KB OTP
Thread 2
C
X0D14 ¶ ·
23
X0D15 ¶ ·
C4
Thread 5
10 Timers
X0D20 ¶ ·
rt
B
X0D21 ¶ ·
Po
8
LB
X0D16 ¶ · 0
rt
X
Security
s
Thread 6
4 Locks
X0D17 ¶ ·
D
Po
Thread 3
d
4
Register
X0D18 ¶ ·
En
rt
X0D19 ¶ ·
el
Po
n
itch
Thread 7
7 Synchronizers
X0D22 ¶ ·
1G
an
Sw
X0D23 ¶
·
h
1H
C
X0D24 ¶
· 1I
2
6 Clock
Thread 4
3
X0D25 ¶
· 1J
Blocks
X3
X0D26 ¶
· E
X0D27 ¶
· 4
X0D32 ¶
· rt
TDI
X0D33 ¶
· Po
C8
TDO
X0D28 ¶
·
rt
10 Timers
Thread 5
TCK
JTAG
X0D29 ¶
· F4
Po
TMS
X0D30 ¶
· rt
TRST_N
X0D31 ¶
·
B
Po
6
DEBUG_N
X0D34 ¶
·
1
1K
X0D35 ¶
·
rt
1L
Po
X0D36 ¶
· 1M
4 Locks
Thread 6
X0D37 ¶
· 1N
X0D38 ¶
· 1O
X2D00
X0D39 ¶
·
D
1A
X2
¶
·
1P
8
X2D01
X0D40 ¶
·
1B
rt
¶ ·X2D02
X0D41 ¶
· Po
7
A
¶ ·
Thread 7
Synchronizers
4
X2D03
X0D42 ¶
·
itch
¶ ·
Thread 0
64KB SRAM
rt
X2D08
X0D43 ¶
·
Sw
A
¶ ·
8
Po
¶ ·X2D09
rt
LA
X2D04
X0
B
0 ¶ ·
Po
4
X ¶ ·X2D05
rt
¶ ·X2D06
PLL_BYPASS
Po
Thread 1
Boot ROM
¶ ·X2D07
PLL_LOCK
1C
PLL_AVDD
¶ ·X2D10
A6
1D
PLL_AGND
¶
·X2D11
PLL
1
X2D12
CLK
rt
1E ¶
·
XC0_BS0
Po
1F
¶ ·X2D13
RST_N
Thread 2
8KB OTP
C
¶ ·X2D14
4
OTP_VPP
¶ ·X2D15
rt
X2D20
VDD
B
¶ ·
VDDIO
8
Po
¶ ·X2D21
GND
rt
LB
D
0 ¶ · X2D16
X1
Po
4
X
Security
¶ ·X2D17
s
Thread 3
rt
d
Register
¶ ·X2D18
Po
64KB SRAM
Thread 0
En
¶ ·X2D19
el
1G
itch
n
¶ ·X2D22
1H
Sw
an
¶
·X2D23
Boot ROM
Thread 1
h
1I
C
¶
·X2D24
6 Clock
1J
2
Thread 4
Blocks
¶
·X2D25
3
E ¶
·X2D26
8KB OTP
Thread 2
4 ¶
·X2D27
rt
s
¶
·X2D32
d
C
Po
8
En
¶
·X2D33
Security Register
Thread 3
rt
el
Thread 5
10 Timers
F ¶
·X2D28
n
itch
Po
4 ¶
·X2D29
an
Sw
rt
h
¶
·X2D30
B
C
6 Clock Blocks
Thread 4
6
Po ¶
·X2D31
2
1
3
1K
X2D34
rt
¶
·
1L
X2D35
Po
¶
·
Thread 6
4 Locks
10 Timers
Thread 5
1 ¶
M
·X2D36
1N¶
·X2D37
1 ¶
O
·X2D38
D
4 Locks
Thread 6
8
1P ¶
·X2D39
rt ¶
·X2D40
7
Po
Thread 7
Synchronizers
¶
·X2D41
7 Synchronizers
Thread 7
¶
·X2D42
¶
·X2D43
Document Number: 1087C
XS1-G04B-FB144 Datasheet
8
5
Product Overview
The XMOS XS1-G04B-FB144 is a powerful device that provides a simple design
process and highly-flexible solution to many applications. The device consists of
four XCores, each comprising an event-driven processor with tightly integrated
I/O and on-chip memory. The processors run mutiple tasks simultaneously using
hardware threads, each of which is guaranteed a slice of processing power and
can execute computational code, control software and I/O interfaces. Threads use
channels to exchange data within a core or across cores. The cores are connected
via an integrated switch network, which uses a proprietary physical layer protocol,
and which can also be used to add additional resources to a design. The I/O pins
are driven using intelligent ports that can serialize data, interpret strobe signals
and wait for scheduled times or events, making the device ideal for real-time
control applications.
The device can be configured using a set of software components that are rapidly
customized and composed. XMOS provides source code libraries for many standard
components. The device can be programmed using high-level languages such as
C/C++ and the XMOS-originated XC language. XC provides extensions to C that
simplify the control over concurrency, I/O and time.
The XMOS toolchain includes compilers, a simulator, debugger and static timing
analyzer. The combination of real-time software, a compiler and timing analyzer
enables the programmer to close timings on components of the design without a
detailed understanding of the hardware characteristics.
5.1
Threads, Synchronizers and Locks
Each XCore has up to eight active threads, which issue instructions down a shared
four-stage pipeline. Instructions from the active threads are issued round-robin. If
up to four threads are active, each thread is allocated a quarter of the processing
cycles. If more than four threads are active, each thread is allocated at least
1/n cycles (for n threads). Figure 1 shows the guaranteed thread performance
depending on the number of threads used.
Figure 1:
Speed Grade
Minimum MIPS per thread (for n threads)
Thread
1
2
3
4
5
6
7
8
performance
400 MHz
100
100
100
100
80
67
57
50
There is no way that the performance of a thread can be reduced below these
predicted levels. Because threads may be delayed on I/O, however, their unused
processor cycles can be taken by other threads. This means that for more than
four threads, the performance of each thread is often higher than the predicted
minimum.
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XS1-G04B-FB144 Datasheet
9
5.2
Channel Ends, Links and Switch
Threads communicate using point-to-point connections formed between two chan-
nel ends. Between cores, channel communications are implemented over XMOS
Links and routed through switches. The links operate in either 2bit/direction or
5bit/direction mode, depending on the amount of bandwidth required. Circuit
switched, streaming and packet switched data can both be supported efficiently.
Streams provide the fastest possible data rates between XCores (up to 250 MBit/s),
but each stream requires a single link to be reserved between switches on two
cores. All packet communications can be multiplexed onto a single link. A total of
eight 5bit links are available between every pair of cores.
Information on the supported routing topologies that can be used to connect
multiple devices together can be found in the XS1-G Link Performance and Design
Guides, document number X2215.
5.3
Ports and Clock Blocks
Ports provide an interface between the threads and I/O pins. The operation of
each port is synchronized to a clock block. A clock block can be connected to an
external clock input, or it can be run from the divided reference clock. A clock
block can also output its signal to a pin. On reset, each port is connected to clock
block 0, which runs from the reference clock.
The ports and links are multiplexed, allowing the pins to be configured for use
by ports of different widths or links. If an XMOS Link is enabled, the pins of the
underlying ports are disabled. If a port is enabled, it overrules ports with higher
widths that share the same pins. The pins on the wider port that are not shared
remain available for use when the narrower port is enabled. Ports always operate
at their specified width, even if they share pins with another port.
5.4
Timers
Timers are 32-bit counters that are relative to the reference clock. A timer is
defined to tick every 10 ns. This value is derived from the reference clock, which is
configured to tick at 100 MHz by default.
5.5
SRAM
Each XCore integrates a single 64 KB SRAM bank for both instructions and data. All
internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte
(8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed
within one core clock cycle. There is no dedicated external memory interface,
although data memory can be expanded through appropriate use of the ports.
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XS1-G04B-FB144 Datasheet
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5.6
OTP
Each XCore integrates 8 KB one-time programmable (OTP) memory along with a
security register that configures system wide security features. The OTP holds
data in 2k rows x 32-bit configuration which can be used to implement secure
bootloaders and store encryption keys. Data for the security register is loaded
from the OTP on power up.
5.6.1
Security Register
The security register enables the following security features:
· Secure Boot: The XCore is forced to boot from address 0 of the OTP, allowing
the XCore boot ROM to be bypassed (see §5.8). This feature can be used to
implement a secure bootloader which loads an encrypted image from external
flash, decrypts and CRC checks it with the processor, and discontinues the
boot process if the decryption or CRC check fails. XMOS provides a default
secure bootloader that can be written to the OTP along with secret decryption
keys.
· Disable JTAG: The JTAG interface is disabled, making it impossible for the
processor state or memory content to be accessed via the JTAG interface.
· Disable Link access: Other processors are forbidden access to the processor
state via the system switch.
Disabling both JTAG and Link access transforms a core into a "secure island"
with other cores free for non-secure user application code.
· Disable Global Debug access: Disables access to the SS_DEBUG pin.
· OTP Master and Sector Lock: Further access to the OTP is prevented by
setting the master lock. Locks can also be applied to each of the four OTP
sectors individually.
These security features provide a strong level of protection and are sufficient for
providing strong IP security.
5.7
PLL
The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input.
It should be supplied with a clock with monotonic rising edges and should be
stable before SS_RESET is taken high.
Many standard clock frequencies can be used with appropriate settings configured
into the PLL. At boot time, before the PLL can be reconfigured, the PLL multiplier
is set using the pins specified in the table in Figure 2. The PLL increases the
clock frequency to the core frequency used to run the processor data path and the
switch.
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Figure 2:
SS_PLL_BYPASS
PLL Multiplier
SS_CLK Input (MHz)
Boot Frequency (MHz)
PLL boot
0
20
12.5Â20
250Â400
modes
1
0.5
<100
<50
Further details on configuring the clock can be found in the XS1-G Clock Frequency
Control document, document number X140.
5.8
Boot ROM
The boot procedure is illustarted in Figure 3. If bit 5 of the security register is set
(see §5.6.1), the device boots from OTP. Otherwise, SS_XC0_BS[0] controls the boot
source.
Start
Boot ROM
Primary boot
No
Security Register
Bit [5] set
Yes
Copy OTP contents
Boot according to
OTP
to base of SRAM
boot source pins
Figure 3:
Boot
procedure
Execute program
SS_XC0_BS[0] operates as an input prior to the de-assertion of SS_RESET. The
device latches the value driven onto these pins on the rising edge (de-assertion)
of SS_RESET. The value driven should be static and configured using a pullup or
pulldown resistor, as the device drives the boot status on this pin after reset. The
value configured on this pin defines the boot mode, as described in Figure 4.
After reset is complete, SS_XC0_BS[0] becomes an output and indicates the boot
mode, as described in Figure 5.
5.9
JTAG
The JTAG module can be used for loading programs, boundary scan testing, in-
circuit source-level debugging and programming the OTP memory.
The JTAG chain structure is illustrated in Figure 6. Directly after reset, two TAP
controllers are present in the JTAG chain for each XCore: the boundary scan TAP
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XS1-G04B-FB144 Datasheet
12
SS_XC0_BS[0]
Boot Mode
0
Boot from SPI
PinA
Signal
Description
X0D00
MISO
Master In Slave Out
X0D01
SS
Slave Select
Figure 4:
X0D10
SCLK
Clock
Boot source
X0D11
MOSI
Master Out Slave In
pins
1
None: Device waits to be booted from JTAG
A The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. An SPI boot
program can be burned into OTP and used at any time.
Figure 5:
Boot mode
SS_XC0_BS[0]
Boot Confirmation
indication
0
Booted from SPI
pins
1
Booted from OTP or JTAG
and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that
can be used for boundary scan of the I/O pins. The chip TAP provides access into
the XCore, switch and OTP for loading code and debugging.
SS_TRST SS_TCK
SS_TD!
SS_TMS
SS_TDO
SS_TMS
SS_TCK
SS_TRST
SS_TDI
SS_TDO
MUX controller
NC
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
Figure 6:
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
JTAG chain
X0 JTAG
X1 JTAG
X2 JTAG
X3 JTAG
Switch JTAG
structure
The SS_TRST pin must be asserted low during and after power up for 100 ns. If
JTAG is not required, the SS_TRST pin can be tied to ground with a 1k resistor to
hold the JTAG module in reset.
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The JTAG device identification register can be read by using the IDCODE instruction.
Its contents are specified in Figure 7.
Bit31
Device Identification Register
Bit0
Figure 7:
Version
Part Number
Manufacturer Identity
1
ICODE return
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
value
0
0
1
0
4
6
3
3
The JTAG usercode register can be read by using the USERCODE instruction. Its
contents are specified in Figure 8. The OTP User ID field is read from bits [22:31]
of the security register on XCore 0 (all zero on unprogrammed devices).
Bit31
Usercode Register
Bit0
Figure 8:
OTP User ID
Unused
Silicon Revision
USERCODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
return value
0
0
0
2
8
0
0
0
5.10
Power Supplies
The device has the following types of power supply pins:
· VDD pins for the chip core
· IO VDD pins for the I/O lines
· SS_PLL_AVDD pins for the PLL
· OTP_VPP pins for faster programming the OTP (optional)
Several pins of each type are provided to minimize the effect of inductance within
the package, all of which must be connected. The power supplies must be brought
up monotonically and input voltages must not exceed specification at any time.
The VDD supply must ramp from 0 V to its final value within 10 ms to ensure
correct startup.
The IO VDD supply must ramp to its final value before VDD reaches 0.4 V.
The SS_PLL_AVDD supply should be separated from the other noisier supplies on
the board. The PLL requires a very clean power supply, and a low pass filter (for
example, a 4.7 resistor and 1 µF multi-layer ceramic capacitor) is recommended
on this pin.
The SS_OTP_VPP supply can be optionally provided for faster OTP programming
times, otherwise an internal charge pump is used.
The following ground pins are provided:
· PLL_AGND for PLL_AVDD
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XS1-G04B-FB144 Datasheet
14
· GND for all other supplies
All ground pins must be connected directly to the board ground.
The VDD and IO VDD supplies should be decoupled close to the chip by several
100 nF low inductance multi-layer ceramic capacitors between the supplies and
GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The
ground side of the decoupling capacitors should have as short a path back to the
GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be
placed on each of these supplies.
SS_RESET is an active-low asynchronous-assertion global reset signal. Following a
reset, the PLL re-establishes lock after which the device boots up according to the
boot mode (see §5.8). SS_RESET and must be asserted low during and after power
up for 100 ns.
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XS1-G04B-FB144 Datasheet
15
6
DC and Switching Characteristics
6.1
Operating Conditions
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
VDD
Core DC supply voltage
0.95
1.00
1.05
V
VDDIO
I/O DC supply voltage
3.00
3.30
3.60
V
PLL_AVDD
PLL analog supply
0.95
1.00
1.05
V
OTP_VPP
OTP external programming
6.18
6.50
6.83
V
voltage (optional program only)
Cl
XCore I/O load capacitance
25
pF
Ambient operating
0
70
°C
Ta
temperature (Commercial)
Ambient operating
-40
85
°C
Figure 9:
temperature (Industrial)
Operating
Tj
Junction temperature
125
°C
conditions
Tstg
Storage temperature
-65
150
°C
6.2
DC Characteristics
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
V(IH)
Input high voltage
2.00
5.50
V
A, B
V(IL)
Input low voltage
-0.30
0.80
V
A, B
Figure 10:
V(OH)
Output high voltage
2.40
V
A, B
DC character-
V(OL)
Output low voltage
0.40
V
A, B
istics
R(PU)
Pull-up resistance
100K
A, C
A All pins except power supply pins.
B Internal pull-up resistors are fitter to general-purpose I/O pins.
C Use for unused I/O only. The internal pull-up resistor is not recommended as a substitute for an
external pull-up resistor.
6.3
ESD Stress Voltage
Figure 11:
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
ESD stress
HBM
Human body model
-2.00
2.00
KV
voltage
MM
Machine model
-200
200
V
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XS1-G04B-FB144 Datasheet
16
6.4
Reset Timing
Symbol
Parameters
MIN
TYP
MAX
UNITS
Notes
T(RST)
Reset pulse width
100
ns
Figure 12:
T(PLLLOCK)
PLL lock
1
ms
Reset timing
T(INIT)
Initialization time
<100
µs
A
A Shows the time taken to start booting after SS_RESET has gone high.
6.5
Quiescent Current
Figure 13:
Symbol
Parameter
MIN TYP MAX
UNITS
Notes
Quiescent
I(DDCQ)
Quiescent VDD current
120
mA
current
I(PLLQ)
Quiescent PLL current
4
mA
6.6
Power Consumption
Figure 14:
Symbol
Parameter
MIN TYP MAX
UNITS
Notes
Core currents
PD
Core power dissipation
1.6
Watts
A, B, C, D
A Use for budgetary purposes only.
B Assumes typical core and I/O voltages operating at 400 MHz with nominal activity on all cores.
C PD(TYP) value is the usage power consumption under typical operating conditions.
D PD(TYP) value includes quiescent current.
The core power consumption of the device is highly application dependent and
should be used for budgetary purposes only. More detailed power analysis can be
found in the XS1-G Power Consumption document, document number X1423.
6.7
Clock
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
f
Frequency
12.5
20
20
MHz
Figure 15:
SR
Slew rate
1
2
ns
Clock
f(MAX)
System clock frequency
400
MHz
Further details can be found in the XS1-G Clock Frequency Control document,
document number X140.
The OTP may be programmed using its internal charge pump or by supplying a
6.5V VPP programming voltage on the SS_OTP_VPP pin. Unless a programming
cycle is underway the SS_OTP_VPP pins should be left undriven.
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XS1-G04B-FB144 Datasheet
17
6.8
XCore I/O AC Characteristics
Symbol
Parameter
MIN TYP MAX UNITS
Notes
T(XOVALID)
Input data valid window
8
ns
Figure 16:
T(XOINVALID)
Output data invalid window
9
ns
I/O AC char-
T(XIFMAX)
Rate at which data can be sampled
60
MHz
acteristics
with respect to an external clock
The input valid window parameter relates to the capability of the device to capture
data input to the chip with respect to an external clock source. It is calculated as the
sum of the input setup time and input hold time with respect to the external clock
as measured at the pins. The output invalid window specifies the time for which
an output is invalid with respect to the external clock. Note that these parameters
are specified as a window rather than absolute numbers since the device provides
functionality to delay the incoming clock with respect to the incoming data.
Information on interfacing to high-speed synchronous interfaces can be found in
the XS1 Port I/O Timing document, document number X9122.
6.9
XMOS Link Performance
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
B(2blinkP)
2b link bandwidth (packetized)
87
MBit/s
A, B
Figure 17:
B(5blinkP)
5b link bandwidth (packetized)
217
MBit/s
A, B
Link
B(2blinkS)
2b link bandwidth (streaming)
100
MBit/s
B
performance
B(5blinkS)
5b link bandwidth (streaming)
250
MBit/s
B
A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header
and payload.
B 7.5 ns symbol time.
The asynchronous nature of links means that the relative phasing of SS_CLK clocks
is not important in a multi-clock system, providing each meets the required stability
criteria.
6.10
JTAG Timing
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
T(TCK)
TCK period
30
ns
T(SETUP)
TDO to TCK setup time
5
ns
A
Figure 18:
T(HOLD)
TDO to TCK hold time
10
ns
A
JTAG timing
T(DELAY)
TCK to output delay
15
ns
B
A Timing applies to SS_TMS, SS_TRST and SS_TDI inputs.
B Timing applies to SS_TDO output.
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XS1-G04B-FB144 Datasheet
18
All JTAG operations are synchronous to SS_TCK apart from the global asynchronous
reset SS_TRST.
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XS1-G04B-FB144 Datasheet
19
7
Package Information
Document Number: 1087C
XS1-G04B-FB144 Datasheet
20
7.1
Part Marking
Product code
Qualification/Speed Grade (optional)
XS1ÂG04BÂFB144Â
Q S
XMOS-YYWW
Manufacturing date code
LLLLLL.LL
Figure 19:
Part marking
Lot code
scheme
8
Ordering Information
Figure 20:
Product Code
Qualification
Speed Grade
Orderable
XS1ÂG04BÂFB144ÂC4
Commercial
400 MHz
part numbers
XS1ÂG04BÂFB144ÂI4
Industrial
400 MHz
9
Development Tools
XMOS provides a comprehensive suite of development tools. Source files, timing
scripts and a board design file are input to the compiler toolchain which produces
a binary executable. This executable file can be simulated, loaded onto the device
and debugged over JTAG, programmed into flash memory on the board or written
to OTP memory on the device. The tools can also encrypt the flash image and write
the decrpytion key securely to OTP memory.
The tools can be driven from either a graphical development environment or the
command line and are supported on Windows, Linux and MacOS X. The tools
are available at no cost from xmos.com/tools. Information on using the tools is
provided in a separate user guide, document number X1066.
10
Addendum: XMOS USB Interface
XMOS provides a low-level USB interface for connecting the device to a USB
transceiver using the UTMI+ Low Pin Interface (ULPI). The ULPI signals must be
connected to the pins named in Figure 21. Note also that some ports on the same
Document Number: 1087C
XS1-G04B-FB144 Datasheet
21
core are used internally and are not available for use when the USB driver is active
(they are available otherwise).
Pin
Signal
Pin
Signal
Pin
Signal
XnD02
XnD16
ULPI_DATA[2]
XnD30
XnD03
XnD17
ULPI_DATA[3]
XnD31
XnD04
XnD18
ULPI_DATA[4]
XnD32
XnD05
XnD19
ULPI_DATA[5]
XnD33
Unavailable
XnD06
XnD20
ULPI_DATA[6]
XnD37
XnD07
XnD21
ULPI_DATA[7]
XnD38
Unavailable
XnD08
XnD22
ULPI_DIR
XnD39
XnD09
XnD23
ULPI_CLK
XnD40
Figure 21:
XnD12
ULPI_STP
XnD26
XnD41
ULPI signals
provided by
XnD13
ULPI_NXT
XnD27
XnD42
Unavailable
the XMOS
XnD14
ULPI_DATA[0]
XnD28
XnD43
USB driver
XnD15
ULPI_DATA[1]
XnD29
11
Associated Design Documentation
Document Title
Information
Document Number
XS1-G Hardware Design Checklist
Board design checklist
X0124
Device Package User Guide
Land pattern, solder paste, ground
X4979
recommendations
Estimating Power Consumption For
Power consumption
X1423
XS1-G Devices
Programming XC on XMOS Devices
Timers, ports, clocks, threads and
X1066
channels
XMOS Tools User Guide
Compilers, assembler and
X1089
linker/mapper
Timing analyzer and debugger
Flash and OTP programming utilities
· Example schematic diagrams detailing minimal system configurations are available from
http://www.xmos.com/support/silicon.
Document Number: 1087C
XS1-G04B-FB144 Datasheet
22
12
Related Documentation
Document Title
Information
Document Number
The XMOS XS1 Architecture
ISA manual
X0102
XS1 Port I/O Timing
Port timings
X9122
XS1-G System Specification
Link, switch and system information
X2725
XS1-G Link Performance and Design
Link timings
X2215
Guidelines
XS1-G Clock Frequency Control
Advanced clock control
X1340
Document Number: 1087C
XS1-G04B-FB144 Datasheet
23
13
Revision History
The page numbers in this section refer to this document.
Rev. 1087CÂ05/11
1. Revised format.
2. Standard XMOS Link format XnLn on page 4.
Rev. 1087BÂ01/11
1. Replaced "Port Pin Table" with "Signal Description" on page 4.
2. Updated "ULPI" on page 20 with set of disabled signals.
3. Removed "Device Configuration".
4. Added "Associated Design Documentation" on page 21.
5. Clock frequencies of betweeen 20 MHz and 25 MHz are not supported.
6. Removed documentation of numerous JTAG commands, which were incorrect.
7. Updated Figure 10 in "DC Characteristics" on page 15 by removing rows for I(OH) and
I(OL).
8. Updated Figure 17 in "XMOS Link Performance' on page 17 by removing rows for B(2link)
and B(5link), and adding rows for B(2linkP), B(5linkP), B(2linkS) and B(5linkS).
9. Renamed IO VSS signals to VSS.
Rev. 1087AÂ06/10
1. Revised format.
2. Updated "Power Consumption" on page 16.
Copyright © 2010 XMOS Limited, All Rights Reserved.
XMOS Limited is the owner or licensee of this design, code, or Information (collectively, the "Information")
and is providing it to you "AS IS" with no warranty of any kind, express or implied and shall have no
liability in relation to its use. XMOS Limited makes no representation that the Information, or any particular
implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Limited in the United Kingdom and other
countries, and may not be used without written permission. All other trademarks are property of their
respective owners. Where those designations appear in this book, and XMOS was aware of a trademark claim,
the designations have been printed with initial capital letters or in all capitals.
Document Number: 1087C
Publication Date: 2011/05/16
Copyright © 2010 XMOS Limited, All Rights Reserved.
XS1-G04B-FB144 Datasheet
1
Table of Contents
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
5
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
6
DC and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
Addendum: XMOS USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Associated Design Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TO OUR VALUED CUSTOMERS
It is our intention to provide you with accurate and comprehensive documentation for the hardware and
software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/.
XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you "AS IS" with
no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names mentioned in this document
are the trademarks or registered trademarks of their respective owners.
Document Number: 1087C
XS1-G04B-FB144 Datasheet
2
1
Features
· Quad-Core Device with Advanced Multi-Threaded RISC Architecture
· Up to 1600 MIPS shared between up to 32 real-time threads
· Each thread has:
-- Guaranteed throughput of between 1/4 and 1/8 of core MIPS
-- 16x32bit dedicated registers
· 159 high-density 16/32-bit instructions
-- All have single clock-cycle execution (except for divide)
-- High-performance DSP (32x3264-bit MAC) and cryptographic instructions
· Programmable I/O
· 88 general-purpose I/O pins, configurable as input, output or bi-directional ports
· Port sampling rates of up to 60 MHz with respect to an external clock
· 128 channel ends for communication with other threads, on or off-chip
· Non-Volatile Memory
· 256KB internal single-cycle SRAM (max 64KB per core) for code and data storage
· 32KB internal OTP (max 8KB per core) for application boot code
· JTAG Module for On-Chip Debug
· Security Features
· Programming lock disables debug and prevents read-back of memory contents
· AES bootloader ensures secrecy of IP held on external flash memory
· Ambient Temperature Range
· Commercial qualification: 0 °C to 70 °C
· Industrial qualification: -40 °C to 85 °C
· Speed Grade
· 400 MHz part: 400 MIPS
· 144-pin FBGA package 0.8 mm pitch
Document Number: 1087C
XS1-G04B-FB144 Datasheet
3
2
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
A
IO VDD
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
VSS
B
X0D33
VSS
X0D18
X0D19
X0D20
IO VDD
VSS
X0D21
X0D22
X0D23
IO VDD
X2D24
C
X0D32
X0D17
VDD
X0D06
X0D07
X0D08
X0D09
X0D10
X0D11
VDD
X2D12
X2D25
SS_PLL_
SS_
OTP_
SS_XC0_ SS_XC_
D
X0D31
X0D16
X0D05
BYPASS
RESET
VDD
VPP
BS[0]
CFG[0]
X2D00
X2D13
X2D26
E
X0D30
X0D15
X0D04
SS_CLK
SS_
VSS
VSS
VSS
VSS
DEBUG
X2D01
X2D14
X2D27
F
X0D29
IO VDD
SS_PLL_
X0D03
AGND
VSS
VSS
VSS
VSS
VDD
X2D02
VSS
X2D28
SS_
G
X0D28
VSS
X0D02
VDD
VSS
VSS
VSS
VSS
TEST_
X2D03
IO VDD
X2D29
ENA
SS_PLL_
H
X0D27
X0D14
X0D01
AVDD
VSS
VSS
VSS
VSS
SS_TCK
X2D04
X2D15
X2D30
SS_PLL_
J
X0D26
X0D13
X0D00
LOCK
SS_TMS
SS_TDO
VDD
SS_TDI
SS_TRST
X2D05
X2D16
X2D31
K
X0D25
X0D12
VDD
X2D11
X2D10
X2D09
X2D08
X2D07
X2D06
VDD
X2D17
X2D32
L
X0D24
IO VDD
X2D23
X2D22
X2D21
VSS
IO VDD
X2D20
X2D19
X2D18
VSS
X2D33
M
VSS
X2D43
X2D42
X2D41
X2D40
X2D39
X2D38
X2D37
X2D36
X2D35
X2D34
IO VDD
Document Number: 1087C
XS1-G04B-FB144 Datasheet
4
3
Signal Description
Module
Signal
Function
Type
Active
Properties
PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger, OT=Output Tristate, S=Switchable
RS=Required for SPI boot (§5.8), RU=Required for USB-enabled devices (§10)
VDD
Digital core power
PWR
--
VSS
Digital ground
GND
--
IO VDD
Digital I/O power
PWR
--
Power
SS_PLL_AGND
Analog ground for PLL
GND
--
SS_PLL_AVDD
Analog PLL power
PWR
--
OTP_VPP
OTP programming voltage
PWR
--
SS_RESET
Global reset input
Input
--
PU, ST
SS_CLK
PLL reference clock
Input
--
PD, ST
PLL
SS_PLL_BYPASS
PLL bypass
Input
--
PD
SS_XC0_BS[0:0]
Boot status (core 0)
I/O
--
PU
SS_TDI
Test data input
Input
--
PU, ST
SS_TDO
Test data output
Output
--
PD
SS_TMS
Test mode select
Input
--
PU, ST
JTAG
SS_TRST
Test reset input
Input
--
PU, ST
SS_TCK
Test clock
Input
--
PU, ST
SS_DEBUG
Multi-chip debug
I/O
--
PU
X0D00
P1A0
I/O
--
RS
X0D01
X0LA4i
5b
P1B0
I/O
--
RS
X0D02
X0LA3i
5b
P4A0 P8A0 P16A0 P32A20
I/O
--
RU
X0D03
X0LA2i
5b
P4A1 P8A1 P16A1 P32A21
I/O
--
RU
X0D04
X0LA1i
2b/5b
P4B0 P8A2 P16A2 P32A22
I/O
--
RU
X0D05
X0LA0i
2b/5b
P4B1 P8A3 P16A3 P32A23
I/O
--
RU
X0D06
X0LA0o
2b/5b
P4B2 P8A4 P16A4 P32A24
I/O
--
RU
X0D07
X0LA1o
2b/5b
P4B3 P8A5 P16A5 P32A25
I/O
--
RU
X0D08
X0LA2o
5b
P4A2 P8A6 P16A6 P32A26
I/O
--
RU
X0D09
X0LA3o
5b
P4A3 P8A7 P16A7 P32A27
I/O
--
RU
X0D10
X0LA4o
XCore 0 I/O
5b
P1C0
I/O
--
RS
X0D11
P1D0
I/O
--
RS
X0D12
P1E0
I/O
--
RU
X0D13
X0LB4i
5b
P1F0
I/O
--
RU
X0D14
X0LB3i
5b
P4C0 P8B0 P16A8 P32A28
I/O
--
RU
X0D15
X0LB2i
5b
P4C1 P8B1 P16A9 P32A29
I/O
--
RU
X0D16
X0LB1i
2b/5b
P4D0 P8B2 P16A10
I/O
--
RU
X0D17
X0LB0i
2b/5b
P4D1 P8B3 P16A11
I/O
--
RU
X0D18
X0LB0o
2b/5b
P4D2 P8B4 P16A12
I/O
--
RU
X0D19
X0LB1o
2b/5b
P4D3 P8B5 P16A13
I/O
--
RU
X0D20
X0LB2o
5b
P4C2 P8B6 P16A14 P32A30
I/O
--
RU
X0D21
X0LB3o
5b
P4C3 P8B7 P16A15 P32A31
I/O
--
RU
(continued)
Document Number: 1087C
XS1-G04B-FB144 Datasheet
5
Module
Name
Function
Type
Active
Properties
X0D22
X0LB4o
5b
P1G0
I/O
--
RU
X0D23
P1H0
I/O
--
RU
X0D24
P1I0
I/O
--
X0D25
P1J0
I/O
--
X0D26
P4E0 P8C0 P16B0
I/O
--
RU
X0D27
P4E1 P8C1 P16B1
I/O
--
RU
X0D28
P4F0 P8C2 P16B2
I/O
--
RU
X0D29
P4F1 P8C3 P16B3
I/O
--
RU
X0D30
P4F2 P8C4 P16B4
I/O
--
RU
X0D31
P4F3 P8C5 P16B5
I/O
--
RU
X0D32
P4E2 P8C6 P16B6
I/O
--
R
XCore 0 I/O
U
X0D33
P4E3 P8C7 P16B7
I/O
--
RU
X0D34
P1K0
I/O
--
X0D35
P1L0
I/O
--
X0D36
P1M0
P8D0 P16B8
I/O
--
X0D37
P1N0
P8D1 P16B9
I/O
--
RU
X0D38
P1O0
P8D2 P16B10
I/O
--
RU
X0D39
P1P0
P8D3 P16B11
I/O
--
RU
X0D40
P8D4 P16B12
I/O
--
RU
X0D41
P8D5 P16B13
I/O
--
RU
X0D42
P8D6 P16B14
I/O
--
RU
X0D43
P8D7 P16B15
I/O
--
RU
X2D00
P1A0
I/O
--
X2D01
X2LA4i
5b
P1B0
I/O
--
X2D02
X2LA3i
5b
P4A0 P8A0 P16A0 P32A20
I/O
--
RU
X2D03
X2LA2i
5b
P4A1 P8A1 P16A1 P32A21
I/O
--
RU
X2D04
X2LA1i
2b/5b
P4B0 P8A2 P16A2 P32A22
I/O
--
RU
X2D05
X2LA0i
2b/5b
P4B1 P8A3 P16A3 P32A23
I/O
--
RU
X2D06
X2LA0o
2b/5b
P4B2 P8A4 P16A4 P32A24
I/O
--
RU
X2D07
X2LA1o
2b/5b
P4B3 P8A5 P16A5 P32A25
I/O
--
RU
X2D08
X2LA2o
5b
P4A2 P8A6 P16A6 P32A26
I/O
--
RU
X2D09
X2LA3o
5b
P4A3 P8A7 P16A7 P32A27
I/O
--
RU
XCore 2 I/O
X2D10
X2LA4o
5b
P1C0
I/O
--
X2D11
P1D0
I/O
--
X2D12
P1E0
I/O
--
RU
X2D13
X2LB4i
5b
P1F0
I/O
--
RU
X2D14
X2LB3i
5b
P4C0 P8B0 P16A8 P32A28
I/O
--
RU
X2D15
X2LB2i
5b
P4C1 P8B1 P16A9 P32A29
I/O
--
RU
X2D16
X2LB1i
2b/5b
P4D0 P8B2 P16A10
I/O
--
RU
X2D17
X2LB0i
2b/5b
P4D1 P8B3 P16A11
I/O
--
RU
X2D18
X2LB0o
2b/5b
P4D2 P8B4 P16A12
I/O
--
RU
X2D19
X2LB1o
2b/5b
P4D3 P8B5 P16A13
I/O
--
RU
X2D20
X2LB2o
5b
P4C2 P8B6 P16A14 P32A30
I/O
--
RU
(continued)
Document Number: 1087C
XS1-G04B-FB144 Datasheet
6
Module
Name
Function
Type
Active
Properties
X2D21
X2LB3o
5b
P4C3 P8B7 P16A15 P32A31
I/O
--
RU
X2D22
X2LB4o
5b
P1G0
I/O
--
RU
X2D23
P1H0
I/O
--
RU
X2D24
P1I0
I/O
--
X2D25
P1J0
I/O
--
X2D26
P4E0 P8C0 P16B0
I/O
--
RU
X2D27
P4E1 P8C1 P16B1
I/O
--
RU
X2D28
P4F0 P8C2 P16B2
I/O
--
RU
X2D29
P4F1 P8C3 P16B3
I/O
--
RU
X2D30
P4F2 P8C4 P16B4
I/O
--
RU
X2D31
P4F3 P8C5 P16B5
I/O
--
RU
XCore 2 I/O
X2D32
P4E2 P8C6 P16B6
I/O
--
RU
X2D33
P4E3 P8C7 P16B7
I/O
--
RU
X2D34
P1K0
I/O
--
X2D35
P1L0
I/O
--
X2D36
P1M0
P8D0 P16B8
I/O
--
X2D37
P1N0
P8D1 P16B9
I/O
--
RU
X2D38
P1O0
P8D2 P16B10
I/O
--
RU
X2D39
P1P0
P8D3 P16B11
I/O
--
RU
X2D40
P8D4 P16B12
I/O
--
RU
X2D41
P8D5 P16B13
I/O
--
RU
X2D42
P8D6 P16B14
I/O
--
RU
X2D43
P8D7 P16B15
I/O
--
RU
SS_PLL_LOCK
Reserved (do not connect)
Output
--
PD
Reserved
SS_TEST_ENA
Reserved (tie to VSS)
Input
--
PD
SS_XC_CFG[0:0]
Reserved (tie to IO VDD)
Input
--
PD
Document Number: 1087C
XS1-G04B-FB144 Datasheet
7
4
Block Diagram
X0D00 ¶
· 1A
X0D01 ¶ ·
1B
Thread 0
64KB SRAM
X0D02 ¶ ·
64KB SRAM
Thread 0
A
X0D03 ¶ ·
4
X0D08 ¶ ·
rt
Thread 1
Boot ROM
X0D09 ¶ ·
A
Po
8
LA
X0D04 ¶ · 0
rt
X
X0D05 ¶ ·
B
Po
4
Thread 2
8KB OTP
X0D06 ¶ ·
rt
Boot ROM
Thread 1
s
X0D07 ¶ ·
Po
d
En
X0D10 ¶ ·
Security Register
1C
Thread 3
el
X0D11 ¶
·
A
1D
6
itch
n
X0D12 ¶
·
1
1E
an
rt
Sw
h
X0D13 ¶ ·
Thread 4
6 Clock Blocks
1F
Po
8KB OTP
Thread 2
C
X0D14 ¶ ·
23
X0D15 ¶ ·
C4
Thread 5
10 Timers
X0D20 ¶ ·
rt
B
X0D21 ¶ ·
Po
8
LB
X0D16 ¶ · 0
rt
X
Security
s
Thread 6
4 Locks
X0D17 ¶ ·
D
Po
Thread 3
d
4
Register
X0D18 ¶ ·
En
rt
X0D19 ¶ ·
el
Po
n
itch
Thread 7
7 Synchronizers
X0D22 ¶ ·
1G
an
Sw
X0D23 ¶
·
h
1H
C
X0D24 ¶
· 1I
2
6 Clock
Thread 4
3
X0D25 ¶
· 1J
Blocks
X3
X0D26 ¶
· E
X0D27 ¶
· 4
X0D32 ¶
· rt
TDI
X0D33 ¶
· Po
C8
TDO
X0D28 ¶
·
rt
10 Timers
Thread 5
TCK
JTAG
X0D29 ¶
· F4
Po
TMS
X0D30 ¶
· rt
TRST_N
X0D31 ¶
·
B
Po
6
DEBUG_N
X0D34 ¶
·
1
1K
X0D35 ¶
·
rt
1L
Po
X0D36 ¶
· 1M
4 Locks
Thread 6
X0D37 ¶
· 1N
X0D38 ¶
· 1O
X2D00
X0D39 ¶
·
D
1A
X2
¶
·
1P
8
X2D01
X0D40 ¶
·
1B
rt
¶ ·X2D02
X0D41 ¶
· Po
7
A
¶ ·
Thread 7
Synchronizers
4
X2D03
X0D42 ¶
·
itch
¶ ·
Thread 0
64KB SRAM
rt
X2D08
X0D43 ¶
·
Sw
A
¶ ·
8
Po
¶ ·X2D09
rt
LA
X2D04
X0
B
0 ¶ ·
Po
4
X ¶ ·X2D05
rt
¶ ·X2D06
PLL_BYPASS
Po
Thread 1
Boot ROM
¶ ·X2D07
PLL_LOCK
1C
PLL_AVDD
¶ ·X2D10
A6
1D
PLL_AGND
¶
·X2D11
PLL
1
X2D12
CLK
rt
1E ¶
·
XC0_BS0
Po
1F
¶ ·X2D13
RST_N
Thread 2
8KB OTP
C
¶ ·X2D14
4
OTP_VPP
¶ ·X2D15
rt
X2D20
VDD
B
¶ ·
VDDIO
8
Po
¶ ·X2D21
GND
rt
LB
D
0 ¶ · X2D16
X1
Po
4
X
Security
¶ ·X2D17
s
Thread 3
rt
d
Register
¶ ·X2D18
Po
64KB SRAM
Thread 0
En
¶ ·X2D19
el
1G
itch
n
¶ ·X2D22
1H
Sw
an
¶
·X2D23
Boot ROM
Thread 1
h
1I
C
¶
·X2D24
6 Clock
1J
2
Thread 4
Blocks
¶
·X2D25
3
E ¶
·X2D26
8KB OTP
Thread 2
4 ¶
·X2D27
rt
s
¶
·X2D32
d
C
Po
8
En
¶
·X2D33
Security Register
Thread 3
rt
el
Thread 5
10 Timers
F ¶
·X2D28
n
itch
Po
4 ¶
·X2D29
an
Sw
rt
h
¶
·X2D30
B
C
6 Clock Blocks
Thread 4
6
Po ¶
·X2D31
2
1
3
1K
X2D34
rt
¶
·
1L
X2D35
Po
¶
·
Thread 6
4 Locks
10 Timers
Thread 5
1 ¶
M
·X2D36
1N¶
·X2D37
1 ¶
O
·X2D38
D
4 Locks
Thread 6
8
1P ¶
·X2D39
rt ¶
·X2D40
7
Po
Thread 7
Synchronizers
¶
·X2D41
7 Synchronizers
Thread 7
¶
·X2D42
¶
·X2D43
Document Number: 1087C
XS1-G04B-FB144 Datasheet
8
5
Product Overview
The XMOS XS1-G04B-FB144 is a powerful device that provides a simple design
process and highly-flexible solution to many applications. The device consists of
four XCores, each comprising an event-driven processor with tightly integrated
I/O and on-chip memory. The processors run mutiple tasks simultaneously using
hardware threads, each of which is guaranteed a slice of processing power and
can execute computational code, control software and I/O interfaces. Threads use
channels to exchange data within a core or across cores. The cores are connected
via an integrated switch network, which uses a proprietary physical layer protocol,
and which can also be used to add additional resources to a design. The I/O pins
are driven using intelligent ports that can serialize data, interpret strobe signals
and wait for scheduled times or events, making the device ideal for real-time
control applications.
The device can be configured using a set of software components that are rapidly
customized and composed. XMOS provides source code libraries for many standard
components. The device can be programmed using high-level languages such as
C/C++ and the XMOS-originated XC language. XC provides extensions to C that
simplify the control over concurrency, I/O and time.
The XMOS toolchain includes compilers, a simulator, debugger and static timing
analyzer. The combination of real-time software, a compiler and timing analyzer
enables the programmer to close timings on components of the design without a
detailed understanding of the hardware characteristics.
5.1
Threads, Synchronizers and Locks
Each XCore has up to eight active threads, which issue instructions down a shared
four-stage pipeline. Instructions from the active threads are issued round-robin. If
up to four threads are active, each thread is allocated a quarter of the processing
cycles. If more than four threads are active, each thread is allocated at least
1/n cycles (for n threads). Figure 1 shows the guaranteed thread performance
depending on the number of threads used.
Figure 1:
Speed Grade
Minimum MIPS per thread (for n threads)
Thread
1
2
3
4
5
6
7
8
performance
400 MHz
100
100
100
100
80
67
57
50
There is no way that the performance of a thread can be reduced below these
predicted levels. Because threads may be delayed on I/O, however, their unused
processor cycles can be taken by other threads. This means that for more than
four threads, the performance of each thread is often higher than the predicted
minimum.
Document Number: 1087C
XS1-G04B-FB144 Datasheet
9
5.2
Channel Ends, Links and Switch
Threads communicate using point-to-point connections formed between two chan-
nel ends. Between cores, channel communications are implemented over XMOS
Links and routed through switches. The links operate in either 2bit/direction or
5bit/direction mode, depending on the amount of bandwidth required. Circuit
switched, streaming and packet switched data can both be supported efficiently.
Streams provide the fastest possible data rates between XCores (up to 250 MBit/s),
but each stream requires a single link to be reserved between switches on two
cores. All packet communications can be multiplexed onto a single link. A total of
eight 5bit links are available between every pair of cores.
Information on the supported routing topologies that can be used to connect
multiple devices together can be found in the XS1-G Link Performance and Design
Guides, document number X2215.
5.3
Ports and Clock Blocks
Ports provide an interface between the threads and I/O pins. The operation of
each port is synchronized to a clock block. A clock block can be connected to an
external clock input, or it can be run from the divided reference clock. A clock
block can also output its signal to a pin. On reset, each port is connected to clock
block 0, which runs from the reference clock.
The ports and links are multiplexed, allowing the pins to be configured for use
by ports of different widths or links. If an XMOS Link is enabled, the pins of the
underlying ports are disabled. If a port is enabled, it overrules ports with higher
widths that share the same pins. The pins on the wider port that are not shared
remain available for use when the narrower port is enabled. Ports always operate
at their specified width, even if they share pins with another port.
5.4
Timers
Timers are 32-bit counters that are relative to the reference clock. A timer is
defined to tick every 10 ns. This value is derived from the reference clock, which is
configured to tick at 100 MHz by default.
5.5
SRAM
Each XCore integrates a single 64 KB SRAM bank for both instructions and data. All
internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte
(8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed
within one core clock cycle. There is no dedicated external memory interface,
although data memory can be expanded through appropriate use of the ports.
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5.6
OTP
Each XCore integrates 8 KB one-time programmable (OTP) memory along with a
security register that configures system wide security features. The OTP holds
data in 2k rows x 32-bit configuration which can be used to implement secure
bootloaders and store encryption keys. Data for the security register is loaded
from the OTP on power up.
5.6.1
Security Register
The security register enables the following security features:
· Secure Boot: The XCore is forced to boot from address 0 of the OTP, allowing
the XCore boot ROM to be bypassed (see §5.8). This feature can be used to
implement a secure bootloader which loads an encrypted image from external
flash, decrypts and CRC checks it with the processor, and discontinues the
boot process if the decryption or CRC check fails. XMOS provides a default
secure bootloader that can be written to the OTP along with secret decryption
keys.
· Disable JTAG: The JTAG interface is disabled, making it impossible for the
processor state or memory content to be accessed via the JTAG interface.
· Disable Link access: Other processors are forbidden access to the processor
state via the system switch.
Disabling both JTAG and Link access transforms a core into a "secure island"
with other cores free for non-secure user application code.
· Disable Global Debug access: Disables access to the SS_DEBUG pin.
· OTP Master and Sector Lock: Further access to the OTP is prevented by
setting the master lock. Locks can also be applied to each of the four OTP
sectors individually.
These security features provide a strong level of protection and are sufficient for
providing strong IP security.
5.7
PLL
The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input.
It should be supplied with a clock with monotonic rising edges and should be
stable before SS_RESET is taken high.
Many standard clock frequencies can be used with appropriate settings configured
into the PLL. At boot time, before the PLL can be reconfigured, the PLL multiplier
is set using the pins specified in the table in Figure 2. The PLL increases the
clock frequency to the core frequency used to run the processor data path and the
switch.
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Figure 2:
SS_PLL_BYPASS
PLL Multiplier
SS_CLK Input (MHz)
Boot Frequency (MHz)
PLL boot
0
20
12.5Â20
250Â400
modes
1
0.5
<100
<50
Further details on configuring the clock can be found in the XS1-G Clock Frequency
Control document, document number X140.
5.8
Boot ROM
The boot procedure is illustarted in Figure 3. If bit 5 of the security register is set
(see §5.6.1), the device boots from OTP. Otherwise, SS_XC0_BS[0] controls the boot
source.
Start
Boot ROM
Primary boot
No
Security Register
Bit [5] set
Yes
Copy OTP contents
Boot according to
OTP
to base of SRAM
boot source pins
Figure 3:
Boot
procedure
Execute program
SS_XC0_BS[0] operates as an input prior to the de-assertion of SS_RESET. The
device latches the value driven onto these pins on the rising edge (de-assertion)
of SS_RESET. The value driven should be static and configured using a pullup or
pulldown resistor, as the device drives the boot status on this pin after reset. The
value configured on this pin defines the boot mode, as described in Figure 4.
After reset is complete, SS_XC0_BS[0] becomes an output and indicates the boot
mode, as described in Figure 5.
5.9
JTAG
The JTAG module can be used for loading programs, boundary scan testing, in-
circuit source-level debugging and programming the OTP memory.
The JTAG chain structure is illustrated in Figure 6. Directly after reset, two TAP
controllers are present in the JTAG chain for each XCore: the boundary scan TAP
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12
SS_XC0_BS[0]
Boot Mode
0
Boot from SPI
PinA
Signal
Description
X0D00
MISO
Master In Slave Out
X0D01
SS
Slave Select
Figure 4:
X0D10
SCLK
Clock
Boot source
X0D11
MOSI
Master Out Slave In
pins
1
None: Device waits to be booted from JTAG
A The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. An SPI boot
program can be burned into OTP and used at any time.
Figure 5:
Boot mode
SS_XC0_BS[0]
Boot Confirmation
indication
0
Booted from SPI
pins
1
Booted from OTP or JTAG
and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that
can be used for boundary scan of the I/O pins. The chip TAP provides access into
the XCore, switch and OTP for loading code and debugging.
SS_TRST SS_TCK
SS_TD!
SS_TMS
SS_TDO
SS_TMS
SS_TCK
SS_TRST
SS_TDI
SS_TDO
MUX controller
NC
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
SS_TMS SS_TCK SS_TRST
Figure 6:
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
SS_TDI
SS_TDO
JTAG chain
X0 JTAG
X1 JTAG
X2 JTAG
X3 JTAG
Switch JTAG
structure
The SS_TRST pin must be asserted low during and after power up for 100 ns. If
JTAG is not required, the SS_TRST pin can be tied to ground with a 1k resistor to
hold the JTAG module in reset.
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The JTAG device identification register can be read by using the IDCODE instruction.
Its contents are specified in Figure 7.
Bit31
Device Identification Register
Bit0
Figure 7:
Version
Part Number
Manufacturer Identity
1
ICODE return
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
value
0
0
1
0
4
6
3
3
The JTAG usercode register can be read by using the USERCODE instruction. Its
contents are specified in Figure 8. The OTP User ID field is read from bits [22:31]
of the security register on XCore 0 (all zero on unprogrammed devices).
Bit31
Usercode Register
Bit0
Figure 8:
OTP User ID
Unused
Silicon Revision
USERCODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
return value
0
0
0
2
8
0
0
0
5.10
Power Supplies
The device has the following types of power supply pins:
· VDD pins for the chip core
· IO VDD pins for the I/O lines
· SS_PLL_AVDD pins for the PLL
· OTP_VPP pins for faster programming the OTP (optional)
Several pins of each type are provided to minimize the effect of inductance within
the package, all of which must be connected. The power supplies must be brought
up monotonically and input voltages must not exceed specification at any time.
The VDD supply must ramp from 0 V to its final value within 10 ms to ensure
correct startup.
The IO VDD supply must ramp to its final value before VDD reaches 0.4 V.
The SS_PLL_AVDD supply should be separated from the other noisier supplies on
the board. The PLL requires a very clean power supply, and a low pass filter (for
example, a 4.7 resistor and 1 µF multi-layer ceramic capacitor) is recommended
on this pin.
The SS_OTP_VPP supply can be optionally provided for faster OTP programming
times, otherwise an internal charge pump is used.
The following ground pins are provided:
· PLL_AGND for PLL_AVDD
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XS1-G04B-FB144 Datasheet
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· GND for all other supplies
All ground pins must be connected directly to the board ground.
The VDD and IO VDD supplies should be decoupled close to the chip by several
100 nF low inductance multi-layer ceramic capacitors between the supplies and
GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The
ground side of the decoupling capacitors should have as short a path back to the
GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be
placed on each of these supplies.
SS_RESET is an active-low asynchronous-assertion global reset signal. Following a
reset, the PLL re-establishes lock after which the device boots up according to the
boot mode (see §5.8). SS_RESET and must be asserted low during and after power
up for 100 ns.
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XS1-G04B-FB144 Datasheet
15
6
DC and Switching Characteristics
6.1
Operating Conditions
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
VDD
Core DC supply voltage
0.95
1.00
1.05
V
VDDIO
I/O DC supply voltage
3.00
3.30
3.60
V
PLL_AVDD
PLL analog supply
0.95
1.00
1.05
V
OTP_VPP
OTP external programming
6.18
6.50
6.83
V
voltage (optional program only)
Cl
XCore I/O load capacitance
25
pF
Ambient operating
0
70
°C
Ta
temperature (Commercial)
Ambient operating
-40
85
°C
Figure 9:
temperature (Industrial)
Operating
Tj
Junction temperature
125
°C
conditions
Tstg
Storage temperature
-65
150
°C
6.2
DC Characteristics
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
V(IH)
Input high voltage
2.00
5.50
V
A, B
V(IL)
Input low voltage
-0.30
0.80
V
A, B
Figure 10:
V(OH)
Output high voltage
2.40
V
A, B
DC character-
V(OL)
Output low voltage
0.40
V
A, B
istics
R(PU)
Pull-up resistance
100K
A, C
A All pins except power supply pins.
B Internal pull-up resistors are fitter to general-purpose I/O pins.
C Use for unused I/O only. The internal pull-up resistor is not recommended as a substitute for an
external pull-up resistor.
6.3
ESD Stress Voltage
Figure 11:
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
ESD stress
HBM
Human body model
-2.00
2.00
KV
voltage
MM
Machine model
-200
200
V
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XS1-G04B-FB144 Datasheet
16
6.4
Reset Timing
Symbol
Parameters
MIN
TYP
MAX
UNITS
Notes
T(RST)
Reset pulse width
100
ns
Figure 12:
T(PLLLOCK)
PLL lock
1
ms
Reset timing
T(INIT)
Initialization time
<100
µs
A
A Shows the time taken to start booting after SS_RESET has gone high.
6.5
Quiescent Current
Figure 13:
Symbol
Parameter
MIN TYP MAX
UNITS
Notes
Quiescent
I(DDCQ)
Quiescent VDD current
120
mA
current
I(PLLQ)
Quiescent PLL current
4
mA
6.6
Power Consumption
Figure 14:
Symbol
Parameter
MIN TYP MAX
UNITS
Notes
Core currents
PD
Core power dissipation
1.6
Watts
A, B, C, D
A Use for budgetary purposes only.
B Assumes typical core and I/O voltages operating at 400 MHz with nominal activity on all cores.
C PD(TYP) value is the usage power consumption under typical operating conditions.
D PD(TYP) value includes quiescent current.
The core power consumption of the device is highly application dependent and
should be used for budgetary purposes only. More detailed power analysis can be
found in the XS1-G Power Consumption document, document number X1423.
6.7
Clock
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
f
Frequency
12.5
20
20
MHz
Figure 15:
SR
Slew rate
1
2
ns
Clock
f(MAX)
System clock frequency
400
MHz
Further details can be found in the XS1-G Clock Frequency Control document,
document number X140.
The OTP may be programmed using its internal charge pump or by supplying a
6.5V VPP programming voltage on the SS_OTP_VPP pin. Unless a programming
cycle is underway the SS_OTP_VPP pins should be left undriven.
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XS1-G04B-FB144 Datasheet
17
6.8
XCore I/O AC Characteristics
Symbol
Parameter
MIN TYP MAX UNITS
Notes
T(XOVALID)
Input data valid window
8
ns
Figure 16:
T(XOINVALID)
Output data invalid window
9
ns
I/O AC char-
T(XIFMAX)
Rate at which data can be sampled
60
MHz
acteristics
with respect to an external clock
The input valid window parameter relates to the capability of the device to capture
data input to the chip with respect to an external clock source. It is calculated as the
sum of the input setup time and input hold time with respect to the external clock
as measured at the pins. The output invalid window specifies the time for which
an output is invalid with respect to the external clock. Note that these parameters
are specified as a window rather than absolute numbers since the device provides
functionality to delay the incoming clock with respect to the incoming data.
Information on interfacing to high-speed synchronous interfaces can be found in
the XS1 Port I/O Timing document, document number X9122.
6.9
XMOS Link Performance
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
B(2blinkP)
2b link bandwidth (packetized)
87
MBit/s
A, B
Figure 17:
B(5blinkP)
5b link bandwidth (packetized)
217
MBit/s
A, B
Link
B(2blinkS)
2b link bandwidth (streaming)
100
MBit/s
B
performance
B(5blinkS)
5b link bandwidth (streaming)
250
MBit/s
B
A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header
and payload.
B 7.5 ns symbol time.
The asynchronous nature of links means that the relative phasing of SS_CLK clocks
is not important in a multi-clock system, providing each meets the required stability
criteria.
6.10
JTAG Timing
Symbol
Parameter
MIN
TYP
MAX
UNITS
Notes
T(TCK)
TCK period
30
ns
T(SETUP)
TDO to TCK setup time
5
ns
A
Figure 18:
T(HOLD)
TDO to TCK hold time
10
ns
A
JTAG timing
T(DELAY)
TCK to output delay
15
ns
B
A Timing applies to SS_TMS, SS_TRST and SS_TDI inputs.
B Timing applies to SS_TDO output.
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XS1-G04B-FB144 Datasheet
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All JTAG operations are synchronous to SS_TCK apart from the global asynchronous
reset SS_TRST.
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XS1-G04B-FB144 Datasheet
19
7
Package Information
Document Number: 1087C
XS1-G04B-FB144 Datasheet
20
7.1
Part Marking
Product code
Qualification/Speed Grade (optional)
XS1ÂG04BÂFB144Â
Q S
XMOS-YYWW
Manufacturing date code
LLLLLL.LL
Figure 19:
Part marking
Lot code
scheme
8
Ordering Information
Figure 20:
Product Code
Qualification
Speed Grade
Orderable
XS1ÂG04BÂFB144ÂC4
Commercial
400 MHz
part numbers
XS1ÂG04BÂFB144ÂI4
Industrial
400 MHz
9
Development Tools
XMOS provides a comprehensive suite of development tools. Source files, timing
scripts and a board design file are input to the compiler toolchain which produces
a binary executable. This executable file can be simulated, loaded onto the device
and debugged over JTAG, programmed into flash memory on the board or written
to OTP memory on the device. The tools can also encrypt the flash image and write
the decrpytion key securely to OTP memory.
The tools can be driven from either a graphical development environment or the
command line and are supported on Windows, Linux and MacOS X. The tools
are available at no cost from xmos.com/tools. Information on using the tools is
provided in a separate user guide, document number X1066.
10
Addendum: XMOS USB Interface
XMOS provides a low-level USB interface for connecting the device to a USB
transceiver using the UTMI+ Low Pin Interface (ULPI). The ULPI signals must be
connected to the pins named in Figure 21. Note also that some ports on the same
Document Number: 1087C
XS1-G04B-FB144 Datasheet
21
core are used internally and are not available for use when the USB driver is active
(they are available otherwise).
Pin
Signal
Pin
Signal
Pin
Signal
XnD02
XnD16
ULPI_DATA[2]
XnD30
XnD03
XnD17
ULPI_DATA[3]
XnD31
XnD04
XnD18
ULPI_DATA[4]
XnD32
XnD05
XnD19
ULPI_DATA[5]
XnD33
Unavailable
XnD06
XnD20
ULPI_DATA[6]
XnD37
XnD07
XnD21
ULPI_DATA[7]
XnD38
Unavailable
XnD08
XnD22
ULPI_DIR
XnD39
XnD09
XnD23
ULPI_CLK
XnD40
Figure 21:
XnD12
ULPI_STP
XnD26
XnD41
ULPI signals
provided by
XnD13
ULPI_NXT
XnD27
XnD42
Unavailable
the XMOS
XnD14
ULPI_DATA[0]
XnD28
XnD43
USB driver
XnD15
ULPI_DATA[1]
XnD29
11
Associated Design Documentation
Document Title
Information
Document Number
XS1-G Hardware Design Checklist
Board design checklist
X0124
Device Package User Guide
Land pattern, solder paste, ground
X4979
recommendations
Estimating Power Consumption For
Power consumption
X1423
XS1-G Devices
Programming XC on XMOS Devices
Timers, ports, clocks, threads and
X1066
channels
XMOS Tools User Guide
Compilers, assembler and
X1089
linker/mapper
Timing analyzer and debugger
Flash and OTP programming utilities
· Example schematic diagrams detailing minimal system configurations are available from
http://www.xmos.com/support/silicon.
Document Number: 1087C
XS1-G04B-FB144 Datasheet
22
12
Related Documentation
Document Title
Information
Document Number
The XMOS XS1 Architecture
ISA manual
X0102
XS1 Port I/O Timing
Port timings
X9122
XS1-G System Specification
Link, switch and system information
X2725
XS1-G Link Performance and Design
Link timings
X2215
Guidelines
XS1-G Clock Frequency Control
Advanced clock control
X1340
Document Number: 1087C
XS1-G04B-FB144 Datasheet
23
13
Revision History
The page numbers in this section refer to this document.
Rev. 1087CÂ05/11
1. Revised format.
2. Standard XMOS Link format XnLn on page 4.
Rev. 1087BÂ01/11
1. Replaced "Port Pin Table" with "Signal Description" on page 4.
2. Updated "ULPI" on page 20 with set of disabled signals.
3. Removed "Device Configuration".
4. Added "Associated Design Documentation" on page 21.
5. Clock frequencies of betweeen 20 MHz and 25 MHz are not supported.
6. Removed documentation of numerous JTAG commands, which were incorrect.
7. Updated Figure 10 in "DC Characteristics" on page 15 by removing rows for I(OH) and
I(OL).
8. Updated Figure 17 in "XMOS Link Performance' on page 17 by removing rows for B(2link)
and B(5link), and adding rows for B(2linkP), B(5linkP), B(2linkS) and B(5linkS).
9. Renamed IO VSS signals to VSS.
Rev. 1087AÂ06/10
1. Revised format.
2. Updated "Power Consumption" on page 16.
Copyright © 2010 XMOS Limited, All Rights Reserved.
XMOS Limited is the owner or licensee of this design, code, or Information (collectively, the "Information")
and is providing it to you "AS IS" with no warranty of any kind, express or implied and shall have no
liability in relation to its use. XMOS Limited makes no representation that the Information, or any particular
implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Limited in the United Kingdom and other
countries, and may not be used without written permission. All other trademarks are property of their
respective owners. Where those designations appear in this book, and XMOS was aware of a trademark claim,
the designations have been printed with initial capital letters or in all capitals.
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