XS1-L2 124QFN Package

The XS1-L2 is a member of the XS1-L family of XMOS devices. The XS1-L family blends a powerful programmable fabric based on multi-threaded processors with a high-level programming language design flow. XMOS chips are general-purpose programmable devices that can be used in a wide range of applications and systems.

The XS1-L2 device is based on the XMOS XCore. Each XCore contains a 32-bit processor, SRAM memory, I/O ports for communicating with external components and channels for communicating with other devices.

OTP memory is provided for application boot code and security keys, with a secure mode that disables debug and prevents read-back of memory contents. High performance switches support low latency and deterministic communication between the threads in different XCores.

The XMOS architecture is unique in its direct support for concurrent processing (multi-threading), event handling, communication and timed I/O operations.