How xCORE Works

The xCORE multicore microcontroller is made up from Tiles that contain multiple 32bit ‘logical processor cores’. [Please note: that we sometimes refer to logical processor cores as 'Threads' in some of our older documentation] Devices are currently available with 1 , 2 and 4 tiles which provide respectively 8, 16 and 32 logical processor cores. The xCORE Tile provides 500MIPs of compute (on a 500MHz device) making it much more powerful than conventional microcontroller products. The logical processor cores share processing resources and memory on the Tile, but each has separate register files. Each logical processor core gets a guaranteed slice of processing power (up to 125 MIPS on a 500MHz device), which is controlled by the unique xTIME timing and synchronization technology. The time-slicing is executed in a such a way that it is completely transparent and the logical processor cores appear as separate, parallel processors, capable of running multiple real-time tasks simultaneously. In fact it is the xTIME technology that gives xCORE its unique timing predictability and real-time responsiveness.

Devices are available at different speeds running at up to 500MHz (with 700MHz devices available soon). Each logical processor can operate at up to one quarter of the clock frequency: 125MIPS on a 500MHz device. When four logical processor cores execute simultaneously, all the cores will be able to run at 125 MIPS. When more logical processor cores execute simultaneously, the MIPS rate per core reduces, and with eight logical cores running each core has 62.5 MIPS. This gives each logical processor core roughly the equivalent compute of a conventional high performance 32bit microcontroller. One way to visualize the xCORE multicore microcontroller is to think of it as an 8-pack, 16-pack, or 32-pack of high performance 32bit microcontrollers.

The xCORE architecture allows multiple tiles to be connected in a single devices and for multiple devices to be joined together. Tiles are connected to each other using an on-chip high-speed interconnect – called xCONNECT. XMOS provides a range of devices that include a single tile with 8 logical processor cores, and devices with multiple tiles, delivering 16 and 32 logical processor cores. Within a tile, tasks running on separate logical processor can use shared memory to exchange data with other tasks. Logical processor cores can also use channels to exchange data and synchronize timing. Channels can be extended, using xCONNECT, to allow data and timing synchronization between tiles and even between separate devices. This allows you to transparently create a system with more resources—more I/O pins, more memory, or additional processing power. For guaranteed real-time performance, single cycle instructions can exchange a word of data between logical cores, implicitly synchronizing the receiver with the sender. If shared memory is used, tasks can use single cycle lock-instructions to ensure synchronization.